Chapter 5 Cooling of Power Switching Semiconductor Devices 136

Conduction heat transfer

Conductive heat transfer occurs when energy exchange takes place, by direct impact of molecules, from a
high temperature region to a low temperature region.
Conductive heat loading on a system may occur through lead wires, mounting screws, etc., which form a
thermal path from the device being cooled to the heat sink or ambient environment.

5
The one-dimensional model for general molecular (non-radiation) heat transfer is given by

CHAPTER Pd   A
T

 m A
T
t
(W)
where δT =T2 -T1 or ΔT, is the temperature difference between two regions of heat transfer
(5.2)

λ is thermal conductivity, W/m K, see Appendix 5.11

ρm is density of the heatsink material
Cooling cp is specific heat capacity, J/kg K, such that ΔT = W/mcp
is distance (thickness).
(W is energy, m is mass)

of Equation (5.2) shows that the thermal power generated Pd is balanced by the stored thermal power (first
term on the right hand side) and the thermally dissipated power (second term on the right hand side).

Power Switching Semiconductor Devices Assuming steady-state heat dissipation conditions, then T /  t  0 in equation (5.2).

Conduction through a homogeneous solid, from Fourier’s law of heat conduction, is therefore given by
dT 
Pd   A  A T (W) (5.3)
dx

Convection heat transfer

When the temperature of a fluid (a gas or liquid) flowing over a solid object differs from that of the object
surface, heat transfer occurs. The amount of heat transfer varies depending on the fluid flow rate.
Convective heat loads are generally a result of natural (or free) convection. This is the case when gas flow
is not artificially created as by a fan or pump (forced convection), but rather occurs naturally from the
Semiconductor power losses are dissipated in the form of heat, which must be transferred away from the varying density in the gas caused by the temperature difference between the object being cooled and the
switching junction, if efficient switching is to be maintained. The reliability and life expectancy of any power gas. Heat transfer processes that involve change of phase of a fluid (for example evaporation or
semiconductor are directly related to the maximum device junction temperature experienced. It is condensation) are also considered to be convection.
therefore essential that the thermal design determine accurately the maximum junction temperature from The convective loading is a function of the exposed area and the difference in temperature between the
the device power dissipation. Every 10°C junction temperature decrease, doubles device lifetime. load and the surrounding gas. Convective loading is usually most significant in systems operating in a
gaseous environment with small active loads or large temperature differences.
i. Heat load
The heat load may be active or passive, then there is a combination of the two. An active load is the heat Convection heat transfer through a fluid or air, under steady-state conditions in equation (5.2), is given by
dissipated by the device being cooled. It is generally equal to the input power to the device, for example, Newton’s law of cooling, that is
P  V  I  I 2  R  V 2 / R . Passive heat loads are indirect, are parasitic in nature, and may consist of Pd  h A T (W) (5.4)
radiation, convection or conduction. The convection heat transfer coefficient h (= λ / ℓ), W/m K, depends on the heat transfer mechanism used
2
Heat energy, due to a temperature difference, can be transferred by any of, or a combination of, three and various factors involved in that particular mechanism. It is not a property of the fluid.
mechanisms, viz., Natural or free convection is essentially still to slightly stirred air with h values ranging from 1 to 25. Forced
 Convection - heat transferred to a moving fluid which takes the heat away convection is air moved by a fan or other active method, giving h values ranging from 10 to 100. Values for
 Conduction - heat flows through a thermal conducting material, away from the heat source forced liquid convection are 50 to 20,000, while the h range for boiling and condensation is 2,500 to
 Radiation - heat flow by long-wave electromagnetic radiation, e.g. infrared. 100,000.
Electromagnetic thermal radiation heat transfer
When two objects at different temperatures come within proximity of each other, heat is exchanged For natural vertical convection in free air, the losses for a plane surface may be approximated by the
between them. Electromagnetic wave propagation, radiation is emitted from one object and absorbed by following empirical formula
the other. As a result of the temperature difference, the hot object experiences a net heat loss and the cold T 5
T
object undergoes a net heat gain. This is termed thermal radiation. Pd  1.35A 4
 1.35 A 4 T  hA T (W) (5.5)

Radiation heat loads are usually considered insignificant when the system is operated in a gaseous where ℓ is the vertical height in the direction of the airflow and h is of the form
¼
environment since other passive heat loads are usually greater. Radiation loading is usually significant in  T 
h K   (5.6)
systems with small active loads and large temperature differences, especially when operating in a vacuum  
environment, where convection processes are absent.
Two cases occur for forced airflow, and the empirical losses are
Electromagnetic thermal radiation heat loading (for a grey body, ε < 1) is given by  for laminar flow
Pd    A (T14 T 24 ) (5.1) v
where Pd is the rate of radiated heat transfer (that is, the power dissipated), W Pd  h A T  3.9 A T (W) (5.7)
σ is the Stefan-Boltzmann constant (5.667×10 W/m K )
-8 2 4
 for turbulent flow
ε is a surface property, termed emissivity, 0 ≤ ε ≤ 1, see Table 5.6 and Appendix 5.11
2 4
A is the surface area involved in the heat transfer, m 5v
Pd  h A T  6.0 A T (W) (5.8)
T is absolute temperature, K
The ideal emitter, or black body, is one which gives off radiant energy with ε = 1 in equation (5.1). where v is the velocity of the vertical airflow.

BWW
137 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 138

Combined convection and conduction heat transfer For convection, from equation (5.4), the effective thermal resistance is
Heat Loss (or gain) - through the walls of an insulated container (combined convection and conduction, T 1
estimation) is R   (5.13)
Pd hA
T
Pd  A  For radiation, from equation (5.1), the effective thermal resistance of radiation is
/  1/h T 1 1
R    (5.14)
 A  T1  T 2  T12  T 22  hr A
where Pd is the heat lost or gained, W
Pd
ℓ is the thickness of insulation, m 2
λ is the thermal conductivity of the insulation material, W/m K where the radiation heat transfer coefficient, hr, in W/m K, is
hr    T 1  T 2  T 12  T 22   4   T mean
2
A is the outside surface area of the container, m . 3
(5.15)
2
h is the convection heat transfer coefficient of the surface material, W/m K
where Tmean is the arithmetic mean of T1 and T2, specifically ½( T1 + T2).
ΔT= To/s - Ti/s
To/s is the outside temperature, °C
Ti/s is the inside temperature, °C
5.1 Thermal resistances

A general thermal dissipation model or thermal equivalent circuit for a mounted semiconductor is shown in
ii. Transient heating figure 5.1. The total thermal resistance from the virtual junction to the open air (ambient), Rθ j-a, is
Some designs require a set amount of time to reach the desired temperature.
R  (R c-s  R c-a )
The estimated time required to heat (or cool) an object (also known as Newton’s Law of Cooling) is R j-a  R j-c   c-a (K/W) (5.16)
m  c p  T R c-a  R c-s  R s-a
t 
P
P is the mean heat added (or being removed) from the object, W, watts In applications where the average power dissipation is of the order of a watt or so, power semiconductors
m is the mass (weight) of the object, kg (density x volume) can be mounted with little or no heat sinking, whence
cp is the specific heat of the object material, J/kg K R j-a  R j-c  R c-a (K/W) (5.17)
t is the time required to cool down (or heat up) the object in seconds Generally, when employing heat sinking, Rθ c-a is large compared with the other model components and
ΔT = To – Tf equation (5.16) can be simplified to three series components:
To is the starting temperature, °C R j-a  R j-c  R c-s  R s-a (K/W) (5.18)
Tf is the final temperature, °C

P  ½ Pt o  Ptt 
Pto is the initial heat pumping capacity when the temperature difference across the cooler is zero.
Ptt is the heat pumping capacity when the desired temperature difference is reached and heat-pumping virtual Tjunction
capacity is decreased. junction Rθ c-a
Heat loading may occur through one or more of four modes: active, radiation, convection or conduction. By
package Tcase Rθ j-c
utilizing these equations, the heat load can be estimated. case at
mount
iii. Thermal resistance Rθ c-hs
heatsink Theatsink
It is generally more convenient to work in terms of thermal resistance, which is defined as the ratio of
temperature change to power. Thermal capacity is the reciprocal of thermal resistance. For conduction,
from equation (5.4), thermal resistance Rθ is
T 1
R    (K/W) (5.9)
Pd hA A
where the conduction thermal heat transfer coefficient, h, is Rθ hs-a

h  (5.10) ambient Tambient

The average power dissipation Pd and maximum junction temperature T j , in conjunction with the ambient
temperature Ta, determine the necessary heat sink, according to equation (5.9)

T T j Ta Figure 5.1. Semiconductor thermal dissipation equivalent circuit.
Pd   (W) (5.11)
R j-a R j-a

where Rθ j-a is the total thermal resistance from the junction to the ambient air. The device user is restricted 5.2 Contact thermal resistance, Rθ c-s
by the thermal properties from the junction to the case for a particular package, material, and header
mount according to The case-to-heat-sink thermal resistance Rθ c-s (case means the device thermal mounting interface
 surface) depends on the package type, interface flatness and finish, mounting pressure, and whether
T T Tc thermal-conducting grease and/or an insulating material (thermal interface material, TIM) is used. In
Pd   j (W) (5.12)
R j-c R j-c general, increased mounting pressure decreases the interface thermal resistance, and no insulation other
where Tc is the case temperature, K and than thermal grease results in minimum Rθ c-s. Common electrical insulators are mica, aluminium oxide,
Rθ j-c is the package junction-to-case mounting thermal resistance, K/W. and beryllium oxide in descending order of thermal resistance, for a given thickness and area. Table 5.1
shows typical contact thermal resistance values for smaller power device packages, with various
An analogy between the thermal (and magnetic) equations and Ohm’s law and Kirchhoff’s laws is often insulating and silicone grease conditions. Silicon based greases are best, for example Assmann V6515,
made to form models of heat flow. The temperature difference ΔT could be thought of as a voltage drop spread at a thickness of 100μm to 150μm, on both surfaces. Grease in excess of this will be squeezed out
ΔV, thermal resistance Rθ corresponds to electrical resistance R, and power dissipation Pd is analogous to under clamping pressure. Initial grease thermal resistance decreases slightly after a few normal deep
electrical current I. [viz., ΔT = Pd Rθ ≡ ΔV = IR]. See Table 5.10. thermal cycles.
139 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 140

Table 5.1: Typical case-to-heat-sink thermal resistance value for various small packages  Cure-in-Place Thermally Conductive Compounds
A thermally conductive compound again incorporates thermally conductive ceramic fillers, shown in
Rθc-s (K / W) Table 5.3, but unlike thermal greases, the binder is a rubber material. When first applied, the
Package Insulating washer paste-like compound flows into the interstices between the mating surfaces. Then, when subjected
Silicone grease
with without to heat, it cures into a dry rubber film. Besides its thermal properties, this film also serves as an
No insulating washer
adhesive, allowing a tight, void-free joint without the need for additional fasteners. Thermally
0.10 0.3
TO-3 Teflon 0.7-0.8 1.25-1.45 conductive compounds can fill larger gaps in situations where thermal greases might ooze from the
Mica (50 - 100 μm) 0.5-0.7 1.2-1.5 joint. Although application and performance is similar to that of thermal grease, cleanup is easier,
simply involving removal of the excess cured rubber film.
No insulating washer 0.3-0.5 1.5-2.0
TO-220
Mica (50 - 100 μm) 2.0-2.5 4.0-6.0
No insulating washer
 Thermally Conductive Elastomeric Pads
0.1-0.2 0.4-1.0
TO-247 A thermally conductive elastomeric pad consists of a silicone elastomer filled with thermally
Mica (50 - 100 μm) 0.5-0.7 1.2-1.5
conductive ceramic particles and may incorporate woven glass fibre or dielectric film reinforcement.
SOT-227 No insulating washer 0.1-0.2 0.3-0.4
Typically ranging in thickness from 0.1 to 5 mm and in hardness from 5 to 85 Shore A, these pads
ISOTOP Mica (50 - 100 μm) 0.5-0.7 1.0-1.2
provide both electrical insulation and thermal conductivity, making them useful in applications
requiring electrical isolation. Thicker pads prove useful when large gaps must be filled. During
application, the pads are compressed between the mating surfaces to make them conform to
The thermal resistance of a heat-conducting layer is inversely proportion to heat conductivity of the
surface irregularities. Mounting pressure must be adjusted according to the hardness of the
material and in direct ratio to its thickness. If the clamping pressure is increased, the layer thermal
elastomer to ensure that voids are filled. A mechanical fastener is essential to maintain the joint
resistance falls. In figure 5.2, the exemplary dependence of the gasket thermal resistance per surface unit
once assembled.
on pressure is shown. However, with a growth of pressure it is necessary to find an optimum, as the
clamping effort should not exceed a package recommended value or introduce differential thermal
 Thermally Conductive Adhesive Tapes
expansion problems into the clamping arrangement.
A thermally conductive adhesive tape is a double-sided pressure sensitive adhesive film filled with
thermally conductive ceramic powder. To facilitate handling, aluminium foil or a polyamide film may
Thermal resistance K/m W pu

support the tape; the latter material also provides electrical insulation. When applied between
1 mating surfaces, the tape must be subjected to pressure to conform to the surfaces. Once the joint
is made, the adhesive holds it together permanently, eliminating the need for supplemental
2

0.9
fasteners. No bond curing is needed. One limitation of thermally conductive tapes is that they
0.8
cannot fill large gaps between mating surfaces as well as liquids; hence, the convenience of tape
0.7 mounting is traded against a nominal sacrifice in thermal performance.
0.6
 Phase Change Materials
0.5 Solid at room temperature, phase change materials, shown in Table 5.3, melt (that is, undergo a
phase change) as the temperature rises to the 40° to 70°C range. This makes the material (0.13
mm thick in its dry film form) as easy to handle as a pad, while assuring, when subjected to heat
0 50 100 150 200
during the assembly process, the melt flows into voids between mating surfaces as effectively as a
Pressure psi thermal grease. Applying power to the power electronic component introduces the needed heat for
Figure 5.2. Exemplary dependence of the gasket thermal resistance on clamping pressure.
the phase change to occur, establishing a stable thermal joint. These materials consist of organic
binders (that is, a polymer and a low-melt-point crystalline component, such as a wax), thermally
conductive ceramic fillers, and, if necessary, a supporting substrate, such as aluminium foil or
woven glass mesh. See section 5.2.2 for further details.
5.2.1 Thermal interface materials

To be effective, heatsinks require intimate surface-to-surface contact with the component to be cooled.
Unfortunately, irregular surface areas, both on the electronic components and on the heatsink mating Table 5.2: Thermal Interface Material (TIM) thermal resistances
surface prevent good contact. Up to 99% of the surfaces are separated by a layer of interstitial air, which is
a poor conductor of heat thus presents a thermal barrier. Therefore, a thermally conductive interface Thickness Thermal Conductivity Thermal resistance Thermal resistance
material is necessary to fill the interstices and microvoids between the mating surfaces. To ensure that Interface λ Rθc-s pu area
electrical problems are not inadvertently introduced while solving the thermal problems, it is often essential mm W / m.K K/W
2
K cm /W
that the thermal interface materials also perform an electrical isolation function. Dry Joint n/a n/a 2.9 1.8 - 2
Thermal interface materials TIMs vary widely in terms of performance (that is, thermal, electrical, and
physical properties), general appearance, and mode of application. Among the most commonly used Thermal Grease 0.076 0.7 0.9 0.5 - 1.1
classes of thermal interface materials are: thermal greases, cure-in-place thermally conductive Thermal Compound 0.127 1.2 0.8 0.2 - 0.7
compounds, gap filling thermally conductive elastomeric pads, thermally conductive adhesive tapes, and
phase change materials, all of which are summarised in Table 5.2 and are briefly described. Elastomer 0.254 5.0 1.8 1-2
Adhesive Tape 0.229 0.7 2.7 0.5 - 1.5
 Thermal Greases
Comprised of thermally conductive ceramic fillers in silicone or hydrocarbon (organic) oils, as Eutectic (soldering)
61 0.1
Sn(91) Zn(9)
shown in Tables 5.3a and b, a thermal grease is a paste, which is applied to at least one of the two
mating surfaces. When the surfaces are pressed together, the grease spreads to fill the void. During
compression, excess grease squeezes out from between the mated surfaces. Some form of clip or
other mounting hardware is needed to secure the joint. Although it is comparatively inexpensive and
thermally effective, thermal grease is not an electrical insulator. Disadvantageously, it can be
inconvenient to dispense and apply, and requires cleanup to prevent contamination problems.
 141 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 142

Table 5.3: Thermal Interface material (TIM) parameters PCM displaces the interstitial air and the distance between the surfaces decreases. Both of these
processes act to reduce the thermal resistance of the interface and the temperature difference is seen to
decrease rapidly, reaching the performance of thermal grease, 4°C. In effect, the solid PCM film has
Thermal Temperature turned into thermal grease and a grease-like joint has been formed. The next time the thermal load is
Material parameters Resistivity Thickness Lifetime
Conductivity range activated, the interface does not experience the large temperature difference because the void free
(a) Thermal grease λ, W / mK ρ, Ω.cm °C mm thermal joint has already been established.
14
Zinc Oxide/Silicone 0.74 > 5×10 < 150 5 years @ 25C
Aℓ203 / Non-Silicone
13
2 > 10 < 150 1 year @ 25°C
AℓN / Non-Silicone 4 > 10
13
< 150 1 year @ 25°C 15

13

°C
Non-silicone paste 2 > 1×10 n/a 1 year @ 25°C Dry interface joint
14
Silicone paste > 4.0 > 1×10 n/a 1 year @ 25°C
10
13
Non-curing paste 4 > 1×10 n/a n/a

Theatsink
Non-silicon Phase Change
> 7.5 1Å -50…+150 n/a
polysynthetic oils Material
14
thermal phase change 0.90 1×10 -50…+200 n/a 5

Tcase -
13
Silicone 0.8-1.2 1×10 -60…+180 5 years
Grease
(b) Heat conducting Tensile
gaskets Strength 0
psi
14
0 300 600
Silicon/Alumina filled 0.38 1×10 -60…+150 0,08 3000
Time seconds
14
Silicon/Boron Nitride 2.07 1×10 -60…+200 0,25 1000
Figure 5.3. Performance of a PCM, compared to a dry interface joint and thermal grease.
Aℓ2O3 filled 1.7 n/a < +150 0,10 15…300
AℓN filled 3.6 n/a < +150 0,10 15…300
The thermal resistance across an interface depends on the thermal conductivity of the PCM in the
97% Graphite filled 5 n/a < +450 0,13 15…300
interface and its conductive path length. Thermal conductivity is a function of the type and level of the
(c) Phase changing
Clamping
Phase Change ceramic filler in the formulation, typically between 0.7 and 1.5 W/m.K. The amount of filler that can be
heat conducting Temperature added is limited by the need to keep the viscosity as low as possible to achieve proper flow of the PCM in
psi
gaskets °C the interface. The thickness of the interface formed by a PCM is determined by the flatness of the mating
Black/self-adhesive layer 0.7 n/a < +120 0.077 10…200 < +120 surfaces, the clamping pressure, and the viscosity and rheology of the molten PCM. Most commercial
surfaces deviate from true flatness by as much as 2µm/mm. This means that the thermal path between a
20…60
15
Grey/self-adhesive layer 1.0 5×10 -60…+125 0.13 -60…+125
module surface and the heatsink may be as much as 100µm, and more with large heatsinks. Critical
50…300
14
Grey/self-adhesive layer 0.6 5×10 -60…+125 0.18 -60…+125 applications may require a better surface flatness through additional machining operations to reduce the
thermal path.
Grey/self-adhesive layer 3 n/a n/a 0.11 n/a n/a
The viscosity and the rheology of the PCM above its melt point represent another factor determining the
thickness of the interface. As the PCM melts in the interface, the pressure applied by the mounting clamps
forces the liquid to spread, eliminating the interstitial air and allowing the space between the two surfaces
to decease. If the viscosity is high, the low force of the clamps will be insufficient to cause sufficient
5.2.2 Phase change gasket materials (solid to liquid) spreading and the conduction path will be long. Low viscosity on the other hand will allow the liquid to fill
The inavertable heat produced by power electronics necessitates a carefully designed thermal path along most of the joint, resulting in the thinnest joint. Using a stronger mounting force will aid the spreading
which all of the thermal resistances are minimized. For the case-to-heatsink interface, this requires that process, but there is a package limit as to the amount of pressure that can be applied.
thermal grease be used to minimize the interface resistance. Phase change materials, PCMs, are an Phase change materials offer the same thermal performance as thermal grease without the mess and
alternative to the messy application and migration problems associated with thermal grease. contamination associated with grease. They can be supplied attached to a heatsink as a dry film. As soon
The term phase change describes a class of materials that are solid at room temperature and change to a as they are heated above their phase change temperature, they melt and perform as well as, or often
liquid as temperature increases. This phase change, or melting, occurs in the range of 40 to 70°C. PCMs better than, thermal grease. Once this interface has been formed, it remains stable until the sink is
are composed of a mixture of organic binders, fine particle ceramic fillers for thermal enhancement, and, physically separated from the power module case-mounting surface.
optionally, a supporting substrate, such as aluminium foil or a woven glass mesh. The organic binder is a
blend of a polymer and a low-melt-point crystalline component, such as a wax. The ceramic fillers may be
Aℓ203, BN, AℓN or Zn0.
5.3 Heat-sinking thermal resistance, Rθ s-a
The way a PCM performs compared to a dry interface joint and thermal grease is illustrated in figure 5.3,
where the case to heatsink temperature difference is plotted against elapsed time after the The thermal resistance for a flat square plate heat sink may be approximated by
commencement of power dissipated. The curve representing the dry interface shows rapid thermal 3.3 ¼ 650
equilibrium at about 13°C. The curve involving the use of thermal grease shows the same rapid rise to R s-a  Cf  C (K/W) (5.19)
b A f
thermal steady-state but at a lower temperature difference of 4°C. The thermal grease significantly
reduces the interface resistance by eliminating the interstitial air.
Typical values of heatsink thermal conductance λ in W/K cm at 350 K, are shown in Appendix 5.11 and
The PCM - a 0.1 mm thick dry film - behaves as a combination of the two interfaces. Initially at power up,
b is the thickness of the heat sink, mm
the cool components give the dry interface behaviour, with the temperature difference rapidly increasing to 2
about 12°C. As the system temperature increases, the PCM melts and the clamping pressure exerted by A is the area of the heat sink, cm
the clamping mechanism forces the liquid to spread in the thermal joint. As the liquid spreads, the molten Cf is a correction factor for the position and surface emissivity of the
heat-sink orientation according to Table 5.4.
143 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 144

Table 5.6: Emissivity coefficient of As the base flow height H is increased, the air at the top of a vertical heatsink is hotter than that entering at
various surface treatments at 100°C the bottom. If the fin depth L is increased, there is more mutual radiation between fins, and as the spacing
Table 5.4: Heatsink correction factor is reduced, mutual radiation increases further. Airflow is also restricted because of the smaller physical
Emissivity area for air to pass, since more of the available space is occupied by the heatsink itself.
Surface The performance of a heatsink is linearly proportional to the base width Whs of the sink in the direction
Surface position
shiny blackened ε
Cf Polished aluminium 0.05 perpendicular to the flow and proportional to the square root of the fin base length H in the direction of the
vertical 0.85 0.43 airflow. (The heat transfer coefficient h is inversely related to H). Therefore it is better to increase the width
Polished copper 0.07
horizontal 1.0 0.5 rather than the length, provided the width is not already excessive compared to the length.
Rolled sheet steel 0.66
Oxidised copper 0.70 Heat transfer coefficient h can be defined in a number of ways. If it is defined referenced to the inlet fluid
temperature of the heatsink, the heatsink thermal resistance is calculated by
Table 5.5: Fin spacing versus flow and fin length Black anodised aluminium 0.70 - 0.90
1
Black air-drying enamel 0.85 - 0.91 R hs a  (5.21)
f hA
Fin length (mm) H 75 150 225 300 Dark varnish 0.89 - 0.93
where A is the total surface area of fins and base between fins and
Airflow (m/s) v Fin Spacing (mm) s Black oil (organic) paint 0.92 - 0.96 ηf is the fin efficiency, defined as
natural convection 6.5 7.5 10 13 Al203 0.15 tanh mf  H  h P
1.0 4.0 5.0 6.0 7.0 f  in which mf  (5.22)
mf  H   Ax
2.5 2.5 3.3 4.0 5.0
where H is the base height of the fin, m
5.0 2.0 2.5 3.0 3.5 P□ is the fin perimeter, m
2
Ax is the fin cross sectional area, m
mf is the mass flow rate, equal to ρℓ ×Vf ×s×L, kg/s
The correction factor Cf illustrates the fact that black surfaces are better heat radiators and that warm air
ρℓ fluid density (= 1/ν specific volume), kg/m
3
rises, creating a ′chimney′ effect. Equation (5.19) is valid for one power-dissipating device, in the centre of
Vf is the velocity between the fins
the sink, at a static ambient temperature up to about 45°C, without other radiators in the near vicinity. If the heat transfer coefficient is defined based on the temperature between the fins, the thermal resistance
In order to decrease thermal resistance, inferred by equation (5.9), finned-type heat sinks are employed expression involves a heat capacitance component:
which increase sink surface area. Figure 5.6 illustrates graphs of thermal performance against length for a
1 1
typical aluminium finned heat sink. This figure shows that Rθ s-a decreases with increased sink length. R hs a   (5.23)
hA 2mf c p
If the fin thickness, t, is small relative to the fin spacing, s, the following equation can be used for estimating where cp is the fluid specific heat capacitance at constant pressure, kJ/kg.K.
the thermal resistance of a vertical heat sink in natural convection.
1 1 Estimating radiation heat transfer from an extruded heat sink
R hs a   (5.20) The effect of radiation heat transfer (hence emissivity, ε) is important in natural convection, as it can be
h  total fin area h   2nf LH  responsible for up to 40% of the total heat dissipation. Unless the heatsink is facing a hotter surface
where a fin efficiency of unity has been assumed (see equation (5.22)) and the number of fins, nf, is nearby, it is imperative to have the heat sink surfaces thinly painted or correctly anodised to enhance
Whs radiation. In natural convection situations where the convective heat transfer coefficient is relatively low,
nf  based on the dimensional parameters in figure 5.4a, the radiation heat transfer from all surfaces of the
s t
extruded heat sink can be calculated using
Minimal thermal reduction results from excessively increasing base length, H, as shown in figure 5.6b. The 1
R hs a  (5.24)
maximum distance between fins, s, depends on the fin depth, L, and width of the fins, t, with deep finned
heat sinks needing more space between adjacent fins than a shallow design, unless fan cooling is used.  
nf  1  a s   a nf t  2 L  B  H  T s  T A  T s2  T A2 
The minimum spacing s is determined by fin depth, L, and airflow. If the fins are packed too closely, the where nf is the number of fins
flow through them is significantly reduced and therefore the heat transfer coefficient, h, decreases. The εa is the apparent emissivity of a channel
deeper the fins, L, the more space needed between them since a portion of the heat is radiated to adjacent Ts is the heatsink surface temperature and
fins, which helps to stabilise the temperature, but does little to dispose of the heat (in figure 5.4a, about TA is the ambient temperature
30% of the heat is radiation transferred fin-to-fin, hence not all dissipated).
3
L/H
Heat transfer co-efficient h Thermal resistance Rθ 1

εa
b 2.5
Whs decreases due to close decreases due to reduction
proximity of adjacent fins in sink surface area
Emissivity ε = 0.8 0.8
L 2

Apparent Emissivity
0.4
Heat sink thermal resistance

1.5 0.2
H
1 0
Rθhs-a

Ts
0.5
Optimal Emissivity ε = 0.08
fin spacing 0
0 2 4 6 8 10
L / Whs
s t g (a) (b) Inside fin spacing s
Figure 5.5. Apparent emissivity εa of a channel heatsink of two different surface emissivities
Figure 5.4. Heat sink dimension parameters and thermal resistance dependence on fin spacing. for different number of fins and dimensions.
145 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 146

The apparent emissivity is a function of heat sink dimensions and surface emittances of the sink material, The chimney effect results in an airflow velocity v, which increases further up the heatsink stack. This and
as shown in figure 5.5, for two values of the surface emissivity, namely ε equals 0.08 and 0.8. The the air density increase results in the upper heatsink being the coolest, even though the passing air is the
apparent emissivity εa is based on enclosure theory and assumes a diffused grey surface and constant warmest.
surface temperature.
The emissivity coefficient, ε, indicates the radiation of heat from a body according the Stefan-Boltzmann
law, compared with the heat radiation from an ideal black body where the emissivity coefficient is ε = 1.

mK/W
60
Regardless of the composition of the emitting surface, the microscopic (and macroscopic) roughness of
the surface causes differences in emissivity because a rougher surface has a larger emitting area.

typical substrate thermal resistance

Generally, the emissivity of most opaque emitting surfaces increases as wavelength becomes shorter. 50
The emissivity coefficient, ε, for some common surface qualities of aluminium and copper can be found in
the Table 5.6 and in Appendix 5.11.
The low emissivity coefficients of untreated, polished aluminium and copper means they have surface 40
finishes that limit the radiated heat from a body. Two thin coats of flat white Krylon #1502 (or equivalent)
which has an emissivity of 0.96, should be used on all untreated (emissivity-wise) areas. Al202
substrate
30
Unless otherwise stated, the heat sink is assumed anodised black (emissivity of up to 0.97) and vertically Al3N4
mounted with negligible thermal resistance from case to sink. In accordance with the data in Table 5.4, a substrate
general derating of 10 to 15 per cent for a bright surface and 15 to 20 per cent in the case of a horizontal
mounting position, are usually adopted. Figure 5.6b also shows the improvement effects on dissipation 0 1 2 3 4 5 6
due to the high thermal conductivity (heat spreader effect) of oxidised copper. water flow l/min

Figure 5.7. Improved cooling with:

(a) forced air cooled heat-sink - relative thermal resistance improvement with surface airflow and
anodised (b) thermal resistance dependence on liquid cooling flow rate and substrate material.

5.4 Modes of power dissipation

fan Al
cooled
Cu For long, >1ms, high duty cycle pulses the peak junction temperature is nearly equal to the average
junction temperature. Fortunately, in many applications, a calculation of the average junction temperature
is sufficient and the concept of thermal resistance is valid.
Other applications, notably switches driving highly reactive loads, may create severe current-crowding
conditions which render the traditional concepts of thermal design invalid. In these cases, transistor safe
operating area or thyristor di/dt limits must be observed, as applicable.
Cu Cu
Al Al In yet other applications, heat cycling can cause power module faults, hence device failure, due to
 thermal cycling – is associated with large base plate (case) temperature changes, ΔTc
 power cycling – is associated with large junction temperature changes, ΔTj

The die is connected to a low thermal impedance substrate, usually utilising copper in the form of so-called
direct copper bonding, DCB, as shown in figure 5.8a and the forced water cooling effectiveness is shown
in figure 5.7b.
Direct copper bonding
Direct copper bonding DCB is a process in which copper (on each side) and a ceramic material, usually
either aluminium oxide (Aℓ2O3) or aluminium nitride (AℓN), are fused (bonded) together at high
temperature.
Figure 5.6. Heat-sink typical data (for aluminium and copper): The properties of DCB substrates are
(a) cross-section view; (b) heat-sink length versus thermal resistance for a matt black surface finish;  High mechanical strength and stability
(c) temperature rise versus dissipation for an anodised finish and different lengths; and
 Good cohesion and corrosion resistance
(d) as for (c) but with a matt black surface finish.
 High electrical insulation
 Excellent thermal conductivity
Thermal resistance increases with altitude, z, above sea level, as air density decreases, according  Reliable thermal cycling stability
to R  z   RO metres / 1  5  10 5 z  . For example: a 1°C/W heatsink degrades to 1.11°C/W at an altitude of  Matched thermal expansion coefficient to silicon and gallium arsenide
2,000 metres, or 1.18° C/W at 3,000 metres.  Good heat spreading
The effective sink thermal resistance can be significantly reduced by forced air cooling, as indicated in  Processable, e.g. copper is etchable and millable like a pcb
Table 5.5, figure 5.7 and by equations (5.7) and (5.8). If the airflow is  Environmentally friendly
 laminar, heat loss is proportional to the square root of air velocity, equation (5.7);  High copper current density
 turbulent, heat loss is proportional to velocity to the power of 0.8, equation (5.8).
The advantages of DBC substrates are high current carrying capability due to thick copper metallization
When heatsinks (dissipating a total power of PDtotal) are vertically stack to share the same vertical natural and a thermal expansion close to the silicon at the copper surface due to high bond strength of copper to
convention airflow, the air temperature of the flow at the upper heatsink, after passing n-1 heatsinks, is ceramic. The DCB process yields a super-thin base and eliminates the need for the thick, heavy copper
n 1 c v
bases that were used prior to this process. Because power modules with DCB bases have fewer layers,
T air  T amb  (5.25) they have a much lower thermal resistance. Because the expansion coefficient matches silicon, they have
n PD total much better thermal cycling capabilities (up to 50,000 cycles). (See Appendix 5.13)
 147 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 148

The drawback of standard DCB substrates for high voltage applications is a start of partial discharge at Power cycling
relatively low voltages. Therefore substrates using expensive metal brazing technologies (AMB) are Rapid cycling of the chip junction temperature causes mechanical stress around the silicon chip to
mainly used in high voltage semiconductor modules for traction applications. The initiation voltage for a aluminium wire bond interface, due to their different linear expansion temperature co-efficients. Eventually
ceramic thickness of 0.63mm is less than 4kV. Main causes for this behaviour are small voids between the a crack occurs on the silicon side of the interface, as indicated in figure 5.8a. Short rapid junction
copper and ceramic and blurred straight border lines of the copper conductors at the copper/ceramic temperature changes, over tens of seconds, of ΔTj =100K, can lead to failure within 2500 cycles. The
interface. Precision etching technology can alleviate these disadvantages. The other disadvantage of number of cycles to failure increases by just over an order for every 10°C decrease in ΔTj.
DCB is its deficiency for thermal shock because of the large residual stress on the substrate surface due to
the coefficient of thermal expansion CTE mismatch of alumina and copper. In a related thermal application, where the power dissipated in the semiconductor consists of pulses at a
low duty cycle, the instantaneous or peak junction temperature, not average temperature, may be the
Thermal cycling limiting condition. Figure 5.9 shows by comparison such a condition, where the operating frequency, not
Intermittent equipment operation, start-up, and shutdown in extreme temperature conditions may cause the maximum power dissipated, is dominant in determining junction temperature. In this case thermal
power module thermal stresses due to the different linear expansion temperature co-efficients of the impedance Zθ j-c is used instead of thermal resistance Rθ j-c such that Zθ j-c = r(tp) Rθ j-c, where r(tp) is the
materials associated with the soldered substrate mounting to the copper base plate in multi-chip large normalising factor yielded from the normalised transient thermal impedance curves for the particular
area packages (see Tables 5.14 and 5.15 in Appendix 5.10). Large base plate (case) temperature device. Appropriate values for the rectangular power pulse width tp and duty cycle factor δ are used.
changes in excess of 80K over a few minutes, stress the hard solder bonding between the copper base
plate and the insulating substrate (usually AℓN or Aℓ203), as shown in figure 5.8a. This fatigue leads to The power devices employed in power electronics are usually used in some form of on/off power pulse
eventual crack failure after a finite number of cycles N, as shown in figure 5.8c, approximated by waveform mode. The following power waveforms are analysed:
k  Periodic rectangular power pulses (steady-state thermal response);
N  (5.26)  Single rectangular power pulse;
A  T 2

where A is the die area and ΔT is the thermal shock temperature change. The constant k depends on the  Composite rectangular superimposed power pulses;
package, type of hard soldering, etc. Large, multiple die IGBT modules suffer from thermal shock  A burst of rectangular power pulses; and
limitations and relatively low reliability, because of the sheer large number of die soldered to the substrate  Non-rectangular power pulses.
over a large base plate copper area in the module.
Figure 5.8b shows how the number of thermal cycles to fracture for DCB substrates varies with copper 5.4.1 Steady-state response
thickness, when cycled between -40°C to +110°C. For a case temperature change of ΔT = 80K, lifetime
can be as low as 3,500 cycles and may only involve powering up and shutting down the associated Large cycle-by-cycle junction temperature fluctuations occur at low frequencies, figure 5.9a. As frequency
equipment. Thermal cycling is normally performed by cycling the inactive package between the maximum increases, thermal inertia of the junction smoothes out instantaneous temperature fluctuations, as shown
and minimum storage temperatures. Although Aℓ/SiC is far superior to copper from a differential thermal in figure 5.9b, and the junction responds more to average, rather than peak power dissipation. At
expansion perspective, its thermal conductivity is only a little better than that of aluminium. Floating silicon frequencies above a kilohertz and duty cycles above 20 per cent, cycle-by-cycle temperature fluctuations
wafers in disc type packages suffer to a much lesser extent (an order) from the effects of differential usually become small, and the peak junction temperature rise approaches the average power dissipation
thermal expansion when thermally cycled. The use of a CuSiC base plate rather than copper can improve multiplied by the steady-state junction-to-case thermal resistance, within a few per cent.
thermal cycling by a factor of ten. Because of thermal inertia (long thermal time constant), the heat sink and package case respond only to
power cycle average power dissipation, except at ultra low frequencies, < 1Hz. The steady-state thermal conditions for
crack
Si chip Aluminium the case-mount and junction (equation (5.12)) are given by
wire
solder layer T j Tc Tc T a
Pd   (W) (5.27)
Cu foil R j c R c-s  R s-a
insulation substrate with thermal cycle
where Pd is the average power dissipation, which is the maximum power multiplied by the on-time duty
adhered copper foil both crack
sides cycle δ for rectangular power pulses. The difficulty in applying equation (5.27) often lies in determining the
Cu foil
average power dissipation.
solder layer
Cu base plate

(a) tp t2
104 T2 T2
80ºC
number of thermal cycles until failure

(b) (c) T1 T1
103
T

2
10

10

1
0 0.2 0.4 0.6 0.8 1 1.2
copper thickness mm
Figure 5.8. Direct copper bonding:
Figure 5.9. Waveforms illustrating that peak junction temperature is a function of switching frequency:
(a) sectional view of power module substrate showing boundary regions where power cycle cracking
(a) lower switching frequency with 10 ms pulse and a 20 per cent duty cycle and
and thermal cycle cracking, occur; (b) copper thickness affect on power failure; and
(b) high frequency and 1 ms pulse with a duty cycle the same as in (a).
(c) power life thermal cycling.
149 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 150

5.4.2 Pulse response 

which yields T = 551.6K. That is, after a long period (>>10ms) the junction temperature would increase
When a junction dissipates power associated with a single pulse, the junction temperature increases by 551.6K. From equation (5.30), this temperature rise corresponds to continuous power of

during the pulse and decays to the original temperature after the energy pulse ceases. The junction 551.6K T
temperature variation may vary from ambient temperature to a level above the normal maximum operating Pd  
 1103.3 W
limit, a change of over 150°C. The upper temperature due to the power pulse can cause silicon damage, if
0.5K/W R
the maximum allowable limit is exceeded too often or by a large amount on just a single occasion. In 10ms the temperature must only rise 100K, hence, from equation (5.32) the transient thermal
impedance Zθ is
Equation (5.2) is valid for one dimensional steady state and transient thermal conditions, and the transient T
temperature equation is given by the first order solution to Z   r t p R 
Pd
 100 K
1103.3 W
 0.091K/W
A T
Pd   T  m A (W) (5.28)
t Thus the thermal resistance Rθ is modified, or normalized, by
The time domain solution for the temperature rise is
Z 0.0001K/W

r 10ms      0.181
T t   T  1  e t /   (5.29) R 0.5K/W
where the maximum temperature eventually attained if the power pulse were maintained, above ambient, Table 5.7 shows the normalised thermal impedance factor, r(tp), for other pulse durations, which are
is plotted in the accompanying figure. Notice the similarity of the single pulse results given for a practical

Pd P power device in figure 5.10.
T   d  Pd R
A hA
K  (5.30)
Table 5.7: Single pulse data
and the thermal time constant
m 2

s 
thermal capacity, J/K Pd
  (5.31) T Zθ r (tp)
 power per K, W/K tp 
= T / R = ΔT / Pd = Z θ / Rθ
t 
The transient thermal impedance Zθ is defined as pulse time temperature rise power dissipated thermal impedance normalised

 

T  1  e
t p / s K W K/W pu
Z   r t p  R 
T
Pd
 1  e  R
t p /

(5.32) 1 100 200 0.5 1
T 0.1 116 231 0.432 0.86
R
That is, thermal resistance Rθ is modified by the factor r(tp) to yield transient thermal impedance Zθ: 0.01 552 1103 0.091 0.181

r t p   1  e t p / 
 (5.33) 0.001 5050 10100 0.0099 0.0198
0.0001 50050 100100 0.0010 0.0020
This one-dimensional solution assumes a homogeneous thermal conducting material with a single point
heat source, producing a uniform heat flow path. Since the practical case is far from ideal, manufacturers 0.00001 500050 1000100 0.0001 0.0002
provide data for dynamic temperature effects based on the concept termed thermal impedance. The
thermal solution given by equation (5.29) gives acceptable results when applied to solid carbon resistors
(being a homogeneous material), as considered in Chapter 30 (specifically, see Example 30.7). The rmal Impe dance

1
Example 5.1: Semiconductor single power pulse capability

A semiconductor has a thermal capacity (mc) of 0.1J/K and a steady state thermal resistance to its case of
0.1
Rθ = 0.5 K/W. If the junction temperature is not to exceed 125°C in a 25°C ambient, determine the

pu
allowable power dissipation, hence transient thermal impedance, as a function of single power pulse
duration. Plot the results for five time decades, decreasing from 1s. single pulse
0.01
t p / 0.05s

r = Z/R
Solution 1e
The power dissipation per K is
0.001
11
Pd / K  
 2 W/K
R
0.5K/W
From equation (5.31) the thermal time constant τ is given by
0.0001
thermal capacity, J/K 0.1 J/K
   0.05s 0.00001 0.0001 0.001 0.01 0.1 1
power per K, W/K 2 W/K single pulse width, t p (s)

After time tp, the junction temperature rise from 25°C must not exceed 125°C, that is ΔT(tp) = 100K, thus ♣
equation (5.29) gives

   100K
 
  
T t p  T  1  e t /  T  1  e t p /0.05s Figure 5.10 shows the thermal impedance curves for a power-switching device, normalised with respect to
the steady-state thermal resistance Rθ j-c. The curve labelled ′single pulse′ shows the rise of junction
As a specific example of the procedure, consider a tp = 10ms energy pulse. temperature per watt of power dissipated as a function of pulse duration. The thermal impedance for


T 10ms   T  1  e 10ms/0.05s  100K  repetitive pulses Z, of duty cycle δ, can be determined from the single pulse value z according to
Z  t p ,      1    z t p  (K/W) (5.34)
151 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 152

5.4.3 Repetitive transient response

Equation (5.12) becomes
 
T j Tc T j Tc Minimal temperature variation occurs if the power switching period T is shorter than the junction to case
Pp   (W) (5.35) mount thermal time constant, T < τ, whence the concept of steady state thermal resistance is applicable,
Z  (t p ,  ) r (t p )R j c
as presented in 5.4.1. When the relative magnitudes are reversed such that T > 5 τ, then the temperature
effects of the power pulse die away, and the single pulse transient thermal impedance approach
Note that the peak power Pp is employed, and then only for thermal analysis from the junction to the case presented in 5.4.2 is applicable.
thermal mounting. That is, Zθ j-c is the only thermal impedance term that exists. See problem 5.8. The transition or boundary between junction operation that can be assumed steady-state junction
temperature operation (T < τ) and that of a series of discrete non-interacting single pulses (T > 5 τ) can be
Figure 5.10 shows that at the pulse width minimum extreme, tp < 1μs, as z(tp→0) →1 in equation (5.34): analysed by extending the one-dimensional thermal transient equation (5.29) in conjunction with figure
lim Z   0,     R j c  r t p  0  R j c (5.36) 5.9a. Figure 5.9a shows how the temperature increases from T1 to T2 during the time tp when power is
t p 0
dissipated, and decreases from T 2 to T1 during time t2 when no power is being dissipated by the virtual
that is, r(tp→0)→δ. junction. This increasing and decreasing of the junction temperature occurs cyclically over each period T.
Based on equation (5.29) the junction temperature increases exponentially according to
Figure 5.10 also shows that at the pulse maximum extreme, that is, tp > 1s or continuous power dissipation, 
  
as z(tp→1) →0 in equation (5.34): T t   T   T  T1  e t / (5.38)
lim Z   ,    R j c (5.37)  
t p 
and decreases exponentially according to
that is, r(tp→∞)→1, independent of duty cycle, that is, for all duty cycles. T t   T2 e t / (5.39)
where the thermal time constant τ and maximum possible junction temperature rise are defined by
equations (5.31) and (5.30), respectively. Since these temperature variations are in steady state, the
temperature constants T1 to T2 can be solve using the boundary conditions. This gives
t /

1 e p
T 2  T and T1  T 2 e t 2 / (5.40)
1  e T /

The junction temperature swing, ΔT is

T j  T 2  T 1  T
 1  e  1  e 
t p / t 2 /

(5.41)
T /
1e
The maximum variation in junction temperature occurs for square-wave power, that is tp = t2 = ½T, δ=½:

T 
T jmax  T tanh   (5.42)
 4 
This equation highlights that the magnitude of the temperature change is highly dependant on the power
switching frequency 1/T relative to the thermal time constant τ of the semiconductor package.
Figure 5.10. Transient thermal impedance curves;
normalised with respect to the steady state thermal resistance, Rθ j-c.
Example 5.3: Semiconductor transient repetitive power capability

Example 5.2: A single rectangular power pulse A semiconductor with a thermal capacity of 0.02J/K and a thermal resistance from the junction to the case
of ½K/W, dissipates 100W at a repetition rate of
A semiconductor with a junction to case thermal resistance of 1 K/W absorbs a single 100W power pulse i. 50Hz
for 20μs. Based on the thermal impedance characteristics in figure 5.10, what is the expected junction ii. 300Hz.
temperature rise, assuming the case-mount temperature does not respond to this short pulse? By calculating the worst-case junction temperature variation, indicate whether steady-state constant
junction temperature-based analysis (a thermal resistance approach) is a valid assumption.
Solution
Solution
The period for a single power pulse is infinite T → ∞, therefore the duty cycle t p / T is zero, δ = 0. The long-term junction temperature rise with 100W continuous is given by equation (5.30), which yields
T j c  P  Z  j c  P  r t p   R j c

T  Pd R  100W  ½K/W  50K
From figure 5.10, for a single 20μs pulse r(tp = 20μs) = 0.035. The junction temperature change is therefore The thermal time constant τ is given by equation (5.31), giving
T j c  P  r t p  20μs   R j c thermal capacity, J/K 0.02

power per K, W/K

1
 0.01 s 
 100W  0.035  1K/W = 3.5K ½
The peak junction temperature will rise to 3.5K above the case mount temperature at the end of the 100W Worst case temperature variation occurs with a 50% power duty cycle, as given by equation (5.42)
rectangular power pulse. 
T   T 
♣ T jmax  T tanh    50K  tanh  4  0.01s 
 4   
The basic single rectangular power pulse approach can be extended to analyse composite rectangular From this equation:
power pulses by algebraic superposition of a series of accumulating rectangular pulses. Because each at 50Hz, T = 20ms, T jmax = 23.1K
composite power pulse extends to the end of the temperature-calculating period, any positive rectangular at 300Hz, T = 3.33ms, T jmax = 4.1K
pulse is subsequently cancelled by a negative power pulse. The technique is illustrated in example 5.4.
The temperature variation of 4.1K at 300Hz is small compared to the maximum allowable junction
temperature, typical between 125°C and 175ºC, thus thermal analysis of this device in a 300Hz
153 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 154

application, can be thermal resistance calculation based as presented in 5.4.1. On the other hand, the Table 5.8: Rectangular, composite pulse example data
same device used in a 50Hz application will experience 5.6 times the junction temperature swing. This
23.1K variation represents a significant portion of the allowable junction operating temperature, and could tx ty
mean a thermal resistance approach is unsafe. A thermal impedance design approach is recommended,
tp1 tp2 tp3 tp4 tp5 tp6 tp7 tp8
as in example 5.2 and 5.4.2. Pulse duration
♣ 180μs 170μs 150μs 30μs 480μs 360μs 330μs 10μs
single pulse δ = tp / T 0 0 0 0 0 0 0 0
Example 5.4: Composite rectangular power pulses T→∞ r(tp) 0.06 0.055 0.05 0.025 0.10 0.085 0.08 0.015

A semiconductor with a junction to case thermal resistance of 1 K/W absorbs the composite power pulse
period δ = tp / T 0.36 0.34 0.30 0.06 0.96 0.72 0.66 0.02
shown in figure 5.11. Based on the thermal impedance characteristics in figure 5.12, what is the expected T = 500μs r(tp) 0.38 0.36 0.35 0.075 0.96 0.73 0.73 0.035
junction temperature rise at indicate times tx and ty, assuming the case temperature does not respond to
this short pulse? That is, the heatsink-case interface temperature is held constant.
In figure 5.11b, power pulse P1 = 40W lasts for 180μs, which represents a duty cycle of δ =180μs/500μs =
What is the average junction to case temperature rise, in the repetitive case, f=2kHz?
0.36. The thermal impedance normalised factor of r(tp1=80μs) = 0.38 corresponds to δ = 0.45 in figure
5.12. t p2 t p6
Solution t p4
r(tp) δ = tp / T t p4 t p3 t p1 t p7 t p5
↓
tx
1
Rectangular power pulses

ty
100 0.5
0.5

normalising thermal factor

80
(W)

r(tp) = Zθj-c (tp, δ) / Rθj-c

60
40 0.2
20 0.2
0 0.1
P

0 50 100 150 200 450 500 550 0.1

0.05
time μs t 0.05
0.02
(a) 0.01
t1 = 180μs 0.02
t2 = 170μs Single pulse
Composite rectangular power pulses

0.01
t3 = 150μs
t4 = 30μs 10μs 20μs 50μs 100μs 200μs 400μs
160
140 square-wave pulse duration tp
(W)

120
100
P3 = 100W
80
60
Figure 5.12. Normalise junction to case-mount thermal impedance characteristics.
P2 = 20W
P

40
20 P1 = 40W
0
-20 P1 = 40W 450
-40
50 100 150 500 450 The junction temperature (rise) at tx, is given by
-60 P2 = 20W time μs t T jtxc  P1Z tpj 1c  P1Z tpj 2c  P2Z tpj 3c  P2Z tpj 4c  P3Z tpj 4c
(b)
The junction temperature (rise) at ty, is given by
Composite rectangular power pulses

T j yc  P2Z tpj 5c  P2Z tpj 6c  P3Z tpj 6c  P3Z tpj 7c  P1Z tpj 8c
t
160
140 P1 = 40W
120
100
80
tx repetitive
(W)

60 P3 = 100W
40
20
T jtxc  40  Z tpj 1c  40  Z tpj 2c  20  Z tpj 3c  20  Z tpj 4c  100  Z tpj 4c
P2 = 20W
0
P2 = 20W
 40  0.38  1K/W  40  0.36  1K/W  20  0.35  1K/W  20  0.075  1K/W  100  0.075  1K/W
P

-20
50 100 150 200 350 400 450
-40 = 13.8K
-60 time t
-80 P3 = 100W
-100 tx single pulse
-120
T jtxc  40  Z tpj 1c  40  Z tpj 2c  20  Z tpj 3c  20  Z tpj 4c  100  Z tpj 4c
T = 500μs
t5 = 480μs
 40  0.06  1K/W  40  0.055  1K/W  20  0.05  1K/W  20  0.025  1K/W  100  0.025  1K/W
t6 = 360μs (c) = 2.7K
t7 = 330μs
t8 = 10μs
ty repetitive
Figure 5.11. Composite power pulses: (a) original rectangular pulse; T j yc  20  Z tpj 5c  20  Z tpj 6c  100  Z tpj 6c  100  Z tpj 7c  100  Z tpj 8c
t

(b) composite rectangular pulse, reference tx; and (c) composite rectangular pulse, reference ty.
 20  0.96  1K/W  20  0.73  1K/W  100  0.73  1K/W  100  0.67  1K/W  40  0.035  1K/W
= 12.2K
155 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 156

Figure 5.14 also shows the two rectangular pulse representations, where successive 50μs portions of the
ty single pulse triangle are represent by pulses, 100W, 37.5μs and 50W, 25μs, such that the total area is maintained and
T j yc  20  Z tpj 5c  20  Z tpj 6c  100  Z tpj 6c  100  Z tpj 7c  100  Z tpj 8c
t the peak junction temperature rise occurs at the end of the power pulse sequence. The two pulses are
subsequently decomposed into three equivalent composite rectangular power pulses, which sum at any
 20  0.10  1K/W  20  0.085  1K/W  100  0.085  1K/W  100  0.08  1K/W  40  0.015  1K/W time to give the original two rectangular pulses.
= 1.4K

In the repetitive composite pulse case, the average power dissipated over 500μs is

Power dissipated, Pd W

Power dissipated, Pd W
100μs, 100W 100μs, 100W
10μs  40W  120μs  20W  30μs  100W 50μs, 62.5μs,
 11.6W 100 100W 100 100W
500μs 80 80
The average junction to case mounting temperature rise is 60 60 25μs,
50μs, 50W

T j c  Pave  R j c  11.6W  1K/W = 11.6K 50W

40 40
♣
20 20
0 0
Non-rectangular power pulses
The concept and characterisation of thermal impedance is based on rectangular power pulses. 0 20 40 60 80 100 0 20 40 60 80 100
Non-rectangular pulses are converted to equivalent energy, rectangular pulses having the same peak time t μs time t μs
power, Pp, of duration tp, as shown in figure 5.13. The resultant rectangular power pulse will raise the tp3
junction temperature higher than any other wave shape with the same peak and average values, since it tp1
concentrates its heating effects into a shorter period of time, thus minimising cooling during the pulse.
160 tp2
Worst case semiconductor thermal conditions result. Improved thermal accuracy is obtained if each 160
non-rectangular pulse is further sub-divided into numerous equivalent total energy rectangular pulses, as 140 140
considered in example 5.5. 120 tp 120

W
100 100 P2

Power composites, P

Power composites, P
80 80
60 60
40 40
20 20 P1
0 0
-20 0 20 40 60 80 100 -20 40 60 80 100
equal
areas -40 time t μs -40
P1 t μs

-60 -60

Figure 5.14. Transient thermal impedance curves;

normalised with respect to the steady state thermal resistance, Rθ j-c.

The thermal impedance normalising factor r(tp) for the applicable device can be read from figure 5.15,
using the pulse periods and duty cycles shown in figure 5.14, and are shown in Table 5.9.
Figure 5.13. Conversion of non-rectangular power pulse (a) into equivalent rectangular pulse (b).

Example 5.5: Non-rectangular power pulses r(tp) δ = tp / T t p2 t p3 t p1

↓
Switch losses are a series of triangular power pulses rising linearly to 100W in 100μs after switch turn-on. 1
If the thermal resistance of the junction to case mounting is 1 K/W and the thermal impedance 0.5
0.5

normalising thermal factor

characteristics are represented by figure 5.15, calculate the case to junction peak temperature rise for

r(tp) = Zθj-c (tp, δ) / Rθj-c

0.2
i. A single pulse, T → ∞ 0.2
ii. 50% power duty cycle, T = 200μs 0.1
iii. 10% duty cycle, T = 1000μs 0.1
0.05
0.05
0.02
Represent the triangular power pulses by firstly one equivalent rectangular power pulse, secondly two
equivalent rectangular power pulses, and compare the predicted peak junction temperature rise results. 0.01
Assume the case temperature is maintained at a constant temperature. 0.02
Single pulse
Where applicable, calculate the average junction to case thermal mounting temperature drop, Tj-c. 0.01
10μs 20μs 50μs 100μs 200μs
Solution
square-wave pulse duration tp
Each saw-tooth power pulse is represented by a single rectangular power pulse, 100W and 50μs duration
in figure 5.14, therein fulfilling the requirements of the same maximum power occurring simultaneously in Figure 5.15. Transient thermal impedance curves;
both waveforms and both containing the same energy, area. normalised with respect to the steady state thermal resistance, Rθ j-c.
157 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 158

Table 5.9: Non-rectangular, composite pulse example data sawtooth area

Pd 
T
½  100W  100μs
One composite power pulse Two composite power pulses     50 W
T
Thus the average case to junction temperature drop is
Pulse duration tp tp1 t p2 t p3
T j c  P d  R j c
50μs 75μs 37.5μs 50μs
   50W  1K/W  50   K
Single pulse δ = tp / T 0 0 0 0 For 50% and 10% duty cycles, this gives average temperature drops of 25K and 5K respectively.
T→∞ r(tp) 0.045 0.04 0.040 0.045
Both rectangular composite power pulse decomposition assumptions produce similar thermal results. At
50% duty cycle δ = tp / T ¼ ⅜ 0.188 ¼ cycle frequencies of 5kHz and 1kHz, together with high duty cycles, the peak junction temperature is
T = 200μs r(tp) 0.32 0.40 0.22 0.32 marginally higher than the average junction temperature. Using the concept of thermal resistance is
adequate under the switching frequency and duty cycle conditions of this problem.
10% duty cycle δ = tp / T 0.05 0.075 0.0375 0.05 ♣
T = 1000μs r(tp) 0.08 0.12 0.066 0.08

5.5 Average power dissipation

For a single pulse rectangular power waveform Two commonly used empirical methods for determining power dissipation Pd are
T j c  P  Z  j c  P  r t p   R j c  graphical integration and
 power superposition.
 100W  r t p  50μs   1K/W
For a single pulse, δ =0 5.5.1 Graphical integration
T j c  100W  r t p  50μs   1K/W
Graphical integration may be formulated by digitally storing a complete cycle of test device voltage and
= 100W  0.045  1K/W = 4.5K current under limiting steady-state temperature conditions. Each voltage and current time-corresponding
For a 50% duty cycle, δ = 0.5 pair are multiplied together to give instantaneous values of power loss. Numerical integration techniques
T j c  100W  r t p  50μs   1K/W are then employed to give the average power dissipation.
= 100W  0.32  1K/W = 32K 5.5.2 Practical superposition
For a 10% duty cycle, δ = 0.1
T j c  100W  r t p  50μs   1K/W This technique is based on substituting a smooth dc voltage source for a complex waveform. A two-pole,
two-position switching arrangement is used, which firstly allows operation of the load with the device under
= 100W  0.08  1K/W = 8K test, until the monitored case temperature stabilises. Then, by throwing the switch to the test mode
position, the device under test (DUT) is connected to a dc power supply, while the other pole of the switch
For a two pulse rectangular power waveform representation supplies the normal power to the load to keep it operating at full power level conditions. The dc supply is
T j c  P1  Z  j c t 1  P1  Z  j c t 3  P2  Z  j c t 2 adjusted so that the semiconductor case temperature remains approximately constant when the switch is
 P1  r t p 1   R j c t1  P1  r t p 3   R j c t3  P2  r t p 2   Z  j c t2
thrown to each position for about 10 seconds. The dc source voltage and current values are multiplied
together to obtain the average power dissipated.
 50W  r t p 1  75μs   1K/W  50W  r t p 3  50μs   1K/W  100W  r t p 2  37.5μs   1K/W

For a single pulse, δ = 0 5.6 Power losses from manufacturers’ data sheets
T j c  50W  r t p 1  75μs   1K/W  50W  r t p 3  50μs   1K/W  100W  r t p 2  37.5μs   1K/W The total power dissipation Pd is the sum of the switching transition loss Ps, the on-conduction loss Pd,
 50W  0.04  1K/W  50W  0.045  1K/W  100W  0.04  1K/W drive input device loss PG, and the off-state leakage loss Pℓ.
= 3.75K The average total power loss is given by
1/fs
For a 50% duty cycle, δ = 0.5 Pd  f s  v (t ) i (t ) dt (W) (5.43)
T j c  50W  r t p 1  75μs   1K/W  50W  r t p 3  50μs   1K/W  100W  r t p 2  37.5μs   1K/W
0

where fs is the switching frequency and v(t) and i(t) are the device instantaneous voltage and current over
 50W  0.40  1K/W  50W  0.32  1K/W  100W  0.22  1K/W one complete cycle of period 1/fs. The usual technique for determining total power loss is to evaluate and
= 26K sum together each of the individual average power loss components.
For a 10% duty cycle, δ = 0.1
T j c  50W  r t p 1  75μs   1K/W  50W  r t p 3  50μs   1K/W  100W  r t p 2  37.5μs   1K/W
5.6.1 Switching transition power loss, Ps

 50W  0.12  1K/W  50W  0.08  1K/W  100W  0.066  1K/W Figure 5.16 shows typical power device voltage-current switching waveforms. Normally an exact solution
is not required and an approximation based on straight-line switching intervals is usually adequate.
= 8.6K
For a resistive load, as derived in Chapter 7
The average junction to case temperature for a single pulse is zero, and the average junction temperature Ps  61Vs I m f s (W) (5.44)
is the heatsink/ambient temperature. and for an inductive load, as derived in Chapter 7
The average junction to case temperature during repetitive operation is independent of whether one or two Ps  ½Vs I m f s (W) (5.45)
composite rectangular pulses are used to analyse the saw-tooth pulse pulses, since both model the same
where τ is the period of the switching interval (both on and off), and Vs and Im are the maximum voltage
original power waveform, each having the same waveform area, energy. The junction to case
and current levels as shown in figure 5.16. Switching losses occur at both turn-on and turn-off.
temperature is dependent on the duty cycle, which specifies the average power dissipation.
159 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 160

5.6.2 Off-state leakage power loss, Pℓ 5.7 Heat-sinking design cases

During the switched-off period, a small, exponentially temperature dependent current Iℓ, will flow through Heat-sink design is essentially the same for all power devices, but the method of determining power loss
the switch. The loss due to this leakage current is varies significantly from device type to device type. The information given in data sheets, in conjunction
P  I Vs (1   ) (W) (5.46) with the appropriate equation in Table 5.11, allows the designer to calculate power semiconductor thermal
where δ is the on-time duty cycle of the switch. Normally Pℓ is only a small part of the total loss so that the rating for a variety of conditions.
error in neglecting Pℓ is not significant. Generally, heatsink design is more readily visualised if a thermal equivalent electrical circuit model
approach is adopted, as shown in figure 5.1. The equivalence of parameters is shown in Table 5.10. The
examples to follow illustrate the approach.

Table 5.10: Thermal equivalent electrical circuit parameters

thermal parameter thermo-electric model magnetic model

temperature potential magneto motive Amp-turn
Kelvin ΔT Volts ΔV 
drop difference force s
power
Watts P current flow Amps I flux Wb Φ
dissipated
thermal Ohm’s Amp-turn
K/W Rθ Ohms R reluctance 
resistance resistance s/Wb

Figure 5.16. Typical voltage and current at turn-off switching transition for:
(a) an inductive load and (b) a resistive load. Current and voltage are interchanged at turn-on. 5.7.1 Heat-sinking for diodes and thyristors

At low switching frequencies (<100 Hz), switching loss can be ignored, so that in the case of rectifying
5.6.3 Conduction power loss, Pc diodes or converter-grade thyristors, 50 to 60 Hz, switching loss can usually be ignored. Fast-recovery
power diodes switching at less than 500Hz can also have switching losses neglected at low VA levels.
The average conduction power loss under a steady-state current condition is given by
Pc   I onVon (W) (5.47) 5.7.1i - Low-frequency switching
although equation (5.43) is valid in the general case when the integration is performed over the interval At a given current level IF and on-time duty cycle δ, on-state power loss can be read directly from the
corresponding to δ. manufacturers’ data. Figure 5.17a illustrates loss for square-wave power pulses, while figure 5.17b
The conduction loss for the MOSFET is usually expressed in terms of its on-state resistance (equations illustrates loss in the case of half-wave sinusoidal current. Figure 5.17b gives energy loss per cycle, which
(3.16) and (4.12)) may be converted to power when multiplied by the sinusoidal pulse frequency.
Pc  I d2(rms )Rds (on ) Thyristor loss due to the current waveform initial rate of rise of current, di/dt, can be incorporated and its
T 25°C contribution is added into the manufacturers’ conduction loss data for a given device type.
  j (5.48)
 I d2(rms )Rds (on ) (25°C) 1   (W) 5.7.1ii - High-frequency switching
 100 
At device operating frequencies greater than about 100 Hz, fast-recovery diodes are normally employed
where  is the temperature coefficient of the on-state resistance, which is positive. A linear resistance
and at about 500Hz, switching losses must be added to the on-state conduction loss. Diode turn-off loss is
approximation of equation (5.48) is accurate above 25°C if  is small, such that Pc can be approximated by
usually more significant than turn-on loss. Manufacturers provide maximum reverse recovery charge, QR,
Pc  I d2(rms )Rds (on ) (25°C) 1   (T j  25°C) (W) (5.49) characteristics as shown in figure 5.18. The reverse recovery charge is a linear function of temperature
and between the given junction temperatures of 25°C in figure 5.18a and 150°C in figure 5.18b,
5.6.4 Drive input device power loss, PG interpolation of QR is used.

A portion of the drive power is dissipated in the controlling junction or, in the case of the MOSFET, in the The reverse recovery W.s/pulse, JR, can be approximated by
internal gate resistance. Usually more power is dissipated in the actual external drive circuit resistance. J R  VRQR (J) (5.52)
Drive input loss is normally small and insignificant compared with other losses, and can usually be where VR is the reverse voltage applied to the diode just after turn-off. Losses are lower since the diode
ignored. only supports voltage once peak reverse recovery has occurred (at the peak of the reverse current). The
reverse recovery average power loss is given by
Two possible exceptions are:
 One notable exception is in the case of the power GTO thyristor, where continuous gate drive is
Ps VRQR f s (W) (5.53)
used to avoid loss of latching or when the holding current is high. The holding current can be 3% of
the anode current thus, the gate to cathode junction loss can be included in the total loss
calculation for better accuracy. Thus, for a gate junction voltage VGC the gate losses are given by The total average power loss is the algebraic sum of the steady-state conduction loss and the recovery
Pg   I G VGC (5.50) loss.
The recovery loss of the gate commutated thyristor (GCT) cathode junction can be included since it
is significant because the full anode current is extracted from the gate, thus is involved in recovery
of the cathode junction.
 A second exception is the MOSFET and IGBT at high switching frequencies, >50kHz, when the
loss in the device, associated with providing the gate charge QT is given by equation (4.36):
RG int
PG (Rint )  Vgg QT f s (W) (5.51)
RG int  RGext
161 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 162

Table 5.11: Power rating equations based on thermal considerations

(c) Constant high

frequency and
constant duty
cycle

P T
T
δ = tp / T
tp
(d) Constant low Tj Ttp
frequency and
Pd Ttp – Ta = Pd zθ(tp)
constant duty
cycle

t
Ta t
0 tp T
Figure 5.17. Diode on-state energy loss at low frequency as a function of forward current for:
(a) squarewave power pulses and (b) sinusoidal power pulses.

(e)

2 2
Example 5.6: Heat-sink design for a diode

A fast-recovery diode switches 60 A rectangular current pulses at 10kHz. The off-state bias is 400V and
the external circuit inductance limits the reverse dIF /dt to 100A/μs. If the device junction-to-case thermal
1 1 resistance is 0.7K/W, calculate the minimum heat-sink size requirement with a 50 per cent conduction duty
cycle, if the maximum ambient temperature is 40°C.

Solution

20 50 100 500 1000 20 50 100 500 1000 The steady-state loss given from figure 5.17a is about 40 W when using IF(AV) = 30A for δ = 0.5.
Minimum possible heat-sinking thermal resistance requirements occur when Tj is a maximum, that is
150°C from figure 5.18b. From figure 5.18b, for dIF /dt = 100 A/μs and IF = 60A, the maximum reverse
recovery charge is 1.3μC. The switching power loss (over estimate) is given by
Ps  QRVR f s
= 1.3μC×400V×10kHz = 5.2W
Figure 5.18. Reverse recovery charge as a function of forward current and dIF/dt at:
(a) 25°C and (b) 150°C junction temperature. The total power loss is therefore
Pd  40 + 5.2 = 45.2W
163 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 164

Since the frequency and duty cycle are both high, the concept of thermal resistance is appropriate; that is 5.7.3 Heat-sinking for power MOSFETs
T j  T a  Pd (R j-c  R c-a )
Switching losses in MOSFETs tend to be low at frequencies below 20 kHz and therefore may be neglected,
Therefore 150V = 40V + 45.2A  (0.7 + R c-a ) (in units of the electrical dual) along with gate and off-state losses. Conduction loss is generally expressed in terms of the on-state
2
resistance as I R loss. The first step in the thermal design is to determine the total power dissipation in the
device, which is generally dominated by the conduction loss. Determination of this loss is not trivial since,
whence R c-a  1.73 K/W while the power dissipation determines junction temperature, the power dissipation itself is a function of
junction temperature, because the on-state resistance increases with temperature, as shown in figure
Figure 5.6b shows that a minimum of 50mm length of matt black heat sink is required. This assumes that 3.13.
the case-to-sink thermal resistance is negligible. In order to improve device reliability and lifetime,
operation at T j is avoided. A derating of 40 to 50°C significantly reduces junction thermal fatigue and can
result in a tenfold improvement in reliability. To restrict T j to 100°C, Rθ c-a= 0.7K/W, necessitating 120 mm Example 5.8: Heat-sink for a MOSFET - repetitive operation at high peak current, low duty cycle
of the heat sink as characterised in figure 5.6b. The flatness of the Rθ s-a curve means that the
effectiveness of the heat sink is diminished and either a wider sink of the same length or a shorter length of Find the thermal resistance of the heat sink needed for a MOSFET conducting a repetitive 20A rectangular
a profile offering lower thermal resistance would be more effective in reducing device thermal fatigue. current waveform. On-time is 10μs, duty cycle is 0.1 per cent, and the maximum ambient temperature is
♣ 40°C. Assume Rds (on) at 150°C and 20 A is 5 Ohms, and Rθ j-c = 1.5 K/W.
Solution
5.7.2 Heat-sinking for IGBTs Since the on-state duty cycle and switching frequency are both low, the peak junction temperature
at the end of the on-period will be significantly different from the average junction temperature. The
Externally, the IGBT conduction loss is related to the gate voltage and the collector current magnitude, concept of thermal resistance from the junction to the case is therefore invalid; rather the concept of
which specify the on-state voltage. No simple power loss characteristic is possible, as in figure 5.17 for the thermal impedance is used.
The peak power per pulse = Pp = I R = 20 × 5Ω = 2 × 10 W
diode and thyristor. Fortunately, the power switching IGBT is used in such a way that its on-state 2 2 3

collector-emitter voltage is near constant, whence conduction loss is given by Using a thermal impedance basis, the case temperature is given by
Pc   v ce I c (W) (5.54) T j  Tc  Pp  Z  j-c
 Tc  Pp r (t p ) R j-c
where r(tp) is the transient thermal impedance factor for the junction-to-case. For a 10 μs pulse
Example 5.7: Heat-sink design for an IGBT- repetitive operation at a high duty cycle from figure 5.10, r(tp) = 0.03, assuming δ = 0.001≈ a single pulse condition, thus
150°C = Tc + 2  103  0.03  1.5 = Tc + 90°C
A power IGBT is used to switch a 20A, 100V inductive load at 10 kHz. The transistor maximum on-state
duty cycle is 90 per cent and the device has a junction-to-case thermal resistance of 0.7K/W. The that is Tc = 60°C
transistor on-state voltage is maintained at 2V and the switch-on and switch-off times are 1 and 2 μs The average junction temperature is
respectively. If the junction temperature is not to exceed 125°C with a maximum ambient temperature of T j  Tc  P d R j c  T c   Pd R j c
35°C, what is the minimum heat-sink requirement? Assume that the transistor is in a T0247 package,
which is mounted directly on the heat sink but with interface silicone grease used.  60°C  0.1%  2  103 W  1.5°C/W
= 60°C + 3°C = 63°C
Solution Although the average junction temperature is only 3°C above the case temperature of 60°C, the peak
junction temperature reaches 150°C.
Since both the duty cycle and switching frequency are high, the peak junction temperature is Because of the heat-sink thermal inertia, the concept of thermal resistance and average power are
approximated by the average junction temperature. That is, the concept of thermal resistance is valid. used for calculations involving the heatsink. That is
The on-state power loss is given by
T c  T a  P d R c-a  T a   Pd R c-a
Pc   v ce I c = 0.9  2V  20A = 36 W
60C = 40C + 0.001  2  103  R c-a
From equation (5.45), the switching losses for an inductive load are thus R c-a  10 K/W
Ps  Ps (on)  Ps (off) The heat sink of cross-section shown in figure 5.6a is not suitable in this application, and one of a much
smaller surface area is applicable. A heatsink may not be necessary since the package thermal
= ½×100V × 20A × (1μs + 2μs) × 10 kHz = 30 W resistance Rθ c-a, shown in figure 5.1, may be less than 10K/W, there in satisfying equation (5.17). See
Total power losses Pd are 36W+30W = 66 W. problem 5.6.
♣
From

Tj  T a  Pd R j-c  R c-s  R s-a 
If the junction operating temperature is unknown but can be assumed greater than 25°C, from equation
125C = 35C + 66W   0.7 + 0.1 + R s-a  (5.49), the total power loss can be expressed as
Therefore R c-a = 0.56 K/W Pd  Po  I d2(rms)Rds (on) (25°C) 1   (T j  25°C) (W) (5.55)
where Po represents all losses other than the conduction loss, and is assumed temperature independent.
The case-to-heat-sink thermal resistance value of 0.1K/W for a T0247 non-insulated case using The temperature coefficient  for Rds (on)(25°C) is positive, typically 1 per cent/K as indicated in figure 3.13.
silicone thermal grease was obtained from Table 5.1. To obtain the minimum heat-sink thermal The usual thermal equality holds, that is
resistance of 0.56K/W, 150 mm of the heat sink with cross-section shown in figure 5.6a is required. T j  T a  R j-a Pd (K) (5.56)
Clearly, a sink profile that has a lower thermal resistance per unit length would be more suitable. Combining equations (5.55) and (5.56) by eliminating Tj yields
♣
P  I d2(rms)Rds (on) (25°C) 1   (T a  25°C)
Pd  o (W) (5.57)
1  I d2(rms)Rds (on) (25°C) R j-a
165 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 166

The denominator yields an asymptotic maximum drain current of T hs  T a  42C  30C  R hs a   40W  20W 
TDiode TTransistor
1
I d (rms)  (A) (5.58) R hs a  42C  30C  12C  0.2K/W
Rds (on) (25°C)  R j-c 40W  20W 60W 20W PD PT 40W
at which current thermal runaway would result. In practice, insufficient gate voltage is available and the RθDj-c RθTj-c 0.8K/W
ii. Assume device losses are not affected by temperature and the heatsink
device would leave the constant-resistance region and enter the constant-current region, where the above 0.7K/W
thermal resistance is decreased to ½×0.2 = 0.1 K/W, then
analysis is invalid.
T hs  Ta  T hs  30C  0.1K/W   40W  20W  RθDc-hsc RθTc-hs
T hs  0.1K/W   40W  20W   30C = 36C
0.6K/W 0.5K/W
Ths
Example 5.9: Heat-sink design for a MOSFET - repetitive operation at high duty cycle The device junction temperatures are given by
A power MOSFET switches 5 A rms at 10 kHz with a maximum on-state duty cycle of 90 per cent. The TDj  36C  20W   0.8K/W  0.6K/W  that is TDj  64C Rθhs-ac
junction-to-case thermal resistance is 0.7 K/W, the maximum ambient temperature 35°C, and on-state TTj  36C  40W   0.7K/W  0.5K/W  that is TTj  84C Ptotal
resistance at 25°C is 1 Ohm. If the heat-sink arrangement yields an effective case-to-ambient thermal 64W Ta
resistance of 1.3 K/W and  = 0.01 /K, what is the junction operating temperature? =30°C

Solution The junction temperature of each device has decreased by about 6°C, so although the lifetime will have
increased, lifetime improvement is not doubled. Device package thermal properties are more dominant
Since the switching frequency and duty cycle are both relatively high, the thermal resistance concept than the heatsink in determining junction temperatures.
based on average junction power dissipation is valid.
iii. If the on-state duty cycle is δ and the instantaneous device losses are both P (since the on-state
Assuming zero losses other than conduction losses, then Po = 0. Equations (5.55) and (5.56) voltage is the same for both devices and the current is constant hence the same for both when each
rearranged to eliminate Pd yield device conducts) then
mosfet  P  40W
T a  R j-aI d2(rms)Rds (on) (25°C) 1  25 
Tj  (W) (5.59) diode 1    P  20W
1   R j-aI d2(rms)Rds (on) (25°C)
Assuming typical  = 0.01/K and Rθ j-a= Rθ j-c+ Rθ c-a Summing these two equations gives an instantaneous loss of P = 60W, whence a switch on-state duty
cycle of δ = , that is the switch conducts for 66% of the cycle period. The diode on-state voltage is
35C + 2  5  1  (1- 25  0.01)
2 2
therefore 60W/30A = 2.0V and the MOSFET on-state resistance is 60W/30A = 67mΩ.
Tj= = 145°C
1 - 0.0l  2  52  l ♣
♣

Example 5.11: Six thermal elements (on a common substrate) in a common package
Example 5.10: Two thermal elements on a common heatsink
A three-phase full-wave diode rectifier package consists of six-diode die within a single module. The
A dc chopper has a MOSFET switch that dissipates 40W and a load freewheel diode that dissipates 20W. junction-to-case thermal resistance of each die is 0.24K/W. The module is mounted on a heatsink with a
Each power device is mounted on a common heatsink. The MOSFET has a junction-to-case thermal module-to-heatsink contact thermal resistance of 0.2K/W and a heatsink-to-ambient thermal resistance of
resistance of 0.7K/W and a case-to-heatsink thermal resistance of 0.5K/W. The diode has a 0.1K/W. The maximum ambient temperature is 30°C and the highly inductive load current is constant at
junction-to-case thermal resistance of 0.8K/W and a case-to-heatsink thermal resistance of 0.6K/W. 100A. If the diode on-state voltage is 1V, determine
i. Determine the maximum heatsink thermal resistance that maintains both junction
i. the diode junction temperature
temperatures below 90°C in a 30°C ambient.
ii. the current to double the rectifier lifetime (decrease junction temperature by 10°C)
ii. Semiconductor lifetime approximately doubles for every 10°C decrease in junction
iii. the heatsink to double the rectifier bridge lifetime (at 100A).
temperature. If the heatsink in the previous case is fan cooled, estimate the lifetime
improvement if the heatsink thermal impedance is halved with fan cooling.
iii. If the load current is constant (25A) and the switch and diode on-state voltages are Solution
the same, determine the chopper on-time duty cycle and device instantaneous
losses assuming no switching losses (only on-state losses). i. During rectification, two diodes always conduct therefore total module conduction losses are
PM  2  I o VDon  2  100A  1V = 200W
Solution Tj1 Tj2 Tj3 Tj4 Tj5 Tj6 Tj
The figure shows how the six thermal paths can be PM/6 PM/6 PM/6 PM/6 PM/6 PM/6 PM 200W
i. Applying Kirchhoff’s voltage law to each loop of the equivalent thermal circuit shown gives:
reduced to the simplified equivalent thermal model
TDj  T hs  20W   0.8K/W  0.6K/W   28C on the right.
TTj  T hs  40W   0.7K/W  0.5K/W   48C Rθj-c Rθj-c Rθj-c Rθj-c Rθj-c Rθj-c = 0.24K/W Rθj-c/6 0.04K/W
Applying Kirchhoff’s voltage law
Since both semiconductor devices are mounted on the same heatsink, Ths is the same in each case, the
T j  T a  PM   1 6 R j c  Rc hs  R hs a 
Tc Tc
MOSFET virtual junction will operate 20°C hotter than the diode junction. Therefore the MOSFET junction
temperature should not exceed 90°C, that is 0.2K/W Rθc-hs 0.2K/W
90C  Ths  40W  0.7K/W  0.5K/W   48C T j  30°C  200W   1 6  0.24K/W  0.2K/W  0.1K/W  Ths Ths

 T j  98°C 0.1K/W Rθhs-a 0.1K/W

giving a heat sink surface temperature of 90°C - 48°C = 42°C and a diode junction temperature of 42°C +
30°C Ta Ta 30°C
28°C = 70°C. The heatsink thermal resistance requirement is
ii. If the current is reduced so as to decrease the
diode junction temperature by 10°C then
167 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 168

-1
10 K
T j  T a  PM   1 6 R j c  Rc hs  R hs a 

-6
10
88°C  30°C=PM   1 6  0.24K/W  0.2K/W  0.1K/W   PM  170.6W

coefficient of thermal expansion

Assuming the diode on-state voltage drop is independent of current, that is remains 1V then 9
PM  2  I o V Don
170.6W  2  I o  1V  I o  85.3A
8
iii. When the junction temperature is reduced by 10°C to 88°C by decreasing the heatsink thermal
resistance, and the constant load current is maintained at 100A
T j  T a  PM   1 6 R j c  R c hs  R hs a  7

88°C  30°C = 200W   0.04K/W + 0.2K/W + R hs a   R hs a  0.5K/W

♣ 6
0 0.2 0.4 0.6 0.8 1 1.2
copper thickness mm
Reading list
Figure 5.19. Thermal expansion dependence on copper base plate thickness.
Fishenden, M. and Saunders, 0. A., An Introduction to Heat Transfer,
Oxford University Press, 1982.

http://www.electronics-cooling.com Table 5.12: Substrates properties

http://www.qats.com/qpedia.asp
Beryllium Silicon
Material Aluminium nitride Aluminium oxide
http://www.lytron.com/ oxide carbide
symbol Aℓ3N4 Aℓ2O3
http://www.aavidthermalloy.com/
Colour Tan/Gray white white
http://www.1-act.com/ Melting point/ maximum >2200/800
°C 2054/1700 2507/1800 -/1650
use temperature oxidizing
http://pcmproducts.net/ Purity wt % 98% 99.6% 99.5
3
Density g/cm >3.25 >3.65 2.85 3.2
Thermal Conductivity W/m. K 100 - 300 27 265 270
5.8 Appendix: Comparison between aluminium oxide and aluminium nitride (substrates) -6
x10 /K @
Thermal Expansion >20°C
<4.3 <7.7 8.0 3.7
Aluminium Nitride is made by nitridation of aluminium or by conversion of alumina Al203 to aluminium Specific Heat J/kg K 740 880 750
nitride. It is a covalently bonded material and has a hexagonal crystal structure. Because of its resistance
to sintering, an oxide-forming additive such as Y203 is needed to form a substrate. General comparison Dielectric Strength kV/mm >15 >12 9.5
properties of aluminium oxide and nitride are listed in Table 5.12. at 1MHz
Dielectric Constant @ 20°C
8.7 9.2 6.6 40
-4
Aluminium nitride is a cost effective, non-toxic alternative to beryllium oxide and has a thermal conductivity Dissipation Factor
x10 @ 1
MHz)
3-7 3 4
nearly eight times higher than alumina (aluminium oxide). Advantages of aluminium nitride include good
12 o
thermal performance, low thermal expansion, and non-toxicity. Aluminium nitride offers: 14 >10 at 20 C 15 2 6
Volume Resistivity ohm-cm >10 8 o 10 10 -10
 High thermal conductivity >10 at 500 C
 Low thermal expansion coefficient closely matching silicon Flexural Strength
kgf /mm >250 >280 120-150 450
 Good dielectric strength MPa 300 345 150-200 550
 High electrical sensitivity Modulus of elasticity GPa 331 372 345 410
 Low toxicity and therefore excellent replacement for Be0 Hardness (Knoop) GPa 11.8 14.1 9.8 27
 Good shock and corrosion resistance
Poisson’s ratio 0.22 0.21 0.26 0.14
 Low dielectric loss
 High temperature stability toxicity nontoxic nontoxic toxic nontoxic
 High flexure strength and light weight Substrate Specification
 Resistant to wafer processing gasses and plasma erosion
Maximum Dimension mm 140 x 100mm, 100 x 200
 Conducive to finishing operations such as lasering, lapping, and polishing
 Substrate for direct bond copper DBC and filled vias Thickness mm 0.63 - 0.2 mm 0.63 - 0.30mm
 Good adhesion for thin and thick film applications as fired - 0.3 as fired - 0.3 as fired - 0.3
 Uniform lapped and polished surfaces for resistor networks Surface Roughness micron as lapped - 0.075 as lapped - 0.075 as lapped - 0.1
as polished - 0.025 as polished - 0.025 as polished-0.08
 Polished and lapped surface finishes to 12nm, Ra, with minimum pullouts
 Lapped surface finishes to 150nm, Ra, where is the roughness average profile
1 n At room temperature, the thermal conductivity of aluminium nitride ceramics is independent of Aℓ 3N4 grain
Ra   y i
n i 1 size or number of grain-boundaries, but is controlled by the internal structure of the grains, such as the
degree of oxidation (oxygen contamination). Thermal impedance is compared in the following figure.
169 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 170

Table 5.14: Properties of module materials

specific linear thermal temperature

relative dielectric loss
thermal expansion coefficient of type
material permittivity factor
conductivity coefficient εp
@1MHz 10GHz, 25°C @25°C
εr tanδε λ Δl / l /ΔT Δε / εΔT
-4 -6 -6
×10 W/m K 10 /K 10 /K
Aℓ203 99.5% 9.8 1 37 6.5 136 insulator
sapphire 9.4 1 42 6 110 insulator
Quartz glass 3.78 1 1.7 0.55 13 insulator
Beryllium oxide ceramic insulator
6.3 60 210 6.1 107 3
Be0 8900kg/m
GaAs 12.9 20 46 5.7 semiconductor
Silicon
11.9 150 145 4.2 semiconductor
ρ = 10 Ωcm
3
time [ms]
PTFE 2.2 3 0.2 106 350 plastic
polyolefin 2.32 7 0.5 108 480 plastic
The coefficient of thermal expansion for direct copper bonded (DCB) substrates with a layer of 0.6 mm copper 1.0 393 17 24.1 metal
alumina sandwiched between Cu layers of various thicknesses is shown in figure 5.19.
−1300+i1.3×10
14
aluminium 220 23.8 metal

Table 5.15: Power electronic component properties

5.9 Appendix: Properties of substrate and module materials
Zn Ag temperature
thermal specific heat Melting
pure metals material density coefficient
conductivity capacity point
liquids of expansion
Ni Al 20°C λ c ρℓ CTE
liquids
alloys 3
W /m K J/ kg K kg/m ppm/K K
liquids
plastics ice oxides air (STP) 0.026 1004 1.2 -
liquids
nonmetallic solids silicon Si 120 700 2330 3.5 1685
liquids
Foams fibres solder PbSn 50 150 8400 24.1 183
liquids
insulation systems copper Cu 385 385 8930 17 1358

Oils H2 O Hg
alumina Aℓ203 22 80 3720 6.5
liquids
liquids aluminium nitride Aℓ3N4 170 725 3300 4.5
aluminium silicon carbide AℓSiC 170 3000 7
CO2 H2
liquids polyimide 0.2 1100 1400
gases
liquids dielectric layer 0.3 1400 1120
encapsulation 0.5 2000
0.01 0.1 1 10 100 1000
Thermal conductivity W /mK aluminium Aℓ 205 900 2710 22.5 775
gold Au 315 126 19320 14.2 1336
platinum (90%) Iridium (10%) 31.1
Table 5.13: Substrate characteristics platinum Pt 70.9 1448 21450 9.0 1728
tungsten W 188 130 19300 4.6 3410
Material Al2O3, BeO, AℓN, Quartz, Silicon, Sapphire, Ferrite
molybdenum Mo 140 250 10200 4.9 2610
Surface Finish Al2O3 As Fired, 0.05μm maximum;
lead Pb 235 130 11340 23 327
Polished to 0.12μm
tin Sn 66 227 7300 23 232
Dimensions 0.5mm x 0.5mm to 100mm x 100mm
Cu/Mo/Cu 5.8
Dimensional Tolerance ± 0.01mm scribed; (± 0.002mm saw cut) silicon carbide SiC 700 250 3.21 3.7
Thickness 0.012mm inches to1.2mm sapphire 2700 419 3900 8.4 2040
Thickness Tolerance 0.12mm standard to as tight as 0.04mm diamond 2300 509 3500 2.4 3100
Sputtered Resistor Material NiCr, Ta2N Sputtered Metallization Ti, TiW, Pd, Ni, Au, Aℓl brass CuZn 111 343 8490 18.0 920
Electro-Plated Metals Au, Cu, Ni, Solder steel (low carbon) 48 460 7850 11.5 1370
Electroless Plated Metals Sn, Ni, Au Mica K Mg3 AlSi3 O10 (OH)2 0.6 1700
171 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 172

beryllium Be 230 1088 2880 5.9 1280

Table 5.16: Normal total emissivity values @ 20°C
silicon thermal grease 0.8 2093 2.8 -
thermal conducting plastic 20 Metals ε Coatings ε
Aluminium polished 0.04 Aluminium bronze 0.3
5.10 Appendix: Emissivity and heat transfer coefficient sheet 0.09 Aluminium paint 0.35
Brass polished 0.05 Blackbody paint 0.97
Emissivity is not only a material property but also a surface property, at least for opaque materials.
Consequently, coatings (oxides, grease, and water film) influence the value measured under pristine oxidized 0.22 Enamel 0.82
conditions. For example, the emissivity of a copper surface covered with 2 µm oxide increases from 0.03 Chromium polished 0.06 Lampblack 0.95
to 0.2. In practice, surfaces that are initially shiny are covered with oxide and dust after one year of
rough 0.74 Paint 0.89
operation. Additionally, surface texture can influence the emissivity because of a strong dependence on
angle. Copper polished 0.03
Gold polished 0.025 Various
For heat transfer calculations, total hemispherical emissivity is found by integration over all wavelengths
and all angles. What is being measured with an IR camera is the normal spectral emissivity restricted to Graphite polished 0.42 Glass, Quartz 0.93
the wavelength band of the detector. Inconel polished 0.2 Ice 0.98
Iron polished 0.06 Plastics 0.8
As a rule of thumb: for unpolished metals the ratio of hemispherical to total emissivity is 1.1 to 1.3, and for
non-conductors 0.95 to 0.97. Another angle-dependent difference between metals and insulators is that oxidized 0.85 Paper 0.8
under a shallow incident angle, the emissivity of metals tends to one and insulators tend to zero. ground 0.24 Porcelain 0.92

A complication is, the emissivity of many materials of interest is strongly dependent on the wavelength. cast 0.16 Silk, Cotton, Wool 0.75
That is, there is a big difference between the visible band and most common IR bands (0.8 to 3 µm, 3 to 8 Mercury 0.09 Stone 0.8-0.9
µm, 8 to 14 µm). Si and Ge are notorious examples. It is relevant to low-temperature applications (<100°C) Molybdenum polished 0.05 Water (> 0.1mm) 0.95
because the bulk of the radiation is in the long-wavelength region: 8 to 14 µm. This is the main reason why
the colour of paints is not relevant for heat sinks and casings. All colours are black. Apart from the fact that @ 2600 K 0.29 Wood 0.9
it is simply impossible to account for all the physics of radiation in a practical situation, the problem is only Silver polished 0.025
relevant when radiation is an important contribution to the total heat transfer. For natural convection cases,
this contribution might well be 40%. When the choice is between an emissivity of 0.05 and 0.1, the Steel polished 0.06
radiation contribution is 2 to 4% - minimal. When the choice is 0.7 to 0.9, matters are different. Most heat oxidized 0.6
transfer simulation software that support radiation heat transfer, assume the following simplifications: Silicon difficult 0.3 - 0.8
 surfaces diffuse, grey (sometimes specula [mirror-like]), opaque
 surfaces isothermal Tin bright 0.07
 surfaces uniformly irradiated Tungsten polished 0.05
 medium is transparent for all relevant wavelengths

In summary, differences exist between experimental data and simulation results when radiation is a major
factor, even when all other data are known to within 1%. visible

highly polished metals, foils, and films

liquids
polished metals
liquids
liquids
metals untreated
liquids X-rays infrared
liquids
liquids metals oxidised ultraviolet microwave

liquids oxides and ceramics thermal radiation

gamma rays
carbon, graphites

minerals, glasses liquids

vegetation, skin, water

liquids
liquids
special paints, anodised finishes
liquids λ μm

0 0.2 0.4 0.6 0.8 1

Electromagnetic spectrum
Surface emissivity ε

Table 5.16 shows typical material normal total emissivity values at 20°C.
173 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 174

Natural convection heat transfer coefficient Substrates

Metal sheets: DCB (Direct Copper Bonding) Metal sheets: IMS (Insulated Metal Substrate)
The convective heat transfer coefficient h, for various geometry arrangements are given by equations AMB (Active Metal Brazing) Multilayer-IMS
(5.60) and (5.61), as applicable, in conjunction with Table 5.17.
¼ Thick film layers: TFC (Thick Film Copper)
 T 
h  kh   (5.60)
 D  DCB (Direct Copper Bonding)
¼
 T  Power modules with IGBTs (or MOSFETs) and freewheel diodes commonly use substrates made of
h  kh   (5.61) DCB-ceramics with Aℓ203 or AℓN isolation that combine good thermal conductivity and high isolation
 L  voltage.
where ΔT is temperature difference, K For DCB, copper surfaces 200μm to 600μm thick, typically 300μm, are applied to the top and bottom
L is length, m surfaces of the isolation substrate material (0.25mm to 0.85mm thick, typically 0.5mm) by eutectic melting
D is diameter, m at between 1065°C and 1083°C. The sandwiched copper oxide layer helps adjust for the different thermal
expansion rates. After the necessary track structure for the module circuitry has been etched into the top
Table 5.17: Heat transfer coefficient constant, kh side copper surface, the chips are soldered on, and contact connection on the chip top side is effected by
bonding. The bottom side copper of the DCB-ceramic substrate is fixed to the module base plate (about
3mm thick copper) usually by soldering, as seen figure 5.8. Other module types do not necessarily require
Dependant geometrical constant
Geometry
parameter kh
equation a base plate and the soldering procedure may be avoided.
DCB AMB
Vertical cylinder or plate Vertical height L 1.42 (5.61)
Horizontal cylinder Diameter D 1.32 (5.60)
Eutectic copper- copper
4  area Upper surface hot 1.32 copper oxide Solder
Horizontal plate L (5.61) Ceramic Silver/copper/titanium
perimeter Lower surface hot 0.59
initial Aluminium oxide
Vertical populated PCB Vertical height L 2.44 (5.61) fracture
Sphere Diameter D 1.92 (5.60) Figure 5.20. Direct copper bonding, DCB and active metal brazing, AMB.

5.11 Appendix: Ampacities and mechanical properties of rectangular copper busbars Advantages of the DCB-technology compared to other structures are mainly the high current conductivity
due to the copper thickness, good cooling features due to the ceramic material, the high adhesive strength
Effect of emissivity and number of busses on ampacity (current carrying capacity) – data in Table 5.18 of copper to the ceramic (reliability), and the optimal thermal conductivity of the ceramic material. Possible
shows how higher emissivities improve ampacity. Multiple busses also affect ampacity in a nonlinear failure due to cracking, termed conchoidal fracture, starts at the copper edge, as shown in figure 5.20, and
relationship. Ampacity may be raised by increasing heat dissipation with convection cooling or surface progressively extends under the copper interface area.
treatments. Surface treatments which improve emissivity are oxidation or thinly coated, flat, inorganic
based spray paints. AMB (Active Metal Brazing)
The AMB process (brazing of metal foil to a substrate) has been developed based on DCB technology.
Table 5.18: Ampcapacity The advantages of AMB-substrates with AℓN-ceramic materials compared to substrates with
Aℓ203-ceramic materials are lower thermal resistance, lower coefficient of expansion, and improved partial
discharge capability.
Ampacity, A
number of 30°C rise 50°C rise 65°C rise Figure 5.20 illustrate the differences between DCB and AMB. AMB offers higher partial discharge levels
6mm x 100mm
busses emissivity ε emissivity ε emissivity ε than DCB.
0.15 0.4 0.7 0.9 0.15 0.4 0.7 0.9 0.15 0.4 0.7 0.9
1 1100 1250 1400 1600 1500 1700 1900 2000 1700 1950 2200 2300 IMS TFC
2 1900 2050 2200 2300 2550 2750 2950 3100 2950 3200 3400 3600 Chip: Si, 280μm
Printed conductor
3 2500 2700 2850 3000 3400 3600 3850 4000 3950 4200 4500 4600
copper Solder: SnAg, 80μm
Cu 100μm Cu, 30 - 200μm
4 3100 3300 3450 3600 4200 4400 4700 4800 4900 5100 5400 5600 Isolation Isolation Al2O3, 380μm
6mm spacing. Polyimid 25μm
Adhesive: silicone, 35μm
Ampacities of bus bar systems of other configurations must be calculated taking into account size, spacing, number of
bus bars, and overall skin-effect ratio. Baseplate
Cu or Al, 3mm

5.12 Appendix: Isolated substrates for power modules Figure 5.21. Basic module structure of: (a) an IMS power module and (b) a TFC power module.
Currently used isolated substrates for power modules are:

Isolation material IMS (Insulated Metal Substrate)

Ceramic: aluminium oxide Aℓ203 Organic: epoxy IMS is mainly used in the low-cost, low-power range and is characterized by direct connection of the
aluminium nitride AℓN polyimide (Kapton) isolation material to the module base plate. For insulation, polymers (such as epoxies, polyamides) are
(beryllia oxide Be0) applied to an aluminium base plate, as seen in figure 5.21a. The upper copper layer is produced in foil
(silicon nitride Si3N4) form and glued onto the isolation substrate (similar to PCB production) and is patterned by etching.
Advantages of IMS are low costs, filigree track structure (possible integration of driver and protection
175 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 176

circuitry), substrate high mechanical robustness, and relatively wide substrate areas, compared to DCB. Al bonding wire
The thin isolation layer, however, leads to comparably high coupling capacitances associated with the Soldered
mounting surface. Also the thin upper copper layer only provides a comparably low heat spreading, which Bond Bond IGBT Cu terminal
Bond
is improved by additional metallised heat spreading layers under the chips or by adding Aℓ-particles to the
isolation layer. Diode

TFC (Thick-Film-Copper)-thick film substrates Chip Solder

Just as with DCB, the basic material for thick film substrates is an isolation ceramic, which is glued directly Substrate
onto the base plate or a heatsink by means of silicone or applied by soldering, as shown in figure 5.21b. Base Plate Solder
The tracks on the top of the ceramic substrate are made of copper and are applied by screen printing. The Screw
power semiconductor chips or other components are soldered or glued onto the track pads. Thermal Base plate
Grease

TFC technology can also be combined with standard thick film technology. Since low resistances may be
produced by the paste materials which are usually applied in thick film technology, and since isolated
tracks can be arranged on top of one another and connected together, quite a number of system
components may be densely integrated. However, the filigree tracks, typically 15μm thick, limit the current Heatsink
capability of such structures to about 10A.

Ptot1 Figure 5.22. Power module with DCB substrate: (a) basic structure and (b) thermal model.
Ptotn

High-temperature lead-free transient liquid phase (TLP) die and substrate attach methods

While silicon semiconductor technology is limited to junction temperatures of about 200°C, emerging SiC
technology could exploit 600°C operating temperatures, were it not for die and substrate attachment
limitations and aluminium thermal bonding stressing.

The high-temperature, lead-free silver-tin transient liquid phase (TLP) die attach process for connecting
the SiC power devices to a nickel-plated direct bond copper (DBC) or direct bond aluminium (DBA) power
substrate (aluminium nitride or silicon nitride) shown in figure 5.23a, allows junction temperature operation
in excess of 400°C.

Similarly the high-temperature, lead-free nickel-tin TLP attachment process for connecting the
nickel-plated DBC or DBA power substrate to a metal matrix composite, MMC, base-plate allows
operation to temperatures in excess of 400°C.

The baseplate of the power module can utilize a lightweight copper-molly (CuMo) metal matrix composite
(MMC) that has a coefficient of thermal expansion (CTE) characteristic closely matching that of the SiC
power die. This CTE matching reduces thermal-stress mismatches, thus improving the long-term thermal
stressing reliability of a power module. The common use of copper as base plate material is for its
advantages of high thermal conductivity, easy mechanical handling, galvanic plating and acceptable
pricing. Disadvantages are non-reversible changes of mechanical properties above 300°C and the
mismatch of the coefficient of thermal expansion (CTE) to the ceramic substrate. The mismatch of the
CTEs is Cu (17ppm/K) and AℓN (7.3ppm/K). Due to this mismatch thermal stress occurs between the
materials and generates mechanical strain on the solder. AlSiC is an alternative baseplate material for
significantly improved thermal cycling properties.

SiC die DBA

substrate

to to

DBA base-plat
substrate e
(a) (b)
Figure 5.23. Cross-section of various layers in the lead-free 400°C high temperature SiC power module:
(a) Ag-Sn TLP die attach and (b) Ni-Sn TLP substrate attach.
177 Power Electronics Chapter 5 Cooling of Power Switching Semiconductor Devices 178

Problems Based on thermal considerations, what is the maximum current rating of the current sink and
under such conditions, what is the heat-sink temperature?
5.1. A thyristor bridge switches at 1 kHz and the total energy losses per thyristor are 0.01 Joule per What power rating would you suggest for the 1 Ohm current measurement resistor?
cycle. The thyristors have isolated studs and a thermal resistance of 2 K/W. The heat sink has a Are there any difficulties in operating the transistor in the linear region in this application if it is in a
thermal resistance of 1.8 K/W. Calculate the maximum number of thyristors that can be mounted 120 W dissipation package which is derated according to figure 5.24b?
on one heat sink if the thyristor junction temperature is not to exceed 125°C in an ambient of 40°C. [1.36 A, 69°C, > 2 W]
What is the heat sink temperature?
[3 devices, Ts= 94°C] 5.4. A power IGBT switches a 600 V, 25 A inductive load at 100 kHz with a 50 per cent on-time duty
cycle. Turn-on and turn-off both occur in 100 ns and the collector on-state voltage is to be 2 V.
Calculate the total power losses, Pd, of the switch.
5.2. A transistorised switch consists of two IGBTs and two 1 Ohm current-sharing resistors, as shown The switch has a thermal resistance Rθj-hs = 0.05 K/W, and the water-cooled heatsink provides a
in figure 5.24, mounted on a common heat-sink. Each transistor has a thermal resistance Rθj-hs of thermal resistance Rθhs-w = 0.05 K/W. Calculate the operating junction temperature if the water for
2 K/W, while each resistor has a thermal resistance Rθ r-hs of 1 K/W. The maximum switching cooling is maintained at 35°C.
frequency is 1 kHz and the maximum duty cycle is 99.99 per cent. The heat-sink thermal The 25 A steady state load current is stepped to 200 A. Calculate the surge power dissipation Ps,
resistance Rθ hs-a is 1 K/W. The energy losses per transistor are 5 mJ/A per cycle. If the ambient at 200 A, assuming transistor switching and on-state characteristics remain unchanged.
temperature is 30°C, maximum allowable junction temperature is 150°C, and the maximum The junction temperature for a power surge during steady-state operation is given by case (e) in
allowable resistor internal temperature is 100°C, calculate the switch maximum current rating Table 5.11.
based on thermal considerations. What are the operating temperatures of the various With the aid of figure 5.10, determine the junction temperature at the end of a 0.1s, 200 A pulse.
components, assuming ideal current sharing? How long is it before the junction temperature reaches T j = 125°C, with a collector current of 200
[6.88 A, Tr = 100°C, Ths = 88°C, Tj = 122.5°C] A?
(Assume Rθc-hs = 0).
[175 W, 52.5°C, 1400 W, 112.6°C, 0.5 s]

5.5 Rework example 5.6 finding the case temperature when the switching losses equal the on-state
loss.

5.6 A 20kHz, step-down, 340V dc chopper feeds an inductive load with an average current of 20A and
T T a peak-to-peak ripple of 20A. Thus the MOSFET switch on-state current rise from 10A to 30A while
the freewheel diode current falls from 30A to 10A when the switch is off. The MOSFET on-state
resistance is 0.1Ω and has switch on and off times of 100ns and 200ns respectively. The switch
duty cycle is 75% and it has a thermal resistance Rθ j-c of 0.4K/W and is mounted on a heatsink of
thermal resistance Rθc-a of 0.6K/W in a maximum ambient temperature is 40°C.
Calculate:
i. switching losses, using equations 7.9 and 7.10
ii. switch on-state losses
iii. MOSFET junction operating temperature
Figure 5.24. Problem 5.2. [3.4W + 20.4W = 23.8W; Irms = 15.8A, 25W; Tj = 88.8°C]

5.3. Figure 5.25a shows the circuit diagram for a power current sink which utilises a 40V source. Both
the IGBTs T and wire wound resistors R are mounted on a common heat-sink, of thermal
resistance Rθ hs-a = 1 K/W. The transistor has a thermal resistance of 2 K/W from the junction to the
heat-sink, and 10 K/W from the junction to air via the transistor casing exposed to the air. The
resistor has a mounting thermal resistance from the insulated wire to the heat-sink of 1 K/W and
10 K/W from the wire to the air via its casing exposed to the air. The maximum transistor junction
temperature is 423 K, the maximum resistor wire temperature is 358 K and the ambient air
temperature is 303 K.

Figure 5.25. Problem 5.3.