Why DFT?

– To make design testable and to find the physical defect in the silicon chip after manufacturing

What are the topics in DFT?

– Scan insertion , ATPG , Simulation , EDT , JTAG , IJTAG , MBIST .

What is DFT and Why DFT require ? Can we achieve DFT goals by any other method ?

Due to complex design it is impossible to use some manual check for e.g Connectivity check by using
DMM . For that we can JTAG Boundary scan chain test circuit which is part of DFT. So dft is dominating as
up now.

what is effect of technology shrink on DFT work/Methodology ?

-Due to shrink in technology complexity in handling DFT task got increased. Space acquired by DFT
circuitry on chip is around 33% of total area of chip, so we have to make optimized architecture of DFT
and as the technology got shrinked the physical defects on silicon chip may increase so DFT plays
important role to check quality and increase the faith on chip.

what is mean by testability/Controllability/observability/coverage

-Testability: Each and every node in the design should be tested {ideally}. That is testability of the circuit

-Controllability: To test each and every node in the design , that node should be controllable ,so that we
can control the value on that node [eg. Values 0 or 1] to test that node.

-observability: similar to controllability node should be observable,so that the we can read the value of
that node to check the fault.

– coverage : How much percentage of the design we are able to cover to find out the fault in design that
is called as coverage.

Two types oo coverage : 1. Test 2. Fault coverage

what is the difference between fault coverage and test coverage ?

-Test coverage=detected faults/testable faults.

-Fault coverage=detected faults/ testable+untestable.

Where DFT part fit in ASIC design flow ?

-DFT come into picture after the synthesis .

– MBIST : may be at RTL or Gate level depends

why the scan frequency is less than functional frequency ?

-Power dissipation is important factor during switching, if frequency is high then switching is more and
power dissipation is more , so it is possible to burn the chip.

-At the time of test all design is in active but in real application entire chip will not be active only the
required part of the design will be active
-So to avoid the power and head dissipation which causes burning of chip test frequency is less than
functional frequency.

What is the use of MBIST ?

– to test Memories in the design

what is the use of BSCAN ?

-BSCAN : Boundary scan is standard

-In BSCAN boundary cell will be added on the primary I/O pins of the chip . This chain will be used to test
the interconnect of IC’s on PCB .

-This chain is controlled through JTAG.

what is a ICG(Integrated Clock Gating) ?

ICG cell basically stops the clock propagation through it when we apply a low clock enable signal on it.
This phenomenon is termed clock gating. We use the ICG cell to stop the clock signal propagation to a big
group of logic cells when the group is not required to operate

1. Why do we use Latch in ICG why not flip flop? (by Ramcharan)

Ans:

1. As we not that flip flop will capture the data only at the edge of the clock signal so any data change
between one active edge to next active edge will not be captured.

2. If we use -ve edge FF the setup timing requirement for FF to ICG will be half cycle which is again
difficult to meet in case of ICG placed near the sink.
what is yield and DPPM? and what is the difference between them ?

Fraction (or percentage) of good chips produced in a manufacturing process is called the yield.

Defective Parts (test escapes) Per Computed for time zero is DPPM.

scan chain reordering

It is the process of reconnecting the scan chains in a design to optimize for routing by reordering the
scan connection which improve timing and congestion. Based on timing and congestion the tool
optimally places standard cells.

which scan style are there in scan insertion ?, Difference between them ? , which one you will prefer for
scan insertion ?

What is mean by Scan Stitching

The scan chain stitching is made power aware by placing flip-flops with higher test combination
requirements at the beginning of scan chains, while flip-flops with lower test combination requirements
are put toward the end of scan chains.

which fault model available for pattern generation ?

-Stuck at

-Transition fault

-bridging fault
-IDDQ fault

what is a ICG(Integrated Clock Gating) ?

-Clock gaters are used to control the clock of block depend upon requirement. We can off the clock of
particular part of design so that we can control power dissipation

DRC Violations that u have faced during Scan Insertion

6 DRC Report Two DRC violations observed during scan insertion, one is the clock violation and the other
is the reset violation. The clock has to be driven from the port pin, if the clock to a scan flip-flop is driven
from any other combinational logic or from data path then the clock violation occurs.

test point Insertion in dft

Test point insertion (TPI) involves adding control and observation points to the CUT. Observation points
involve making a node observable by making it a primary output or sampling it in a scan cell. Control
points involve ANDing or ORing a node with an activation signal

decompression logic

The decompressor logic consists of the LFSR(linear shift feedback register) along with the phase shift flip-
flops. The decompressor logic distributes the compressed patterns from the input channels to the scan
chains.

clock latency in dft

Clock Latency is the general term for the delay that the clock signal takes between any two points. It can
be from source (PLL) to the sink pin (Clock Pin) of registers or between any two intermediate points.

Clock latency = Source latency + Network latency

setup slack

Setup Slack = Required time - Arrival time

Wheather you are asking about scan style uses for patterns generation ?

If yes , then answer is “Multiplexed flop”

There are three scan style :- Multiplexed flop, Cloked Scan, LSSD(Level Sensitive Scan

Design)

what are wrapper cells and chains tell it's function

The wrapper chains can comprise of two distinct kinds of wrapper cells: shared and

dedicated. A shared wrapper cell is really a current functional flop in the structure that

additionally shares duty as a wrapper cell. No extra rationale is required. One just

needs to distinguish the right functional flop as the shared wrapper cell and stitch it

into the wrapper chains. A dedicated cell is another cell that is added to the plan. In its

most straightforward structure, it very well may be only a mux and a flop. In any case,

it can likewise be progressively mind boggling.

in DFT why is a slow clock used forshifting the patterns

There are two primary reasons why patterns shift-in and captured output shift-out

cannot be done at higher speed.

1. Test clock comes from out side a chip. ATE provides the clock. Clock enters the chip

though a GPIO (general purpose IO) pad. So the max frequency at which clock can

enter the chip is limited by the ATE probe capacitance and the input capacitance of

the pad. GPIOs have high input capacitance.

2. Conceptually, during shift phase, all flops in your design are configured as shift
registers and then you shift in all the patterns. Same thing happens during shift out.

Thus, the flops toggle together for many clock cycles. Since all the flops are toggling

all the down stream combinational logic also toggle along with then. This scenario will

never occur in functional modes (while chip is actually working inside a device).

This means there is a lot of dynamic current going to be drawn from the power grid

during shift phase. So the chip power grid needs to support this much dynamic

currant and dynamic IR drop needs to be signed off for shift mode otherwise logic will

malfunction during shift phase.

Now increasing shift frequency further will further increase the dynamic current

demand your power grid needs to support.

Thus, you need to limit the shift frequency to the extent your power grid can support.

describe about occ in dft

On -chip clock controller is the logic inserted on the SOC for controlling clocks during

silicon testing for defects on ATE (Automatic test Equipment). OCC enables the ATspeed/Transition
testing of the Logic by generating two clock pulses at speed during

capture phase. So OCC enables the pulse control of the clock during Test mode

through clock chain (chain comprising all the OCC logic flops in a chain)

Without OCC you need to provide At-speed pulses through Top pins called PADS. But

Pads has limitation in terms of maximum frequency they can support. OCC on other

hand uses internal PLL clock for generating 2 pulses for test.

1. What is scan insertion?

In the scan insertion we add extra circuitry to providing controllabilityand observability.Scan insertion is
nothing but control the inputs of gates and observe the output of the pins .

2.What is OCC?
Without OCC can we generate two pulses (alternative)Occ is on chip clock controller it controls the
switching between ATE low frequency and functionalfrequency.We can’t generate two pulses with out
occ.

3.Explain slow to fall transition faults in circuit.

Transition faults occur when gate delay is larger than the expected delay.Step-1:initialization the vector
one(V1) is one , second vector is stuck-at one.Step-2: launching the second vector(V2) means forcing the
opposite value to vector2Step-3: fault propagation.

4. Once we got 100% scan? Why we are facing again DRC’S in ATPG?

In scan insertion we check theclock and reset is properly connected or not.In ATPG we check the C6-
data considered as the clock, C2-set/reset considered as the clock.

5. Scan operation with diagram

Shift-incaptureshiftout

6.DFT violations

1. clock rule violations: means the clock is not controllable from the primary inputs.

2.Reset rule violations: means these type of violations occur when the reset signal is not
controllablefrom the primary pins.

3.combinational feedback violations: means in which the faulty values is again going to the
inputs .because of this coverage is less. So control and observe the values . we can break the loops by
applyingfault free value

edt violations k19 to k22

DRC for Channel Input Pipelining

The K19 and K22 design rules detect errors in initializing the channel input pipeline stages. Ifthe pipeline
is not correctly initialized for the first pattern, K19 reports mismatches on the EDTblock channel inputs -
assuming the hierarchy is not dissolved and the EDT logic is identified. Ifthe EDT logic channel inputs
cannot be located, for example because the design hierarchy wasdissolved, K19 reports that Xs are
shifted out of the decompressor. On the EDT logic channelinputs, the simulated values would mismatch
within the first values shifted out, while the rest ofthe bits subsequently applied would match.If the
pipeline is correctly initialized for the first pattern and K19 passes, but the pipelinecontents change
(during capture or the following load_unload prior to shift) such that it nolonger contains zeros, K22 fails.
K19 and K22 detect these cases if input channel pipelining isdefined and issue warnings about the
possible problems related to channel pipelining.

DRC for Channel Output Pipelining

The K20 rule check considers channel output pipelining, in addition to any compactorpipelining that may
exist. K20 reports any discrepancy between the number of identified andspecified pipeline stages
between the scan chains and pins (including compactor and channeloutput pipelines).If the first stage of
the channel output pipeline is TE instead of LE, this results in one less cycleof delay than expected, which
also triggers a K20 violation. If the first stage is TE, and youspecify one less pipeline stage, those two
errors may mask each other, which means no violationis reported. However, this may result in
mismatches during serial pattern simulation