TED (21) – 2041 REVISION 2021

SECOND SEMESTER DIPLOMA EXAMINATION IN ENGINEERING

AND TECHNOLOGY
(Common to BM / EC / EL)

BASIC ELECTRONICS CIRCUITS

MODEL QUESTION PAPER – SET-1

Time: 3 hours Maximum Marks: 75

PART A

I. Answer all questions in one word or one sentence. Each question carries one mark.

(9 x 1 = 9 Marks)
An intrinsic semiconductor at absolute zero temperature behaves
1 M 1.01 U
like ...............
2 Name a trivalent impurity used in extrinsic semiconductor. M 1.01 R
Write the equation to calculate the dynamic resistance of a forward
3 M 1.03 R
biased diode.
In a transistor .................. region is larger in size and medium in
4 M 2.01 R
doping.
5 Draw symbol of PNP transistor and mark its terminals. M 2.01 R
6 FET is a .................... controlled device. M3.01 R
7 Draw the equivalent circuit of a UJT. M3.01 R
State the relationship between Xc and R in a good RC
8 M 4.03 R
differentiator circuit.
9 State the need of filter in rectifier circuit. M 4.02 U

PART B

II. Answer any eight questions from the following. Each question carries 3 marks

(8 x 3 = 24 Marks)

1 Differentiate drift current and diffusion current. M 1.02 U

Define the terms forward voltage drop, maximum forward current,
2 M 1.04 R
and peak inverse voltage of PN diode.
3 Define reverse saturation current in PN diode. M 1.03 R
4 Define barrier potential in PN junction. M 1.02 R
 5 Compare emitter, base and collector regions in a BJT. M 2.01 R
6 Derive the expression for  in terms of . M 2.03 U
7 Explain the transistor action. M 2.05 U
8 State why CE configuration is widely used in amplifiers. M 2.04 R
9 Draw VI characteristics of UJT and mark operating regions. M 3.03 R
10 Differentiate linear and non linear wave shaping circuits. M 3.03 U

PART C

Answer all questions. Each question carries seven marks

(6 x 7 = 42 Marks)
III Compare intrinsic and extrinsic semiconductor. M 1.01 R

OR

IV Draw the atomic structure and explain the formation of N type M 1.01 U
semiconductor.

V With the help of a sketch explain the operation of NPN transistor. M 2.02 U

OR

VI Draw output characteristics of NPN transistor in CE configuration,

and explain various operating regions. M 2.04 U

VII Draw structure of N channel JFET and explain its principle of M 3.01 U
operation.

OR

VIII Draw the drain characteristics of N channel depletion type

MOSFET. Compare MOSFET and JFET. M 3.03 R

IX Draw drain characteristics of N channel JFET, and discuss various M 3.03 U

operating regions.

OR

X Draw the structure and explain the working of N channel depletion M 3.02 U
type MOSFET

XI Design a diode circuit to develop an output as shown, and explain M 4.04 A

operation. Assume the diode is ideal, and suitable sine wave as
 input.

OR

Design a diode circuit to shift the base of the sine wave input M 4.04 A
XII
VmSinet to –Vm, and explain operation

XIII Draw circuit diagram and explain operation of RC differentiator. M 4.03 U

OR

XIV Draw a voltage quadrupler circuit, and explain its operation. M 4.05 U
TED (21) – 2041 REVISION 2021

SECOND SEMESTER DIPLOMA EXAMINATION IN ENGINEERING

AND TECHNOLOGY
(Common to BM / EC / EL)

BASIC ELECTRONICS CIRCUITS

MODEL QUESTION PAPER – SET-2

Time: 3 hours Maximum Marks: 75

PART A

I. Answer all questions in one word or one sentence. Each question carries one mark.

(9 x 1 = 9 Marks)

1 Name any donor type impurity used in extrinsic semiconductor. M 1.01 U

The width of depletion layer within a PN junction increase with
2 M 1.02 R
....................... bias.
3 ........................ configuration offers highest voltage gain. M 2.04 R
In saturation mode of operation, collector base junction has
4 M 2.02 R
........................... bias.
5 A field effect transistor operates using ............... carriers only. M 3.01 R
Operation of a N channel depletion type MOSFET needs a
6 M 3.02 R
................. gate voltage.
7 Draw the symbol of N channel MOSFET M 3.01 R
State equation for calculating DC output voltage in a centre tap
8 M 4.01 R
full wave rectifier.
........ is the output of an integrator when the input is rectangular
9 M 4.03 U
wave.

PART B

II. Answer any eight questions from the following. Each question carries 3 marks

(8 x 3 = 24 Marks)

1 List the features of intrinsic semiconductor. M 1.01 R

Draw the energy band diagram of conductor, semiconductor and
2 M 1.03 R
insulator.
 Draw forward VI curve of a diode and show how to calculate
3 M 1.03 R
static and dynamic resistance.
4 Explain zener breakdown. M 1.03 U
State biasing conditions for active, saturation and cut-off modes of
5 M 2.02 R
operation in a BJT.
Draw transfer characteristics of N channel depletion type
6 M 3.03 R
MOSFET, and mark various regions.
7 Write note on pinch off voltage of JFET. M 3.02 U
Define dynamic drain resistance, trans-conductance, and
8 M 3.03 R
amplification factor for JFET.
Draw transfer curve of N channel JFET. Write expression for
9 drain current in terms of maximum drain current and pinch off M 3.03 R
voltage.
Compare capacitor and inductor type filters used in power
10 M4.02 R
supplies.

PART C

Answer all questions. Each question carries seven marks

(6 x 7 = 42 Marks)
III Draw the atomic structure and explain the formation of P type M 1.01 U
semiconductor.

OR

IV Draw a sketch and explain the formation of PN junction and M 1.02 U

depletion region.

V Draw the symbol of NPN and PNP transistor. Draw structure of M 2.01 U
NPN transistor and explain features of different sections.

OR

VI Draw output characteristics of NPN transistor in CB configuration, M 2.04 U

and explain various operating regions.

VII Draw input characteristics of NPN transistor in CE configuration, M 2.04 U

and explain the behaviour. Show how input resistance is
calculated.

OR

VIII Draw sketch and explain mechanism of current flow and current M 2.02 U
relations in NPN transistor.
IX Compare JFET and BJT. M 3.04 R

OR

X Draw structure and explain working of UJT. M 3.02 U

XI Draw circuit diagram and explain operation of RC integrator. M 4.03 U

OR

XII Draw circuits and explain operation of half wave and full wave M 4.04 U
voltage doubler.

XIII Design a diode circuit to develop an output as shown, and explain M 4.04 A
operation. Assume the diode is ideal, and suitable sine wave as
input

OR
XIV
Design a diode circuit to develop an output as shown, and explain M 4.04 A
operation. Assume the diode is ideal, and suitable sine
wave as input.
 Scoring Indicators

Model Question Paper Set 1

BASIC ELECTRONIC CIRCUITS

Q Scoring Indicators Split Sub Tota

No score Total l
scor
e

PART A 9

I. 1 Insulator 1

I. 2 Gallium, indium, aluminium, boron(any one) 1

I. 3 Rd=Vf/f or change in forward voltage/change in current 1

I. 4 Collector 1

I. 5 1

I. 6 Voltage 1

I. 7 1

I. 8 Xc>>R 1

I. 9 To remove ripple from rectifier output. 1

PART B 24

II. 1 Diffusion current- due to movement of carriers from a high 1.5 3

density area to low density area in a semiconductor without
 applying external potential.
Drift current – due to movement of carriers inside
1.5
semiconductor under influence of external field.

II. 2 1*3 3
Forward voltage drop, VF – The maximum voltage drop across
diode, for a given forward current and device temperature.

Maximum Forward Current IF(max) - is the maximum forward

current allowed to flow through the device, without damaging.
Peak Inverse Voltage (PIV) - is the maximum allowable
Reverse operating voltage that can be applied across the diode
without damage occurring to the device.

II. 3 When the diode is reverse biased then the depletion region 3 3
width increases, majority carriers move away from the junction
and there is no flow of current due to majority carriers. But
thermally produced electron hole pairs will cause current to
flow in the circuit. This current is usually very small (in terms
of micro amp to nano amp). Since the current is almost constant
known as reverse saturation current ICO.

II. 4 3 3

When PN junction is formed, immobile +ve ions appears near

junction in N side and _ve ions on P side. This layers of charges
creates field which prevents further movement of charges
across junction. This is barrier potential ; about .6v for Si.

II. 5 Emitter – supplies carriers, heavily doped , medium size. 3 3

Base – passage between emitter and collector, small, light
doping.
Collector – collects the carriers, large, medium doping.

II. 6 Ie=Ib+Ic; 3 3
Ie, Ie/Ic=Ib/Ic+Ic/Ic=1/=1/+1
1/=(1+)/
Ie, = /( +1)

II. 7 A transistor transfers the input signal current from a low- 3 3

resistance circuit (forward biased EB junction)to a high-
resistance circuit(reverse biased CB junction).- Ie=Ic. This is
the key factor responsible for the amplifying capability of the
transistor.

II. 8 The CE configuration provides both High Current and Voltage 3 3

gain unlike other configurations like CC (High current gain but
 voltage gain less than unity i.e 1) and CB (High voltage gain
but current gain less than unity). i/p and o/p resistance are also
favorable.

II.9 3 3

II.10 In the non-linear circuit,, the non-linear devices like diodes are 3
used, not have any linear relationship between the current &
voltage
In the linear circuits, the linear element like resistor, capacitor
and inductance are used and there will be a linear relationship
between the voltage and current.

PART C 42

III 7*1 7 7

(any 7 points)

IV 3 7 7

In intrinsic semiconductor crystal, all atom forms covalent 4

bonds with four adjacent atoms, no free electrons, acting as
 insulator at absolute zero. Impurity atoms with 5 valence
electrons when added, they form bonds with four atoms by
sharing four outer band electrons, but fifth one pushed to next
free level, where it is free to move. Every impurity atom
donates one conducting electron, produce n-type
semiconductors.

V 3 7 7

E-B junction forward and C-B reverse. Electrons entering 4

emitter causes Ie flowing out. These electrons crossing
junction, and few recombines with +ve carriers in base causing
base current Ib. Only few electrons recombines as base width is
less and doping is low, so Ib is very low. Majority of electrons
from emitter crossing B-C junction and reaching collector,
going to +ve terminal of Vcb causing collector current Ic.
Collector current almost same as emitter current.

VI 3 7 7

plot of the collector current, IC, versus the collector-emitter 4

voltage, VCE, for various values of the base current, IB.

When Ib=0, cut off region, Ic is vary small (leakage current)

When Vce increases from zero collector current increases
rapidly, Ic=b.-saturation region.
Ic saturates around Vce=1V, and no much increase in Ic with
Vce. Active region.
VII 3 7 7

PN junction between gate and channel; depletion region more 4

in channel due to less doping. Drain +ve with source, andno
gate voltage, drain current flows through channel. –ve gate
voltage widens depletion region, drain current reduces due to
narrow channel.for a set drain voltage, drain durrent is function
of gate –ve voltage. JFET- voltage controlled device. The gate
voltage at which drain current becomes zero is pinch off
voltage.

VIII 4 7 7

(any three points)

IX 4 7 7

Plot between Id and Vds for different Vgs. Vg & Vds=0 no Id.
3
As Vds increases, Id increase initially- ( ohmic region).
Increase in Vds increases reverse bias between the gate drain
PN junction, increases width of depletion region in channel,
restricts channel width, Id restricted even with rise in
Vds.(pinch off/saturation region).
At very high Vds, breakdown occurs in channel, damaging
channel(break down region).
Increase in –ve Vgs reduces channel width, and Id falls for
same Vds

X 3 7 7

No gate voltage, drain current flows due to Vds. In depletion 4

mode, negative gate potential repels electrons in channel,
increases its resistance, reducing drain current. At Vgg(off),
channel shuts off and drain current becomes zero.
Enhancement mode - With +ve gate voltage, more electrons
induced in to the channel, and drain current increases with
increase in Vgg.

3 7 7
XI

Biased –ve clipper. During –ve half cycle, and in +ve half cycle
4
for Vi<V, diode conducts, and o/p same as V. for Vi>V, diode
reverse biased, o/p same as Vi.
XII 4 7 7

-ve clamper circuit. During C charges to Vm through D.

3
capacitor voltage Vm added with i/p voltage, like a battery, to
shift o/p reference to –Vm.

XIII 2 7 7

RC differentiator. Vi=Vc+Vr. o/p Vo is voltage across R, ie Vr.

Circuit current i=Vc/Xc=Vr/R.
If Xc>>R, Vc=Vi.
i=q/t; dq/dt. Q=Vc*C. ie 5

or
Out put Vo= i*R. ie o/p voltage proportional to the integral of
Vi

; provided Xc>>R, and RC<<period of input.

XIV 3 7 7

During the positive cycle, diode D1and D3 forward biased and , 4

C1 charges to Vm. diodes D2 and D4 are reverse biased.

During the negative cycle, through D2, C2 charges to 2Vm, as

C1 voltage added with input voltage.

Similarly, C3 charges to 2Vm through D3 (Vi-Vm+2Vm)

during +ve half, and C4 to 2Vm during –ve half cycle. Voltage
across C2and C4 is 2Vm+2Vm=4Vm

Scoring Indicators
 Model Question Paper II

BASIC ELECTRONIC CIRCUITS

Q No Scoring Indicators Split Sub Total

score Tot Score
al
PART A 9
I. 1 Phosphorus, antimony, arsenic, bismuth ( Write any one) 1 1

I. 2 Reverse bias 1 1
I. 3 Common emitter 1 1
I. 4 Forward bias 1 1
I. 5 Majority carriers. 1 1
I. 6 Negative. 1 1

I. 7 1 1

I. 8 2Vm/ 1 1
I. 9 Saw tooth 1 1
PART-B 24

II. 1 1)materials in pure form show the property of semiconductor 1*3 3 3

are called intrinsic semiconductor.

2)the number of free electrons in the conduction band is

equal to the number of holes in the valence bond.

3)Its electrical conductivity is low.

4)Its electrical conductivity depends on temperature only.

5)It is of no practical use. (any three)

II. 2 1*3 3 3

Conductor semiconductor insulator

II. 3 3 *1 3 3

Dyanamic resistance:

rd= ΔVd/ΔId

Static resistance:

Rd= Vd/Id

II. 4 When the high electric-field

field is applied across the PN 3 3
junction diode,, under reverse bias, then the electrons start 3
flowing across the PN-junction,
junction, and current flows in reverse
bias. Happens in diodes with thin depletion region. Generally
not damaging the junction.
II. 5 1*3 3 3

II. 6 3 3 3

II.7 For VGS=0 V, the value of VDS at which ID becomes 3 3 3

essentially constant is the pinch
pinch-off voltage, VP. For a given
JFET, VP has a fixed value. A continued increase in VDS
above the pinch-off
off voltage produces an almost constant
drain current. the drain current is a function of rev
reverse bias
voltage at gate.
II. 8 This is the ratio of change of drain to source voltage (δVDS) 1+1+1 3 3
to the change of drain current (δID) at a constant gate to
source voltage (VGS = Constant). The ratio is denoted as rd.

Transconductance is the ratio of change in drain current (δID)

to change in the gate to source voltage (δVGS) at a constant
drain to source voltage (VDS = Constant).

The amplification factor is defined as the ratio of change of

drain voltage (δVDS) to change of gate voltage (δVGS) at a
constant drain current (ID = Constant).

II. 9 2 3 3

II.10 3 3 3

(three points)

PART-C 42
 3 7 7
III

In intrinsic semiconductor crystal, all atom forms covalent

bonds with four adjacent atoms, no free electrons, acting as
insulator at absolute zero. Impurity atoms with 3 valence 4
electrons when added, they form bonds with four atoms by
sharing three outer band electrons, and one bone has absence
of electron. It has ability to accept one electron, like a mobile
+ve charge, or known as hole. Every impurity creates one
hole, produce P-type semiconductors.

3 7 7

When the N-type semiconductor and P-type semiconductor

IV joined together free electrons from N side crosses to P side
and recombines with holes. Exposing immobile +ve ions in
N side, and _ve ions in P side near junction. The field thus
created prevents further flow of carriers- potential barrier.
This region called depletion region- with no carriers. 4
Forward bias reduces, reverse bias increases width.

V 2 7 7

Emitter – supplies carriers, heavily doped , medium size.

Base – passage between emitter and collector, small, light

doping.
 Collector – collects the carriers, large, medium doping. 2

VI 3 7 7

plot of the collector current, IC, versus the collector-base

voltage, VCb, for various values of the base current, Ie.

in saturation region Vcb is –ve, both junction forward

biased, collector current rises with Vcb.

Vcb more than zero, collector junction reverse biased, Ic=Ie 4

– i/p current (active region).

For Ie=0, cut off region, Ic = leakage current.

VII 3 7 7

Plot between i/p current Ib against i/p voltage Vbe, for

constant value of o/p voltage Vce. Like diode, no current up
to knee voltage ,about .6 for silicon, there after increases
rapidly. Ib very low as i/p impedance very high. With high 3
Vce, Ib low as width of depletion region increases in Base
region.
 i/p resistance ri=Vbe/Ib

VIII 3 7 7

E-B junction forward and C-B reverse. Electrons entering

emitter causes Ie flowing out. These electrons crossing
junction, and few recombines with +ve carriers in base 4
causing base current Ib. Majority of electrons from emitter
crossing base and reaching collector, going to +ve terminal
of Vcb causing collector current Ic.
So Ie=Ib+Ic. Ib is <<Ic. so Ie=Ic.
IX 1*7 7 7

X 3 7 7

Emitter region is heavily doped and close to B2. Inter base

Resistance Rbb =Rb2+Rb1, Rb2 resistance from B2 to PN
junction, Rb1 junction to B1. When biased as shown, EB1 4
region forward biased, which injects carriers in lower region
reducing Rb1, under forward bias. Voltage across Rb1
reverse biasing PN junction. Until Vee <Vd+Vrb1, junction
reverse biased and no emitter current(cut off). When
Vee=Vd+Vrb1(peak voltage-Vp), junction forward biased, Ie
start flowing, injecting carriers (conductivity modulation), to
reduce Rb1. It reduces net reverse bias, increasing Ie even at
lower Vee(negative resistance region), until valley voltage,
and there after, emitter voltage is almost constant, with
increase in Ie(saturation).
XI 2 7 7
 RC integrator circuit. Vi=Vr+Vc. Vo is Vc. i=Vr/r=Vc/Xc.
If Vr>> Vc, Vi=Vr. i=Vi/R. 5

Vo=Vc; Vc=Q/C; i*t/C; Vi*t/RC. ie output voltage Vo

; proportional to integral of input

provided R>>Xc, and RC>> time period of input
XII 1.5 7 7

Half wave doubler. During +ve half cycle, C1 charges to

Vm through D1.during –ve half cycle, C2 charges to 2Vm
2
through D2, C1 and source voltage.

1.5

Full wave voltage doubler. +ve half cycle, C1 charges to Vm

of i/p through D1. C2 charges to Vm during –ve half cycle.
DC o/p voltge across C1 and C2, Vm+Vm= 2Vm.

XIII 4 7 7

Combination diode clipper. During +ve half cycle of i/p, D1

forward biased and D2 reverse biased. D1 not conducting
until Vin <V1, and o/p same as i/p. Vin>V1, D1 conducts,
o/p =V1. Similar in –ve half cycle.
3
XIV 4 7 7

Biased +ve clamper. For Vi<V, diode reverse biased, o/p

3
same as Vi. Vi>v, diode conducts, o/p same as V