Code No: R2021041 R20 SET - 1

II B. Tech I Semester Regular/Supplementary Examinations, January-2023

ELECTRONIC DEVICES AND CIRCUITS
(Com to ECE, EIE, ECT)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions, each Question from each unit
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~~
UNIT-I
1 a) Derive an expression for continuity equation and explain its importance. [7M]
b) Define Fermi level and explain its significance in the energy band diagrams. [7M]

OR
2 a) Draw and explain the V-I characteristics of PN junction diode. [7M]
b) The reverse bias saturation current for a P-N junction diode (Silicon type) is 2μA [7M]
at 300K. Calculate the dynamic and static resistances at 100mV forward bias at
300K.
UNIT-II
3 a) Draw the symbol of Tunnel diode. Explain the construction and tunneling [10M]
phenomenon of Tunnel diode.
b) Explain how zener diode acts as a voltage regulator. [4M]

OR
4 a) With the help of neat circuit diagram, explain the operation of Bridge rectifier. [8M]
b) Compare the performance of inductive, L-section and π-section filters. [4M]
c) What is peak inverse voltage (PIV) of a diode in a rectifier circuit? [2M]

UNIT-III
5 a) Define α, β and γ of a transistor. Show how they are related to each other. [4M]
b) Explain about transistor as an amplifier. [5M]
c) Explain the operation of photo transistor. [5M]

OR
6 a) Explain the working of a depletion-type MOSFET. [7M]
b) For n-Channel JFET, VDS=10V and VGS is changed from 3V to 4V and drain [7M]
current changed -4mA to 2nA. Find gm , rd, and μ if VDS changes from 8 to 12V
and ID changes from 3 to 3.2mA at VGS=2.5V.

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Code No: R2021041 R20 SET - 1

UNIT-IV
7 a) Explain about the need for biasing in electronic circuits. What are the factors [6M]
affecting the stability factor?
b) A silicon transistor with β=70 is used in self biasing arrangement with [6M]
VCC = 15V, RC = 4.7KΩ. The operating point Q is at VCE = 8.2V, IC = 1.2mA.
Find the values of R1 and R2.
c) Define stability factor ‘S’. [2M]

OR
8 a) Explain how the Q-point is obtained graphically. [5M]
b) Explain diode compensation against variation in base-emitter voltage VBE. [6M]
c) In a silicon transistor circuit with a fixed bias, VCC = 10V, RC= 3KΩ, RB = 6KΩ, [3M]
β = 100, VBE = 0.7V. Find the stability factor.
UNIT-V
9 a) What are the benefits of h-parameters? [2M]
b) Draw the h-parameter equivalent circuit for a typical common base amplifier and [8M]
derive expressions for Ai and Av.
c) Define the three small-signal parameters of the FET. How are they inter-related? [4M]

OR
10 a) Give the complete analysis of CE transistor amplifier circuit using h-parameters [12M]
and derive the expressions for current gain, voltage gain, input impedance and
output admittance.
b) Draw the small signal model of FET. [2M]

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Code No: R2021041 R20 SET - 2

II B. Tech I Semester Regular/Supplementary Examinations, January-2023

ELECTRONIC DEVICES AND CIRCUITS
(Com to ECE, EIE, ECT)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions, each Question from each unit
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~~

UNIT-I
1 a) Explain about Hall effect. [5M]
b) The Hall-coefficient of specimen doped silicon is found to be 3.66 x 10-4 m3C; [4M]
the resistivity of the specimen is 8.93 x 10-3 Ω-m. Find the mobility and density
of charge carriers assuming single carriers conduction.
c) Explain about Law of junction. [5M]

OR
2 a) Briefly explain about Open circuited p-n junction and Biased p-n junction. [10M]
b) A silicon diode has a saturation current of 6.5 µA at room temperature 300K. [4M]
Calculate the saturation current at 400K.
UNIT-II
3 a) Explain the construction and operation of SCR. [8M]
b) Draw and explain the V-I characteristics of Varactor diode. [6M]

OR
4 a) With a neat sketch explain the operation of center tapped full wave rectifier and [9M]
derive the expression for ripple factor.
b) Determine the ripple factors of an L-section filter and Capacitive filter with [5M]
C=40μF, Vdc=12V, RL=10 KΩ, f=50Hz and L=10H used with FWR.
UNIT-III
5 a) Explain the various current components in BJT. [7M]
b) Draw the Ebers-Moll model of a transistor for NPN transistor and explain the [7M]
same.
OR
6 a) Define the following terms for a JFET: [7M]
(i) The pinch-off voltage
(ii) IDSS
(iii) IGSS
(iv) Drain resistance
b) Explain the working of an enhancement-type MOSFET. [7M]

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Code No: R2021041 R20 SET - 2

UNIT-IV
7 a) Draw the Fixed bias circuit and derive the expression for the stability factor S. [8M]
What are the limitations of this circuit?
b) What is thermal runaway in transistors? Obtain the condition for thermal [6M]
stability in transistors.
OR
8 a) Explain why bias stabilization is needed in a transistor amplifier circuit. [6M]
b) In a self biased circuit, the Q-point is established at VCE = 12V and IC = 2mA. [8M]
Determine RE, R1 and R2 so that S(IC0) = 3. Assume β=50, VBE = 0.7V,
VCC=22.5V
UNIT-V
9 a) Draw the small signal model of FET and explain the significance of each [5M]
element.
b) A CE amplifier is drawn by a voltage source of internal resistance rs = 700 Ω, [9M]
and the load impedance is a resistance RL = 1000Ω. The h-parameters are
hie=1KΩ, hre=2x10-4, hfe=50 and hoe=25µA/V. Compute the current gain, input
resistance, voltage gain and output resistance.
OR
10 a) Derive the expressions for voltage gain, current gain, input and output [10M]
impedance of CC amplifier using exact and approximate analysis.
b) Give the comparison of transistor amplifiers. [4M]

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Code No: R2021041 R20 SET - 3

II B. Tech I Semester Regular/Supplementary Examinations, January-2023

ELECTRONIC DEVICES AND CIRCUITS
(Com to ECE, EIE, ECT)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions, each Question from each unit
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~~
UNIT-I
1 a) Explain energy band diagrams of intrinsic and extrinsic semiconductors with [7M]
neat sketches.
b) Derive an expression for the Fermi level in an intrinsic semiconductor. Express [7M]
electron and hole concentrations in terms of Fermi level.
OR
2 a) Calculate the barrier capacitance of a Germanium p-n junction whose area is [7M]
-4
1mm by 1mm and space charge thickness is 2 x 10 cm. The dielectric constant
of Germanium (relative to free space) is 16.
b) Explain the effect of temperature on characteristics of PN junction diode. [7M]

UNIT-II
3 a) In what respect is an LED different form an ordinary PN junction diode? State [6M]
the applications of LEDs.
b) Discuss the operation of UJT with necessary diagrams. [8M]

OR
4 a) With neat sketch explain the operation of full wave rectifier with capacitor filter [10M]
and derive the expression for ripple factor.
b) In a half-wave rectifier circuit, a voltage of 12 sin ωt is applied. The diode has a [4M]
forward resistance of 10Ω. The load is 1.5KΩ. Determine Im and Vdc.
UNIT-III
5 a) Explain the operation of transistor in CE configuration and draw its input and [10M]
output characteristics.
b) A certain transistor has a current gain of 0.99 in CB configuration. Calculate its [4M]
current gain in the CE configuration and another transistor has β=70, determine
its α.
OR
6 a) Explain how a FET is used as a voltage variable resistor. [5M]
b) Give the comparison between JFET and MOSFET. [4M]
c) An n-channel JFET has IDSS = 10mA and VP = -2V. Determine the drain source [5M]
resistance rDS for (i) VGS = 0V and (ii) VGS = -0.5V.

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Code No: R2021041 R20 SET - 3

UNIT-IV
7 a) Explain the importance of biasing. [4M]
b) Define the three stability factors. [3M]
c) Design a self-bias circuit using silicon transistor to achieve a stability factor of [7M]
10, with the following specifications:VCC=15V, VBE=0.7V, VCEQ=8V, ICQ=4 mA
and β=50.
OR
8 a) Explain why the self-biasing arrangement cannot be used in an enhancement [4M]
type MOSFET.
b) With a neat sketch, explain the operation of collector to base bias. [6M]
c) Explain how thermistor is used for bias compensation. [4M]
UNIT-V
9 Derive the expressions for voltage gain, current gain, input impedance and [14M]
output impedance of CE amplifier using exact and approximate analysis.
OR
10 a) Define the various h-parameters and give their units. [3M]
b) Draw the h-parameter model for common collector configuration. [2M]
c) Deduce the expressions for input impedance, output impedance and voltage gain [9M]
of Common Drain amplifier.

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Code No: R2021041 R20 SET - 4

II B. Tech I Semester Regular/Supplementary Examinations, January-2023

ELECTRONIC DEVICES AND CIRCUITS
(Com to ECE, EIE, ECT)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions, each Question from each unit
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~~
UNIT-I
1 a) What is meant by Fermi level in semiconductor? Where does the Fermi level lie [7M]
in an intrinsic semiconductor? Prove that the Fermi level in an n-type material is
much closer to the conduction band.
b) Explain about Fermi-Dirac function. [7M]

OR
2 a) “The barrier potential developed across an open-circuited PN junction allows the [7M]
flow of minority carriers”. Explain how the current due to this flow of charge
carriers is counterbalanced.
b) Explain about the current components in PN junction diode. [7M]
UNIT-II
3 a) Draw and explain the V-I characteristics of Photodiode. [6M]
b) A 10V zener diode is used to regulate the voltage across the variable load RL. [8M]
VDC has the range 13V ≤ VDC≤16V and load current is 10 mA≤ IL ≤85 mA.
Given Izmin as 15mA, calculate: (i) RS and (ii) zener diode power dissipation PZ.
OR
4 a) Sketch the circuit of a half-rectifier and explain its operation. [6M]
b) A sinusoidal voltage whose Vm = 25V is applied to a half-wave rectifier. The [6M]
diode may be considered to be ideal and RL = 1.5 KΩ is connected as load.
Determine the following:
(i) Peak value of current
(ii) RMS value of current
(iii) Ripple factor
c) Define form factor. [2M]
UNIT-III
5 a) Draw and explain the input and output characteristics of BJT in common base [8M]
configuration.
b) Explain about punch through/reach through in BJT. [6M]

OR
6 Explain the construction and operation of n-channel JFET with neat sketches. [14M]
Discuss its drain and transfer characteristics.

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Code No: R2021041 R20 SET - 4

UNIT-IV
7 a) Explain why it is considered better to fix the quiescent operating point in the [4M]
middle of the active region.
b) Give the comparisons among fixed, collector to base and self-bias circuits. [3M]
c) Explain about the transistorized bias compensation against the variation in base- [7M]
emitter voltage VBE.
OR
8 a) What are the limitations in selecting the operating region in a transistor circuit? [3M]
b) Draw the various biasing circuits used for JFET/MOSFET. [6M]
c) An N-channel JFET with VP = 2.0V and IDSS = 1.75mA is used in an amplifier, [5M]
using self-bias circuit. It uses a drain-source supply VDD = 25V. It is desired to
bias the circuit at ID=1mA. Find (i) VGS and (ii) RS.
UNIT-V
9 a) Determine the current gain and input impedance when the transistor is [6M]
connected in CB configuration with a load RL=10KΩ, VCB=10V, IC=1.5mA,
hib=20Ω, hrb=5x10-4, hfb= -0.98, hob=10-7 Ω-1.
b) Deduce the expressions for input impedance, output impedance and voltage gain [8M]
of Common Source amplifier.
OR
10 a) Explain in detail about the small signal analysis of Common Source FET [10M]
amplifier.
b) Discuss the generalized analysis of transistor amplifier model using h-arameters. [4M]

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