BBME 2

Digital Electronics
DIE-221

Lesson 5: Properties of Sequential Logic Circuits

and Systems

E. Chiwaya, Staff Associate in Computer Engineering

LAST LESSON
In the last lesson, we designed:
o combinational logic circuits
o adders, decoders, encoders, magnitude comparators, and
multiplexers.
INTENDED LEARNING OUTCOMES
In this lesson we will introduce sequential logic designing:
By the end of this lesson, the student should be able to:
o distinguish sequential logic from combinational
o explain the construction, operation and types of storage
elements: latches &flip-flops
o discuss flip-flop operating characteristics and apply them in the
design of sequential logic systems
o explain basic flip-flop applications.
REFERENCE MATERIALS
o Saha, A., & Manna, N. (2007). Digital Principles and Logic Design.
Hingham: Infinity Science Press.
o Mbewe, S.A (2021). Digital Electronics lecturer notes. (MUBAS)
o Mano M.M., Ciletti M.D. (2013) Digital Design: With an Introduction
to the Verilog HDL, 5th Edition, Pearson Education, Inc.,
o Floyd, T. L. (2015). Digital Fundamentals. Pearson Education
Limited.
OUTLINE
o Last lesson
o Intended learning outcomes
o Reference materials
o Outline
o Introduction
o Storage elements
o Flip-flop operating characteristics
o Flip-flop applications
INTRODUCTION
Logic Gates
• A logic gate is an electronic circuit that performs basic
logical functions that are fundamental to digital circuits.

• They can be used to combine digital signals based on

basic Boolean functions

• AND, NOT, OR, NAND, NOR, XOR, &XNOR

INTRODUCTION
AND Gate
• The AND gate can have two or more inputs, the output
variable takes the high logic level (1) if and only if the
input variables are all at the high logic level.
INTRODUCTION
OR Gate
• With an OR gate, the output takes the logic level 1 if at least one
of its inputs is at the logic level 1.
INTRODUCTION
NOT Gate
• The NOT function provides the complementary state to a given
variable. The logic level of the output variable is obtained by
taking the complement of the input variable, as shown in the
truth table.
INTRODUCTION
NAND Gate
• It produces a LOW output only when all the inputs are
HIGH
INTRODUCTION
NOR Gate
• It produces a LOW output when any of its inputs is
HIGH, and a HIGH output only when all inputs are LOW

Students are advised to revise XOR&XNOR gates at

their own time
SEQUENTIAL LOGIC
• Storage elements are connected back to form a feedback
path
• The binary information stored at a given time defines the
present state of the storage element
• Both external inputs and the present state determine the
output’s binary value.
• A sequential circuit is specified by a time sequence of
inputs, outputs, and internal states.
SEQUENTIAL LOGIC
• Classification based on timing of their signals:
asynchronous and synchronous
Employs signals that affect the
storage elements at only discrete
instants of time.

• Behavior depends upon the input signals at any instant of

time and the order in which the inputs change
SEQUENTIAL LOGIC
• Synchronization is achieved by a timing device called
a clock generator, which provides a clock signal having
the form of a periodic train of clock pulses.

• The clock pulses are distributed throughout the system

in such a way that storage elements are affected only
with the arrival of each pulse.
LATCHES & FLIP-FLOPS
• A storage element in a digital circuit can maintain a
binary state indefinitely until directed by an input signal
to switch states.
• The storage elements differ in the number of inputs they
possess and in the manner in which the inputs affect the
binary state.

A Latch operates with signal levels flip-flop is controlled by a clock transition

 LATCHES
• A latch is a type of temporary storage
S-R device that has two stable states
(bistable logic device or multi-
Gated S-R
vibrator): set state & reset state
D • Set state: output Q = 1 & Q’ = 0
Gated D • Reset state: output Q = 0 & Q’ = 1
Active HIGH • The outputs, Q &Q’, are normally
Active LOW
complementary
S-R (SET-RESET) LATCH
• It can be an active-HIGH input or active-LOW input
latch.

Active-High input S-R latch

S-R (SET-RESET) LATCH
• It can be an active-HIGH input or active-LOW input
latch.

Active-LOW input S-R latch

ACTIVE-HIGH INPUT S-R LATCH
• It is implemented with two cross-coupled NOR gates
and its resting state is when both inputs are logical 0.
• The application of a momentary 1 to the S input causes
the latch to go to the set state
• The S input must go back to 0 before any other
changes take place, in order to avoid occurrence of an
undefined next state.
ACTIVE-HIGH INPUT S-R LATCH
• Removing the active input from S leaves the circuit in
the same set state i.e. Q output is logical 1 then the
latch is said to have stored a logical 1
• After both inputs return to 0, it is then possible to shift
to the reset state by momentary applying a 1 to the R
input
• The condition that is forbidden is when both inputs are
equal to 1 at the same time
ACTIVE-HIGH INPUT S-R LATCH
ACTIVE-LOW INPUT S-R LATCH
• It is implemented with two cross-coupled NAND gates
and its resting state is when both inputs are logical 1.
• The application of a momentary 0 to the S input causes
the latch to go to the set state
• When the S input goes back to 1, the circuit remains in
the set state
• After both inputs go back to 1, we are allowed to
change the state of the latch by placing a 0 in the R
input.
ACTIVE-LOW INPUT S-R LATCH
THE GATED S-R LATCH
• It is an S-R latch with a control input ‘En’ that
determines when the state of the latch can be
changed.
• The outputs of the NAND gates stay at the logic-1
level as long as the enable signal remains at 0.
• An indeterminate condition occurs when all three
inputs are equal to 1.
THE GATED S-R LATCH
THE GATED D-LATCH
• The D (Data) Latch eliminates the undesirable
condition of the indeterminate state, S and R are never
equal to 1 at the same time.
• The output Q follows D when ENABLE is high.
THE GATED D-LATCH
EXERCISE
Consider the active low input latch, draw the waveform
to be observed on the Q output given the following input
waves. Assume that Q is initially LOW
END OF LESSON
Next Lesson
Flip-flops
FLIP-FLOPS
• They are sensitive to their inputs at the transition of the
clock: unlike latches, flip-flops are edge sensitive
devices.
• Identified using a dynamic input indicator (small
triangle) inside blocks representing them.
• Classified as S-R flip-flop, D flip-flop, J-K flip-flop
and T flip-flop
FLIP-FLOPS

Positive edge
triggered
Flip-flop changes
state at the rising
edge of the clock
pulse
FLIP-FLOPS

Negative edge
triggered
Flip-flop changes
state at the falling
edge of the clock
pulse
THE EDGE-TRIGGERED S-R FLIP-
FLOP
THE EDGE-TRIGGERED S-R FLIP-
FLOP
• The S and R inputs of the S-R flip-flop are called
synchronous inputs because data on these inputs are
transferred to the flip-flop’s output only on the
triggering edge of the clock pulse.
• When S is HIGH and R is low, the Q output goes HIGH
on the triggering edge of the clock pulse and the
device is SET. When S is LOW and R is HIGH, the Q
output goes LOW on the triggering edge of the clock
pulse, the device is RESET.
THE EDGE-TRIGGERED S-R FLIP-FLOP
• When both inputs are LOW the output does not change
from its prior state. It is an invalid condition if both
inputs are HIGH.
• The operation of the negative and positive edge-
triggered devices is the same
TRUTH TABLE FOR EDGE TRIGGERED FLIP-FLOP
EXERCISE
• Determine the 𝑄 𝑎𝑛𝑑 𝑄 ′ output waveforms of the flip-flop shown
for the S, R and clock inputs shown in figure below. Assume
that the positive edge-triggered flip-flop is initially RESET.
SOLUTION
THE EDGE-TRIGGERED D FLIP-FLOP
• A positive edge-triggered D Flip-Flop is formed with
an S-R flip-flop and an inverter.
• The inverter ensures that the inputs are
complementary.
• The D flip-flop is useful when a single data bit (0 or 1)
is to be stored.
• Basically Q follows D on the triggering edge of the
clock
THE EDGE-TRIGGERED D FLIP-FLOP
THE EDGE-TRIGGERED D FLIP-FLOP
• When D is HIGH, the output ‘Q’ goes HIGH at the
triggering edge of the clock pulse and the flip-flop is
SET.
• Likewise, when the D input is LOW, the output ‘Q’
goes LOW at the triggering edge of the clock pulse
and the flip-flop is RESET
THE EDGE-TRIGGERED D FLIP-FLOP
EXERCISE
Determine the 𝑄 𝑎𝑛𝑑 𝑄′ output waveforms of the flip-flop
shown for the given CLK and D inputs assuming the
positive edge-triggered flipflop is initially RESET.
Determine the 𝑸 𝒂𝒏𝒅 𝑸′ for the D input if the flipflop
is a negative-edge-triggered device
SOLUTION
Determine the 𝑄 𝑎𝑛𝑑 𝑄′ output waveforms of the flip-flop
shown for the given CLK and D inputs assuming the
positive edge-triggered flipflop is initially RESET.
Determine the 𝑸 𝒂𝒏𝒅 𝑸′ for the D input if the flipflop
is a positive-edge-triggered device
THE EDGE-TRIGGERED JK FLIP-
FLOP
• The J – K flip flop is versatile and widely used flip flop.
• The function of J – K flip flop is identical to that of the
S-R flip flop in the SET, RESET, and no-change of
state conditions of operation.
• The difference is that J - K flip-flop has no invalid state
as does the S – R flip-flop.
THE EDGE-TRIGGERED JK FLIP-
FLOP
• When both J and K are LOW, the output does not
change from its prior state, but toggles when J and K
are both HIGH
• J and K labels are in honor of Jack Kilby
THE EDGE-TRIGGERED JK FLIP-
FLOP

A simplified logic diagram for a positive edge-triggered JK

flip-flop
THE EDGE-TRIGGERED JK FLIP-FLOP
TRUTH TABLE
EXERCISE
Determine the 𝑄 𝑎𝑛𝑑 𝑄′ output waveforms of the flip-flop
shown below for the given J,K, and CLK inputs assuming
the flipflop is initially RESET.
 END OF LESSON
Next Lesson
Flip-flop Operating Characteristics & Applications