Xilinx Solutions

for Next
Generation
SONET/SDH
Networks
Xilinx, Inc.
 Agenda
• Telecom today and SONET / SDH
• Data over SONET / SDH technologies
• Xilinx solutions for next generation SONET / SDH

2
Telecom Today &
SONET/SDH
• Fiber-optical transport system (L1)
– Synchronous Optical NETwork and
Synchronous Digital Hierarchy
• Scalable performance
– 155Mbps (OC3/STM1) to 40 Gbps
(OC192/STM64) and beyond
SONET/SDH
ADM
• Widely deployed
– In over 95% of telecom optical
infrastructure
– Multiple, global equipment vendors
• Supports an array of traffic, but
ideal for voice and delay sensitive
traffic

3
 Future of SONET/SDH
• Carriers want to keep SONET due to its reliability, standardization,
flexibility, QoS, manageability, scalability
• Carrier investment and SONET proliferation is continuing in the
edge and metro area
• SONET/SDH variants needed for efficient data transport
• Multi-Service Provisioning Platforms (MSPP)
– Combines various functionalities and protocol support into a single chassis
with SONET/SDH, Ethernet, Fibre Channel, IP, etc.
– Built for the Metro Edge Networks to alleviate metro-bottleneck, save rack
space, power, and $$$
• Key opportunity: Data (Ethernet, FC, etc.) over SONET/SDH

4
 Data over SONET / SDH
Issues
• SONET has fixed Synchronous Payload Envelopes (SPE)
– How to efficiently transport mis-matched frames?
• Inefficient, inflexible & expensive scheme
– Mapping into SONET is line rate/ bandwidth mismatched
• Mapping 10 Mbps Ethernet into SONET requires the entire STS-1
(payload size of 48.384 Mbps): 20.7% utilized
• Gig Ethernet requires an entire OC-48 (2.5 Gbps): 41.7% utilized
• Inflexibility due to burst nature of Ethernet (IP traffic) and
Fibre Channel frames

5
Today’s Metro Area Network
New and Legacy Technologies
Data Center
Storage & Servers

Metro Backbone
SONET, ATM, PoS, DWDM

Metro Aggregation
T1, T3, WDM, Ethernet
Metro Access
T1, ATM, FR, Ethernet
Broadband Access
Cable, DSL, Wireless
Source: RPR Alliance

6
 Client SAN Requirements
• Different packet types coexist on the same SAN
– Metro equipment will have a mixture of port types
• For example
– Fiber Channel from storage arrays
– iSCSI/Ethernet from ESAN/LAN
– ESCON for legacy data centers
• In the future:
– Add video, and other native storage formats
– 8B10B encoding is a key requirement
7
 LAN Technology for SAN
• TCP/IP is the predominant data transport protocol
– iSCSI is SCSI commands encapsulated by TCP/IP
– Resilient to latency variation and packet loss
(1-2% packet loss* is typical across Internet)
• FC is the storage data transport protocol
– Delivers in-order, loss-less data
– Credit buffering provides end-to-end flow control
– Sensitive to latency
*www.internetweather.com - independent source of IP network performance

8
 Ethernet over SONET (EoS)
• EoS collectively represents a group of industry (ITU)
specs that have been developed for optimal transport of
Ethernet over SONET/SDH
– Very cost-effective
– Allows bandwidth to be shared among several Ethernet ports
• Using EoS with VC a GE channel can be built (24 STS-
1’s concatenated) while the unused portion of the OC-
48 bandwidth can be deployed for other Ethernet or
TDM services

9
 Modern SONET Technology
• Generic Framing Procedure (GFP) - G.7041
– Provides a standard mapping of Level 1-2 (Link Layer)
protocols into SONET/SDH (or OTN)
• Virtual Concatenation (VCAT) - G.707
– Enables SONET streams to be multiplexed together in
arbitrary configurations (create right-sized ‘pipes’)
• Link Capacity Adjustment Scheme (LCAS) - G.7042
– Enables SONET streams to be dynamically re-provisioned to
meet bandwidth requirements

10
 Generic Framing
Procedure/Protocol (GFP)
• GFP joint standardization: ANSI and ITU-T (G.7041)
• Protocol for mapping packet data into an octet-synchronous transport like SONET
– Protocol-agnostic frame delineation (L2 & higher) & encapsulating mechanism for
transporting packets
– Robust & efficient packet transport
• GFP frame = GFP header + GFP payload

11
 GFP Mapping to SONET/SDH
Storage
IP Data Services
Services Future Lamda
Services Services
GE, ESCON,
10GE ATM PPP (POS) Ethernet RPR
FC, FICON

WIS HDLC Frame GFP Transparent GFP

OTN

Virtual Concatenation
SONET/SDH

DWDM

12
 Frame Frame Mapping
SOF
EOF Client LAN SONET WAN

Site A
Site B
IFG

Adaptation

• Client (Ethernet) frames are stripped of 8B10B

encapsulation and Inter-Frame Gap (IFG)
• Client frames are encapsulated in GFP frames
13
 Frame Transparent Mapping
SOF
EOF Client LAN SONET WAN Rate Adaptation

Site A
Site B
IFG

Adaptation
• Client symbol stream is encapsulated into fixed-
size GFP frames. Rate adaptation is required
• Opacity! Must insert/remove idles. Also latency…

14
 Data Encapsulation
Evolution
Client Data

PPP/HDLC
ATM Cells

GFP

15
 Transport Over SONET

GE
FC OC-192

DVB

VCAT enables right-sized pipes

16
 Efficient use of VC

Source: Tellabs

17
 Dynamic Reprovisioning of
SONET/SDH Bandwidth
• Link-Capacity Adjustment Scheme (LCAS)
– Supplement to VC function for dynamic bandwidth adjustment
– Allows designers to adjust capacity on a real-time basis
– Carrier & equipment manufacturers can adjust the amount of STS-1s
provided in a group dynamically for network conditions
• Link-Access Procedure for SDH (LAPS)
– Defined as a type of HDLC that includes data link service and protocol
spec used in transporting IP packets over SDH
– Provides a point-to-point unacknowledged connectionless service over SDH
– Enables encapsulation of IPv6, IPv4, PPP & other higher-layer protocols

18
Programmable MSPP Line Card

Memory
Interfacing Interfacing

Backplane/
Framer MAC NPU
Physical Switch Fabric
O/E
Layer
Transceiver

Interfacing Interfacing
Interfacing
Control Plane

19
Xilinx Solutions
 Next-Gen
Memory Technology
Embedded Tri-Mode
Ethernet MAC

Next-Gen
Clocking & Clock Mgmt
Next-Gen
Technology
SelectIO
Technology

Next-Gen
Virtex-4 FX Silicon
Floorplan RocketIO™
Next-Gen
Multi-Gigabit Serial
PowerPC™ Processing
Technology
Technology

21
 V-4 Benefits for MSPP
Feature Benefit
2.488G – 9.953G – Allows a single line card to
Multi-rate Support 600M – 3.125G
10.3G
600M – 11.1G
10.709G support multiple traffic speeds
Allows integration of
processing components
FPGA Fabric Yes Yes Yes No
(MAC/Framer), and
customization
Allows a single line card to
Configurable PCS Yes Yes Yes No
support multiple data protocols
x16 and x20 Allows support of SONET /
Yes Yes Yes
support SDH traffic

OC-12 OC-192 Direct interface to other

SONET Jitter
OC-48 devices, reduces
compliance OC-48 G.709 component count

22
 Xilinx IP Solutions for MSPP
•1GE
•10GE

Ethernet/
FC Framer/ Fiber
SFP/GBIC
PHY
PHY
Mapper/
Security Network SONET
Optical CPCS
Link MAC GFP PMD Optics
Module Layer
Layer
Layer/
Processor Processor Framer
MAC

•MGT • 1G Base-x
• GFP-F •OC-48
(622-11.1G) • 10GE
• GFP-T •OC-192
• 1 & 2 Gbps FC
• FICON •VC/LCAS
• ESCON • SPI-3
• SPI-4.2

23
 GFP IP Core: Highlights
• Fully compliant with ITU-T G.7041 GFP recommendation
• Configurable for frame-mapped, transparent,
or Mixed Mode
– Individually optimized for OC-48 or OC-192 applications
• Supports MANY different protocols
– Frame: Ethernet, PPP, RPR
– Transparent: Gigabit Ethernet, Fibre
Channel, FICON, ESCON, DVB ASI
• Supports up to 10 unique channels
– Multi-line / Multi-protocol applications
– MSPP’s, e.g.. 10x 1GE => OC-192
24
 GFP IP Core
• Xilinx standard LocalLink
M AP CORE interfaces
Data
(Local Link)
Data
(Local Link)
– easy system integration
Line
Interface • Map & Unmap cores

Line Interface (to SONET)

System Interface (to client)

System
Control
Interface
Software SW I/F
delivered independently
& Status
Interface (DCR)
– Enables separate ingress
and egress paths/devices
UNM AP CORE
Data Data
• Dynamic reconfiguration
(Local Link) Line
Interface
(Local Link) through host interface
System
Interface
– No line-card power-down
Control
Software SW I/F
& Status Speed Mode Slice
Interface (DCR)
OC-48 Frame-mapped 2000
OC-192 Frame-mapped 4500
OC-192 Frame/Transparent 9600

25
 GFP: Buffer Manager Ref Core
• Frame buffering
– Store and forward on a per-channel
basis
– Round robin between N channels
– Clock adaptation (N client clks to one
system clk)
– Applicable to both GFP-F and GFP-T
• Utilize on-chip or off-chip RAM
• Local Link for easy system
integration

26
 SPI-4.2 IP Core
• 22% smaller FPGA implementation in V-4
– 3900 slices for fully-compliant (OIF-SPI4-02.1) DPA solution
• Up to 1-Gbps/pin data rates
– 311-Mhz DDR minimum for 10-Gbps
– NPU SPI-4.2 interfaces up to 500-Mhz DDR (16-Gbps)
• Complete pinout flexibility
– NOT pinlocked
• Support for multiple cores
– Up to 4(+) SPI-4.2 interfaces in a single Virtex-4 device
• Differential global clock implementation
– Improved system margins for designers
27
 SPI-4.2 IP Core
User SPI-4.2 • Embedded DPA
Interface Interface
SPI-4.2 CORE
– Utilizes dedicated source synchronous
Internal CORE IO
resources in Virtex-4
64
Source Data Source
SPI-4.2
64
SRC
TDat [15:0] • Industry leading payload efficiency
Channel Addr FIFO TCTL
TStatOut
SOURCE I/O
TCLK
– No idle insertions, supports back-to-
Status
Tstat Channel Memory
TStat back small packets

Sink Data
64
Sink 64 • Independent Sink & Source cores
SNK RDat [15:0]
SPI-4.2
Channel Addr FIFO
SINK I/O
RCTL – Enables separate ingress and egress
RStatIn
Rstat Channel
Status RCLK paths/devices
Memory RStat
Core Resources: Dynamic Alignment
Rx Tx
Virtex-4 Slices 2000 1900
Most extensive industry-proven Virtex-4 Block RAM 6 6
Global Clock Buffers 2 3
hardware interoperability Digital Clock Managers (DCM) 1 2

28
 Configurable PCS Reference
Design
• Xilinx CPCS solution can be accessed in application note
XAPP759
• Provides a multi-mode soft PCS
– FC (1G/2G), ESCON/SBCON: Transparent mapping
– GE: Frame and Transparent mapping
• Dynamically controls PCS mode on each port
– MGT attributes are partially reconfigured utilizing PPC
– Clock multiplexing uses local routing
• Scales to multiple ports
– Each port operates independently with unique clocking

29
 Configurable PCS (CPCS)
CPCS
Frame/Transparent
1000BASE-X Mapped Client
PCS Interfaces
MGT
High-speed MGT
I/Os FC PCS Transparent
Mapped Client
ESCON PCS Interfaces

Common Client
Control/Status Interfaces
Module
Reference Clock
Clocks Module
External
PPC405 Processor
Interface

30
 1-GE & 10GE MAC IP
• Only FPGA supplier with UNH proven 1GE & 10GE MAC IP
Cores
– Tested against 802.3 Standards Compliance
– Interoperability tested with major vendors’ network equipment
• Highly parameterizable
– Flexibility to optimize GEMAC & 10GEMAC IP cores based on the application needs
• Features well-suited for Ethernet over SONET/SDH application
– Supports jumbo frame of any size --> Results in efficient payload transport
– VLAN frame support --> Essential for metro Ethernet applications
– Cut through operation minimizes latency --> Ideal to meet SONET/SDH protocol
latency requirements
• Supports broad range of PHY interfaces
1GE 10GE System Benefit
GMII/RGMII 1000 Base-X broad range of PHY choices

1000 BASE-X/SGMII XAUI less power & board space

TBI Low cost

31
 1 GEMAC with PCS/PMA
1 GE MAC + PCS/PMA CORE

GMAC PCS PMA

8
TX Data Tx Elastic PCS T x
Transmit Buffer Engine
TX Ctrl SGMII / TBI /
Engine
Back-End Interface

1000BASE-X

RocketIO
TBI Module
Optional
Pause Req Flow Auto-Neg
Pause Value 16 Control
8 Receive
RX Data PCS Rx
Engine Engine
RX Ctrl
R/GMII
MDIO I/F Management

MAC PCS/PMA Slices

1GE 1000 Base-X 1172
1GE TBI 1295
1GE None 742

32
 10 GEMAC with XAUI Interface
Back-End 10 GE MAC + XAUI CORE
Interface XAUI
XGEMAC PCS/PMA
64
TX Data Transmit
TX Ctrl Engine
8
Pause Req Flow
Pause Value 16 Control
64 Receive
RX Data
Engine
RX Ctrl
8 XGMII
MDIO I/F Management

MAC PCS/PMA Slices

•Optimizable core with right 10 GE 2631
features for EOS applications 10 GE XAUI 3298
UNH Compliance Tested

33
 Embedded Tri-Mode
Ethernet MAC in V-4
• Fully Integrated 10/100/1000 Mbps Statistics Interface

Ethernet Media Access Controller

Processor
– Up to 4 Cores per FX device Block
– UNH Compliance Tested
• Use with or without PPC Client
Interface
Phy
Interface
• Key Benefits
– 2100 more Slices available for user
logic
– Implement Single-chip 1000 Base-X
Client Phy
Ethernet Interface Interface
– Low cost connectivity due to multiple
(MII/GMII/RGMII/SGMII) PHY
interfaces support
Statistics Interface

34
 Fibre Channel Core Highlights
• Auto-negotiable 1Gbps and 2Gbps
operation
• Supports all non-loop port types (N, B, E, F)
32-bit
Negotiable MAC • Optional 32-bit Statistics counters
Tx Data • Optional Host Interface
1 or 2 Gbps

Client Interface
serial Tx • Supports all classes of FC frames
Tx
Credit
RocketIO

Data • Independently configurable TX and RX

Contro speeds
Management
l
Controller

• Supports Buffer to Buffer Credit

Management and Credit Recovery
Link

Negotiable PSM • Programmable Timeout values

1 or 2 Gbps • User-customizable using CORE Generator
serial Rx 32-bit • The only UNH-certified FPGA solution!
Rx Optional
Data Rx Data
Contro Statistics
l Speed Mode Slices
1 or 2 No Host I/F or 1440
Optional Gbps Statistics
Management 1 or 2 With Host I/F 1950
(Host) Interface Gbps and Statistics

35
 Example Linecard Solution

MGT
MAC/
CPCS
VCAT/ SONET/
GFP-T GFP-F LCAS SDH Optics
MGT Framer

AMCC
S19225

Virtex-4 FPGA is complimentary to SONET/SDH

Framer/Mapper ASSP in the application

36
 Example Linecard Solution

MGT
MAC/
CPCS
VCAT/ SONET/
GFP-T GFP-F LCAS SDH Optics
MGT Framer

Vitesse
VSC911
5

Virtex-4 FPGA allows flexible partition which enables

customer to implement a low-cost solution

37
Example Linecard Solution

MGT
MAC/
CPCS
VCAT/ SONET/ Optics
GFP-T GFP-F SDH
MGT LCAS
Framer

Agere
TADM042G5

• Virtex-4 FPGA provides migration path to next

generation linecard solution
• Allows customer to leverage legacy devices - leads
to faster time-to-market
38
Ethernet Aggregation (XAPP695)
SFP
Optics • SONET framer adaptation
SFP
Optics
– 4/8 GE ports to SPI4.2
SONET

SFP
Framer
– Optional GFP-F (2003)
Optics
– SAR + MUX/DMUX
SFP

• Integrated control plane

Optics

– PPC for init/stats/debug

• Reference Design
– Verilog + EDK +
LogiCores
– Hardware demonstration
• Unique demonstration of PPC
control plane
– Init, stats, debug

39
 Solution Case Study

• Target device - 4VFX60

• Sub-modules in the solution
– CPCS, MAC, FIFO, GFP,
SPI4.2, Misc. logic
OC-48
• OC-48 solution
4VFX60
– Four 1g ports
– Uses only 28% of the slices
– Smallest device 4VFX20
• OC-192 solution
– Ten 1g ports or one 10g port OC-192

– Uses 58% of the slices

40
Xilinx Solutions Address Line Card Designs
FPGA, IP (GbE, POS, HDLC, GFP, RPR)

Network SerDes
PHY Framer/ Security Processor,
Traffic,
Integrated Queue, +
PMD Layer Mapper/ Processor Look-up,
Optics MAC Classification
Policy Mng. Switch
Fabric
PCI, PCI-X
PCI Express
SFI-4 CSIX QDR, QDR-II
System SPI-3,
PCI, PCI-X
Adv anced
XSBI SPI-4.2 CAM I/F Sw itching
Interfaces TFI-5 UTOPIA L2,L3 PCI Express RL-DRAM Serial RapidIO
HyperTransport DDR-RAM Ethernet
RapidIO FCRAM Proprietary
Proprietary NoBL/ZBT
Sigma RAM Memory

• Rocket I/O • DLLs and clock trees

– Required signaling technology for data plane, control plane and backplane – Enables support for multiple clock domains at different clock
interfacing
rates
• High-speed I/Os (HSTL, SSTL, GTL, LVDS) - Efficient inter-chip communication
– Critical for high throughput packet processing – Manage PCB board signal skew
• PECL for >200MHz clocks • High-speed multipliers
– Increased bandwidth per I/O enables practical PCB layout – Used to calculate packet transmit schedule
• High-speed external memory interfaces >200MHz SDR • Power PC - efficient implementation of compute intensive algorithms
– Enables offloading of high performance memory intensive operation
• High-speed internal Block RAM – Weighted fair queuing, per flow queuing, security
– Maintains linked list headers/packet descriptions

41
Reference Slides
 GFP Application Example
Support 8 ports
programmable to SPI4.2
GFP-T programmable port Individually
or address, Store and programmable GFP-F
GFP-F forward or cut- Mapper
through FIFO (pass-thru GFP-T)

0
1 s Line Intel
e 2VP-50 OC192 OTN OC192
SPI4.2
r Intel® IXF19301 Module
d (GFP-F: 8xGE MAC Framer/ Mapper w/ GFP-F,
7 e GFP-T: CPCS) VC and LCAS
s

43
 10 GEMAC Core
• Only FPGA supplier with UNH proven 10 GEMAC IP
– tested against 802.3ae Standards Compliance & for interoperability with major vendors
– Eliminates expensive and time consuming interoperability testing for customer
equipment
• Enables efficient payload transport with unlimited size jumbo frame support
• VLAN support to enable Metro Ethernet applications
• Implements cut-through operation critical for latency sensitive applications
• Loss-less flow control
• Highly parameterizable
– Flexibility to optimize 10 GEMAC core based on the application needs
• 10 GEMAC supports both LAN (10.3Gbps) & WAN (OC192 9.953Gbps) Line
applications
• Uses 4 embedded RocketIO Transceivers

44
 Seamless Serial Solutions
(622 Mbps to 11.1 Gbps)
*
XFI
OC-192
STM-64
OTN G.709
0C-48 Telecom

1 G FC 2 G FC
Infiniband 10 GFC Storage
Serial ATA

1 GbE 10 GbE Networking

XAUI Proprietary
Proprietary Backplane
Aurora Aurora X
Data &
Serial Rapid I/O PCI Express Control Plane

622 Mbps 3.125 Gbps 9.95 Gbps 11.1 Gbps

* RocketPhy is SONET Compliant. Virtex-4Supports SONET Payload abov e 2.5Gbps.

45
 Virtex-4 FX Family
4VFX12 4VFX20 4VFX40 4VFX60 4VFX100 4VFX140
Logic Cells 12,312 19,224 41,904 56,880 94,896 142,128
BRAM Blocks 36 68 144 232 376 552
Block RAM Kbits 648 1,224 2,592 4,176 6,768 9,936
DCMs 4 4 8 12 12 20
DSP Slices 32 32 48 128 160 192
System Monitors 0 0 1 1 1 1
Max Select IO 320 320 448 576 768 896
Total IO Banks 9 9 11 13 15 17
Processors 1 1 2 2 2 2
EMACs 2 2 4 4 4 4
RocketIO™ MGTs 0 8 12 16 20 24
Package Size MGT IO
SF363 17 0 240 240
FF668 27 0 448 320
FF672 27 12 352 (8) 320 (12) 352 (12) 352
FF1152 35 20 576 (12) 448 (16) 576 (20) 576
FF1517 40 24 768 (20) 768 (24) 768
FF1760 42.5 24 896 (24) 896

(Y) X Y = MGT Channels and X = IO capacity

46
 Xilinx Solution Space
FC FC
SAN SAN
SD

SD

IP SONET/SDH IP
SAN RING SAN

IP IP
LAN LAN

Mixed Fibre
Channel,
Ethernet Links SONET
SPI-3/4
CPCS GFP-F/T FRAMER
CORE

47
 Sub-systems of Xilinx Solution
Networking IP Networking IP Reference Designs
$ P 10 Gb Ethernet MAC (w/ XAUI option) $ P SPI -4.2 (POS -PHY L4) Configurable PCS reference design
P XAUI $ SPI-4.2 Lite (reduced area,1/4 rate) Ethernet aggregation reference design (XAPP695)
XGMII Ref Des . $ SPI-3 (POS -PHY L3) Intel GFP mapping reference design
$ P 1 Gb Ethernet MAC (w/ PHY option) Quad SPI -3 to SPI -4.2 Bridge Ref Des.
P 1 Gb Ethernet PCS/PMA $ P GFP Silicon
$ P 10/100/1000 Mb Ethernet MAC $ A Framer V2-Pro
$ P C 10/100 Mb Ethernet MA C $ A VCAT/LCAS V2-Pro X
$ XGMII/10GE MAC to SPI4.2 Bridge $ P FiberChannel 1x/2x V4
8B/10B Encoder/Decoder

$ - License Fee, P - Parameterized, C- CoreConnect I/F, A - Alliance Core

48
 Fibre Channel Core
• Single or Dual-speed core running at 1 Gb (1062.5 Mb),
2 Gb (2125 Mb) or 1 Gb / 2 Gb per second (negotiable).
• Common internal core clock frequency maintained at
53.125 MHz independent of communication rate
• Designed to ANSI INCITS X3-230-1994 (R1999), X3-297-
1997 (R2002), X3-303-1998 FC-PH and T11-FC-FS
(v1.9) specs
• Industry’s first UNH tested programmable solution for
interoperability and standards conformance!

49
Krista M. Marks:
Update figure to
be correct: Xilinx MPPS Card Solutions
FIFOs come
between CPCS
and GFP core
Multi-Rate Line Card
GbE
1G & 2G
FC

Mux
ESCON SFP GFP-F
RocketIO FIFO &
Optica (GbE)
Transceive Configurabl Channel SONET
l Selectio SPI-3
r e PCS Framer
Modul n GFP-T
(PMA)

Mux
e (FC, ESCON)

1G Ethernet GFP-F SPI-3

10G PPP Sonet
1G FC FC GFP-T SPI- (vc/lcas)
2G FC FICON 4.2
4G FC ESCON
DVB-ASI

50
 Xilinx Solution Resource Utilization
OC -48 GFP -F OC -48/192 GFP -T
Modules solution solution
Slices Slices
10GE w/XAUI 4,430
Multi -protocol interface (xN)
10/100/1000M embedded MAC 0 (embedded)
CPCS 4,368 10,920
GFP -F/T 2,000 5,000
Aggregation 1250 1250
CPI 1750 1750
FIFO 3000 5800
SPI4.2 3900 3900
Total 16,268 33050

Potential V -4 target device

4VFX40: Slices (41,904); EMACs (4); RocketIO MGTs(12); Processors(2); IOs (upto 448)

Potential V2 -Pro target device:

XC2VP50 or XC2VP70

Notes: (1) N is the number of CPCS ports implemented in the system. N = 1,2,…, 8
(2) Resource utilization depends on settings of CPCS configuration parameters

51
 GFP-F Only Core Topology
System Line
Interface Interface

Buffer GFP Core

Ethernet 1000 Ethernet M anager SPI Core Sonet
Base-X M AC Core Reference Framer
(N x Links) Design Frame M ode
PCS

(N x PCS) (N x M AC Core)
RAM
New IP Core Reference IP Core Solutions
Design
• Xilinx reference design for complete system solution
• Frame buffering
– Store and forward on a per-channel basis
– Round robin between N channels
– Clock adaptation (N client clocks to one system clock)
– Applicable to both GFP-F and GFP-T
• Utilize on-chip or off-chip RAM

52
 Ethernet/FC Interoperability
• Xilinx IP solutions tested
by UNH Interoperability Lab
– 10/100, 1GE, and 10GE MAC
– FC
– Tested against IEEE
compliance standards
– Multiple configurations tested,
including XAUI
• UNH using Xilinx board
for pre-test and pattern
generation
• Only FPGA supplier participating

53
Thank you!