INDIAN INSTITUTE OF SCIENCE, BENGALURU

DEPARTMENT OF ELECTRONIC SYSTEMS

ENGINEERING

ANALOG IC DESIGN PROJECT

DESIGN OF TWO STAGE OP-AMP

USING GM-ID METHODOLOGY

SOUMYA KANTA RANA

M.TECH, ELECTRONIC SYSTEMS ENGG. (2021-23)
Contents

1 Literature Review 2
1.1 Drawbacks of traditional design process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Preparation of gm/Id charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Using gm/Id charts for circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 MOSFET Characterization 4
2.1 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Procedure and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Two Stage Op-amp Design 8

3.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Device size calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Miller Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Design Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Testing of the Op-amp 11

4.1 DC analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.2 Differential sweep results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.3 Common-mode sweep results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1.4 Summary of DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 AC analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Stability analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Transient analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 References 16

i
List of Figures

1.1 Flowchart of gm/Id based design process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Schematic of NMOS characterization simulation setup in Cadence Virtuoso . . . . . . . . . . . 4

2.2 Schematic of PMOS characterization simulation setup in Cadence Virtuoso . . . . . . . . . . . 4
2.3 NMOS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 NMOS characteristics(contd.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 PMOS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 PMOS characteristics(contd.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 gm/Id charts for PMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.8 gm/Id charts for NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Two stage CMOS op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Cadence Virtuoso schematic of two stage op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Testbench for DC analysis of Op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Output of differential input sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Output of common-mode input sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Frequency response of uncompensated op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Frequency response of compensated op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Testbench schematic for stability analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 Testbench schematic for transient analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8 Transient simulation output of uncompensated op-amp . . . . . . . . . . . . . . . . . . . . . . . 15
4.9 Transient simulation output of compensated op-amp . . . . . . . . . . . . . . . . . . . . . . . . 15

1
Chapter 1

Literature Review

1.1 Drawbacks of traditional design process

Traditional methods of analog circuit design are predominantly based on the square law expression
relating the drain current (Id ) of MOSFET with the gate overdrive voltage (Vgs −Vth ). The shortcomings
of this method include neglecting several other second-order effects as enlisted below:

1. Drain induced barrier lowering, reverse drain induced barrier lowering.

2. Dependence on VT H of a MOSFET on its dimensions.
3. Channel length modulation

and many more. As a result, there is significant departure of the simulation results from the hand
calculations at sub-micron process nodes.
The gm /Id method aims to address this issue and arrive at better correspondence of hand calculations
and simulation results. The method involves detailed characterization of the MOSFET and prepare
lookup tables to aid hand-calculation.

1.2 Preparation of gm/Id charts

The gm /Id method is based on the following figures of merit:
gm
1. Transit Frequency(fT ) : 2πCgs . This figure is an indication of the device bandwidth.

2. Intrinsic Gain : gm ro or gm /gds . This figure is an indication of the maximum voltage gain that
can be obtained from the device.
3. Transconductance efficiency : gm /Id . This indicates the transconductance obtained per unit drain
current.
In this method, the MOSFET is characterized to obtain the following plots
1. gm versus Vgs
2. Id versus Vgs

3. gm /Id versus Vgs

4. fT versus Vgs
5. gm /gds versus Vgs

From the above plots, the plots of fT , gm /gds , Id /W versus gm /Id need to be obtained.

2
1.3. USING GM/ID CHARTS FOR CIRCUIT DESIGN CHAPTER 1. LITERATURE REVIEW

Specifications

Hand Calculations gm/Id tables

Circuit

Simulation Model

Results

Figure 1.1: Flowchart of gm/Id based design process

1.3 Using gm/Id charts for circuit design

gm /Id of a MOS transistor is nearly independent of its aspect ratio (fig. 2.8, 2.7) when the gate overdrive
voltage Vov (Vgs − Vth ) > 0. Also, its variation is less significant from one technology to another. The
typical range of gm /Id is 5 to 25. While choosing the gm /Id of each device, the following guidelines may
be followed:
1. A small gm /Id can be chosen for the devices whose transconductance doesn’t contribute to gain
(e.g. active loads) or in cases where small area and high speed is desired.

2. A large gm /Id can be chosen for devices whose transconductance contributes to the gain (e.g. input
stage of an amplifier) or in cases where low flicker noise, less mismatch and large voltage swings
are desired.
After choosing the gm /Id for a device, Id has to be chosen as per the power budget, and L has to be
chosen such that the intrinsic gain gm /gds is enough to meet the gain requirement. Choosing a very
large gm /gds might lead to a low fT resulting in a low bandwidth: this tradeoff has to be taken care of
properly. After choosing Id , the width W can be obtained from the Id/W versus gm /Id chart. Lastly,
The DC operating voltage of the device should be chosen from the gm /Id versus Vov chart so that it
operates at the chosen gm /Id .

3
Chapter 2

MOSFET Characterization

2.1 Simulation Setup

Figure 2.1: Schematic of NMOS characterization simulation setup in Cadence Virtuoso

Figure 2.2: Schematic of PMOS characterization simulation setup in Cadence Virtuoso

2.2 Procedure and Results

For obtaining the gm /Id charts, the first step is to plot Id , gm , gm /Id , fT , gm /gds , vov and Id /W versus
Vgs . The figures 2.1 and 2.2 show the schematic of the simulation setup in Cadence Virtuoso™ for the

4
2.2. PROCEDURE AND RESULTS CHAPTER 2. MOSFET CHARACTERIZATION

NMOS and the PMOS respectively. In this exercise“pmos 2” and “nmos 2V” cells of GPDK090 library
are used. The obtained characteristic are shown in figures 2.3, 2.4, 2.5 and 2.6.

Figure 2.3: NMOS characteristics

Figure 2.4: NMOS characteristics(contd.)

From the obtained data, the gm /Id charts can be generated for the PMOS and the NMOS. It consists
of preparing the following graphs:
1. gm /Id versus Vov .
2. fT versus gm /Id .
3. gm /gds versus gm /Id .
4. Id /W versus gm /Id .
Using MATLAB™the above graphs for PMOS and NMOS are plotted and shown in figures 2.7 and 2.8
respectively.

5
2.2. PROCEDURE AND RESULTS CHAPTER 2. MOSFET CHARACTERIZATION

Figure 2.5: PMOS characteristics

Figure 2.6: PMOS characteristics(contd.)

6
2.2. PROCEDURE AND RESULTS CHAPTER 2. MOSFET CHARACTERIZATION

Figure 2.7: gm/Id charts for PMOS

Figure 2.8: gm/Id charts for NMOS

7
Chapter 3

Two Stage Op-amp Design

3.1 Problem Statement

Figure 3.1: Two stage CMOS op-amp

Design a basic two stage op amp based on the following specifications:

Open loop voltage gain ≥ 60dB

Unity gain frequency ≥ 10M Hz
Phase margin ≥ 75 deg
CMRR ≥ 50dB
Power dissipation ≤ 30µW

considering VDD = 1.8V and load capacitance CL = 100f F .

8
3.2. SCHEMATIC CHAPTER 3. TWO STAGE OP-AMP DESIGN

3.2 Schematic

Figure 3.2: Cadence Virtuoso schematic of two stage op-amp

[NOTE: device sizes denoted here do not represent the actual values used in the design]

3.3 Design Methodology

1. The starting point of the design is to choose gm /Id for each transistor. It is chosen between 10-20
depending upon the purpose served by the device in the circuit.
2. The transistors whose transconductance contribules to the gain (M1 , M2 , M6 ) need to have a higher
gm /Id .

3. The transistors which act as current source loads (whose 1/gds contributes to the gain) need to
have a lower value of gm /Id .
4. The starting point is chosen as follows: a gm /Id of 15 for M1 , M2 , M6 and 10 for the other transis-
tors.
5. The transistor length L can be chosen from the gm /gd s vs gm /Id curve for various channel lengths.
Approximate hand calculations can be helpful for determining the minimum channel length that
gives the required gm /gd s and hence the gain.
6. The power budget can be used to choose the currents through each transistor. The transistor
widths can be obtained from the Id /W vs gm /Id chart.

7. The fT vs gm /Id chart is used to make sure that the chosen L and gm /Id meets the bandwidth
requirement.
8. Once device sizes are fixed, the transistor bias voltages can be obtained from the gm /Id vs Vov
charts.

9
3.4. DEVICE SIZE CALCULATION CHAPTER 3. TWO STAGE OP-AMP DESIGN

3.4 Device size calculation

1. The power budget is 30µW which translates to a bias current budget of 16.7µA. Current mirror
biasing is chosen where the bias transistor is allowed 1µA. The bias currents for the differential
stage tail and the CS stage is chosen as 6µA.
2. Desired open loop gain is 1000. So, the transistor length is chosen such that the intrinsic gain
gm /gd s for both PMOS and NMOS is above 40. L = 540nm is chosen as the starting point.
3. For M1 & M2 , Id /W obtained from the gm /Id charts for gm /Id = 15 is 1.82. So, WM1 = WM2 =
1.6µm is chosen.
4. For M3 & M4 , Id /W obtained from the gm /Id charts for gm /Id = 10 is 3. So, WM3 = WM4 = 1µm
is chosen.
5. For M5 & M7 , Id /W obtained from the gm /Id charts for gm /Id = 10 is 5. So, WM5 = WM7 =
1.2µm is chosen. Accordingly, the bias transistor of the current mirror is chosen as 0.2µm.

3.5 Miller Compensation

If p1 , p2 denote the dominant poles ,z denotes the zero, GBP denotes the gain-bandwidth product and
P M denotes the phase margin of the op-amp, we have
     
◦ −1 GBP −1 GBP −1 GBP
P M = 180 − tan − tan − tan
p1 p2 z
 
Here , tan−1 GBP p1 ≈ 90◦ . Assuming that the zero is cancelled by the zero-cancelling resistor, we need
p2 = 2.75GBP for a phase margin of 70◦ . It is known that
gm6 gm2
p2 = , GBP =
CL CC

For the values of gm6 , CL in this case, p2 = 57 × 107 rad/s ≈ 9GBP . So, the chosen gm6 satisfies stability
condition. For GBP = 10M Hz, miller capacitance CC = 390f F is obtained. The zero-cancellation
resistor is given by Rz = 1/gm6 = 17.5kΩ.

3.6 Design Summary

The device sizes and approximate operating conditions as obtained from the previous section are sum-
marised as follows. It is to be noted that the obtained device bias currents depart significantly from the
design bias current values due to finite 1/gds of the NMOS devices used as current source loads.

Device L(nm) W (µm) gm /Id(V −1 ) Id (µA)

M1 650 1.6 15 1.7
M2 650 1.6 15 1.7
M3 650 1.0 10 1.7
M4 650 1.0 10 1.7
M5 650 1.2 10 3.4
M6 650 2 15 3.8
M7 650 1.2 10 3.8

The final choice of channel length (L = 650nm) differs from the initial choice as L = 540nm doesn’t
satisfy the gain requirement.

10
Chapter 4

Testing of the Op-amp

4.1 DC analysis
4.1.1 Schematic

Figure 4.1: Testbench for DC analysis of Op-amp

4.1.2 Differential sweep results

The figure 4.1 above shows the schematic of the test setup used for dc analysis of the op-amp. The first
step in dc analysis if the differential voltage sweep. The figure 4.2 below shows the results of a differential
input sweep of −2mV to 2mV .
The obtained differential input swing is −0.4mV to 0.2mV , and the differential gain magnitude is
1120.

4.1.3 Common-mode sweep results

The figure 4.3 shows the output voltage waveform for a 0 − 1.8V input common-mode sweep. The
common-mode gain obtained at VCM = VDD /2 is 0.639 and the maximum common-mode gain is 5 at
VCM = 0.65V .

11
4.1. DC ANALYSIS CHAPTER 4. TESTING OF THE OP-AMP

Figure 4.2: Output of differential input sweep

Figure 4.3: Output of common-mode input sweep

12
4.2. AC ANALYSIS CHAPTER 4. TESTING OF THE OP-AMP

4.1.4 Summary of DC parameters

The DC performance parameters of the op-amp as obtained from the DC analysis are enlisted below:

1. DC diferential-mode gain = 1120

2. DC common-mode gain = 0.639
3. Worst case CMRR = 47dB
4. Input offset voltage = −0.12mV

5. Input bias and offset current = 0

6. Positive saturation limit = 1.72V
7. Negative saturation limit = 18mV
8. Power dissipation = 14.3µW

4.2 AC analysis
Using the same test setup as in figure 4.1, the open loop frequency response Vo /(Vi2 − Vi1 ) for the
uncompensated op-amp is plotted for the frequency range 1Hz − 1GHz and is shown in figure 4.4.

Figure 4.4: Frequency response of uncompensated op-amp

It is to be noted that the uncompensated op-amp has a negative gain margin as well as a negative
phase margin. As a result, it will be unstable when used in a negative feedback configuration. The
transient response of the uncompensated op-amp used as an unity-gain buffer with square wave input is
an evidence of the same (fig. 4.8). The frequency response for the miller-compensated op-amp is shown
in figure 4.5 below. It exhibits a bandwidth of 10M Hz, gain margin of 47.2dB and phase margin of
69.9◦ .

13
4.3. STABILITY ANALYSIS CHAPTER 4. TESTING OF THE OP-AMP

Figure 4.5: Frequency response of compensated op-amp

4.3 Stability analysis

Figure 4.6: Testbench schematic for stability analysis

Figure 4.6 shows the schematic of the setup used for stability analysis. A ”.stb” analysis carried out for
1Hz − 1GHz shows that the obtained phase margin is 70.73 deg at 10.7M Hz.

14
4.4. TRANSIENT ANALYSIS CHAPTER 4. TESTING OF THE OP-AMP

4.4 Transient analysis

Figure 4.7: Testbench schematic for transient analysis

The figure 4.7 shows the schematic of the transient simulation setup for both the uncompensated and the
compensated op-amps. An unity-gain buffer is made by shorting the ”-” terminal to the output and a
pulse voltage waveform of amplitude 900mV (VDD /2), dc offset of 450mV , period of 1us, rise and fall time
of 10ns and a 50% pulse width is applied at the input. The output waveforms for the uncompensated
and the compensated op-amps are shown in figures 4.8 and 4.9 respectively. The slew-rate obtained is
35V /µs for the compensated op-amp.

Figure 4.8: Transient simulation output of uncompensated op-amp

Figure 4.9: Transient simulation output of compensated op-amp

15
Chapter 5

References

1. Behzad Razavi, ”Design of Analog CMOS Integrated Circuits”, 2ed.

2. Hafeez K T lectures on gm/Id methodology.
3. Hesham Omran lecture on ”The gm-Id design methodology demystified” and accompanying lecture
slides.

4. Sampatrao L. Pinjare et al., A Gm/Id Based Methodology for Designing Common Source Amplifier

16