FPGA Based Design

Spring-2022
Grading

Name CLO1 CLO2 CLO3 Total

Ahmer
Fahad
Comments:

Lab Report: Group Section: Electronics

Experiment No: 07 Date of Experiment:
April-25-2022
Experiment Title:
Implementation of Digital Watch on LCD

Group No: 08
Students’ Names:
1. Muhammad Ahmer Masood
2. Muhammad Fahad
Teachers:
Batch:
Dr. M. Riaz
BSEE 2019-23
Mr. Shahid Nazir
Lab Engineers:
Semester:
Mr. Syed Abuzar Hussain Shah
6th
Mr. Abdul Sabhan

Department of Electrical Engineering

Lab 07: Implementation of Digital Watch on LCD Page|2

7.1. Abstract
The main purpose of this lab session is the implementation of Digital Watch on LCD using
Behavioral Abstraction. The clock divider module is designed which has a single clock input and
a single clock output. The input clock has frequency 50 MHz which is the default clock frequency
of the FPGA board. It is converted to output clock of 1 Hz frequency. Thus, counter which
increments after every second is designed. This seconds’ counter is now used to design a minutes’
counter which increments after every 60 seconds. Afterwards, an hours’ counter is designed using
this minutes’ counter which increments after every 60 minutes. The seconds’ counter and minutes’
counter are set to zero at 60th count and hours’ counter is set to zero at 24th count. These values are
displayed on the character LCD screen available on the FPGA Board. The Xilinx ISE is used to
generate synthesize model and the bit file is downloaded which is used on the hardware kit to test
the digital watch using the onboard LEDs.

7.2. Introduction
7.2.1. Objectives
The main objectives of this lab session are:
1) Designing of block diagram using LCD driver core and counter instances with connections.
2) Implementation of behavioral abstractions of digital watch with LCD.
3) Generate synthesis model and test the digital watch on LCD.

7.2.2. Background
Behavioural Modelling:
Behavioural models in Verilog contain procedural statements, which control the simulation and
manipulate variables of the data types. These all statements are contained within the procedures.
Each of the procedure has an activity flow associated with it.
Xilinx ISE:
A The Xilinx ISE Design Suite is an essential part of several CMC-supported FPGA-based
Development System environments and is provided at no cost to Designer and Prototyping
Subscribers to enable effective use of these systems, including:
• ISE Design Suite
• Vivado HLS tool for C, C++ and SystemC design and automated implementation on Xilinx
FPGAs
• Vivado Design Suite of tools: With enhanced features for Xilinx 7 Series FPGAs (Virtex-7,
Artix-7 and Kintex-7). Currently, Zynq devices are not supported with Vivado.
• Partial Reconfiguration: Allows designers to change FPGA functionality on the fly.
Lab 07: Implementation of Digital Watch on LCD Page|3

Character LCD Screen:

The Spartan-3E Starter Kit board prominently features a 2-line by 16-character liquid crystal
display (LCD). The FPGA controls the LCD via the 4-bit data interface shown in the figure below.
Although the LCD supports an 8-bit data interface, the Starter Kit board uses a 4-bit data interface
to remain compatible with other Xilinx development boards and to minimize total pin count.

Block Diagram:

Figure 1 Block diagram for Character LCD Interface

CG ROM:
The Character Generator ROM (CG ROM) contains the font bitmap for each of the predefined
characters that the LCD screen can display, shown in Figure 5-4. The character code stored in DD
RAM for each character location subsequently references a position with the CG ROM. For
example, a hexadecimal character code of 0x53 stored in a DD RAM location displays the
character ‘S’. The upper nibble of 0x53 equates to DB [7:4] = “0101” binary and the lower nibble
equates to DB [3:0] = “0011” binary. As shown in figure below, the character ‘S’ appears on the
screen. English/Roman characters are stored in CG ROM at their equivalent ASCII code address.
The character ROM contains the ASCII English character set and Japanese kana characters. The
controller also provides for eight custom character bitmaps, stored in CG RAM. These eight
custom characters are displayed by storing character codes 0x00 through 0x07 in a DD RAM
location.
Lab 07: Implementation of Digital Watch on LCD Page|4

Character Set Table:

Table 1 LCD Character Set

Counter:
A 4-bit asynchronous UP counter with D flip flop is shown in the diagram below. It is capable of
counting numbers from 0 to 15. The clock inputs of all flip flops are cascaded and the D input
(DATA input) of each flip flop is connected to a state output of the flip flop. That means the flip
flops will toggle at each active edge or positive edge of the clock signal. The clock input is
connected to first flip flop. The other flip flops in counter receive the clock signal input from Q’
output of previous flip flop. The output of the first flip flop will change, when the positive edge
on clock signal occurs. In the asynchronous 4- bit up counter, the flip flops are connected in toggle
mode, so when the when the clock input is connected to first flip flop FF0, then its output after one
clock pulse will become 20.
Lab 07: Implementation of Digital Watch on LCD Page|5

Circuit Diagram:

Figure 2 Block diagram of 4-bit ripple counter using D Flip Flop

Clock Divider:
Thus, we can see that a counter is nothing more than a specialised register or pattern generator that
produces a specified output pattern or sequence of binary values (or states) upon the application
of an input pulse signal called the “Clock”. The clock is used for data transfer in these applications.
Typically, counters are logic circuits that can increment or decrement a count by one but when
used as asynchronous divide-by-n counters they are able to divide these input pulses producing a
clock division signal. Counters are formed by connecting flip-flops together and any number of
flip-flops can be connected or “cascaded” together to form a “divide-by-n” binary counter where
“n” is the number of counter stages used and which is called the Modulus. The modulus or simply
“MOD” of a counter is the number of outputs states the counter goes through before returning
itself back to zero i.e., one complete cycle. Then a counter with three flip-flops like the circuit
above will count from 0 to 7 i.e., 2n-1. It has eight different output states representing the decimal
numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will
count from 0 to 15 and is therefore called a Modulo-16 counter and so on.
For frequency division, toggle mode flip-flops are used in a chain as a divide by two counters. One
flip-flop will divide the clock, ƒIN by 2, two flip-flops will divide ƒIN by 4 (and so on). One benefit
of using toggle flip-flops for frequency division is that the output at any point has an exact 50%
duty cycle. The final output clock signal will have a frequency value equal to the input clock
frequency divided by the MOD number of the counter. Such circuits are known as “divide-by-n”
counters. Counters can be formed by connecting individual flip-flops together and are classified
according to the way they are clocked.

Circuit Diagram:
Lab 07: Implementation of Digital Watch on LCD Page|6

Figure 3 Block diagram and waveform of Clock Divider

7.3. Equipment
• Computer / laptop
• ModelSim / ISE IDE software

7.4. Procedure
1. Create a new project in ISE and do the following settings:
• Select the device family: SPARTAN 3
• Select the device: xc3s200
• Select the package: ft256
• Select the speed grade: -4
• Check for HDL module
• Check for VHDL Language
2. Create a new source file: (VHDL Module) and add the digital clock module code in it.
Lab 07: Implementation of Digital Watch on LCD Page|7

3. We find the project tree on the left side, which gives an overview of the embedded source
files. We can easily find the available compile / implement / place and route processes below
it.
4. Click on “Generate Programming File” to start the compile / place and route process.
5. This project can be compiled without an error, but to implement this code now to a specific
hardware we need to define the IO pins. So, an IO Pins are defined by “User Constraints File”.
Write the inputs, outputs, and its pin location in proper format of .ucf file. (Use datasheet of
Xilinx board for pin location).
6. Double click on Synthesize – XST. After successful completion of Synthesis, double click on
Implement Design. Implement design consists of three parts- (✓) Translate (✓) Map (✓) Place
and Route.
7. After successful completion of implement design, double click on programming file
Generation. Programming File Generation produces a bitstream for Xilinx device
configuration.
8. Double click on Configure Target Device and a new ISE iMPACT window open.
9. Connect the Xilinx board to your PC/Laptop using USB cable.
10. Double click on Boundary scan. Check auto cable connection Output > Cable Auto Connect.
11. Click on File > Initialize Chain. After that, “Do you want to continue and assign configuration
files(s)?” message appears on screen.
12. Click on Yes and select the generated bit-stream file.
13. If programming gets successful, then “Program Succeeded” message appears on screen.

7.5. Results
7.5.1. Results for Digital Watch on LCD

Figure 4 Waveform showing hours’ increment

Figure 5 Waveform showing soft reset

Lab 07: Implementation of Digital Watch on LCD Page|8

Figure 6 Waveform showing minutes’ increment

Figure 7 Waveform showing seconds’ increment

7.5.2. Realization of Digital Watch on LCD of Spartan 3e kit

Figure 8 Realization of Digital Watch

7.6. Discussion
• For certain cases, behavioral abstraction is even easier and more user friendly than dataflow
abstraction.
Lab 07: Implementation of Digital Watch on LCD Page|9

• The clock divider module inverts the output clock signal from zero to one or vice versa
after every fifty million pulses or counts of the input clock signal. This technique can be
used to make a clock divider module for any frequency of the output clock.
• A minimum of 26-bit number is required to keep count of fifty million pulses.
• The LCD Driver is used in the code for Interfacing LCD Screen. The Code for the Driver
is written in VHDL Language.
• The seconds’ counter resets to zero at 60th count and gives an overflow signal to the
minutes’ counter. The minutes’ counter resets to zero at 60th count and gives an overflow
signal to the hours’ counter. The hours’ counter resets to zero at 24th count.
• A soft reset is added in the code that sets the value to 00:00:00 if the previous value was
23:59:59 and the watch starts again.
• In the stimulus block, the 50 MHz clock is provided by using 10 nanoseconds delay
between positive and negative half cycle of the clock. This block is only used in testbench
and is not used in the synthesize process.

7.7. References
• Palnitkar, Samir. Verilog HDL: A Guide to Digital Design and Synthesis. Second ed.,
Prentice Hall PTR, 2003.
• Ciletti, Michael D. Advanced Digital Design with the Verilog HDL. Second ed., Pearson
Education Inc., 2011.

7.8. Appendices
7.8.1. Code for Counter Module
module counter_enb_ovf (// Inputs
clock,reset_p,enable,
// Outputs
ovf,cnst_val
);

parameter BITS = 2;
parameter MAX = 2;

//Port Declarations
input clock, reset_p, enable;
output ovf;
output [BITS-1:0] cnst_val;

//Intermediate signal declarations

reg [BITS-1:0] cnst_val;
reg ovf;

always @(posedge clock or posedge reset_p)

begin
if(reset_p)
Lab 07: Implementation of Digital Watch on LCD P a g e | 10

begin
cnst_val <= 0;
ovf <= 1'b0;
end
else if(enable)
begin
if(cnst_val == MAX-1)
begin
cnst_val <= 0;
ovf <= 1'b1;
end
else begin
cnst_val <= cnst_val + 1;
ovf <= 1'b0;
end
end
else begin
cnst_val <= cnst_val ;
ovf <= 1'b0;
end
end
endmodule

7.8.2. Code for Digital Watch Core

`timescale 1ns / 1ps
module digital_watch_core(//Inputs
clock,reset_p,enable,//Outputs
sec_d,min_d,hr_d);

//---- Port Declarations

input clock,reset_p,enable;
output [7:0]sec_d;
output [7:0]min_d;
output [7:0]hr_d;

//-- Intermediate signal declarations --

wire ovf_1sec, ovf_10sec;
wire ovf_1min, ovf_10min;
wire ovf_1hr, ovf_l0hr;

wire [3:0] sec1_val, sec10_val;

wire [3:0] min1_val, min10_val;
wire [3:0] hr1_val, hr10_val;

reg soft_reset;
wire reset_sig;

wire [7:0] sec_d, min_d, hr_d;

Lab 07: Implementation of Digital Watch on LCD P a g e | 11

assign reset_sig = reset_p | soft_reset;

assign sec_d = {sec10_val,sec1_val};
assign min_d = {min10_val,min1_val};
assign hr_d = {hr10_val,hr1_val};

always @(posedge clock or posedge reset_p)

begin
if(reset_p)
soft_reset <= 1'b0;
else if (hr10_val == 4'd2 && hr1_val == 4'd4)
soft_reset <= 1'b1;
else
soft_reset <= 1'b0;
end
counter_enb_ovf #(2,2) clockdiv_counter (.clock(clock) , .reset_p(reset_sig),
.enable(enable), .ovf(ovf_1sec), .cnst_val());
counter_enb_ovf #(4,10) sec1_counter (.clock(clock) , .reset_p(reset_sig),
.enable(ovf_1sec), .ovf(ovf_10sec), .cnst_val(sec1_val));
counter_enb_ovf #(4,6) sec10_counter (.clock(clock) , .reset_p(reset_sig),
.enable(ovf_10sec), .ovf(ovf_1min), .cnst_val(sec10_val));
counter_enb_ovf #(4,10) min1_counnter (.clock(clock) , .reset_p(reset_sig),
.enable(ovf_1min), .ovf(ovf_10min), .cnst_val(min1_val));
counter_enb_ovf #(4,6) min10_counter (.clock(clock) , .reset_p(reset_sig),
.enable(ovf_10min), .ovf(ovf_1hr), .cnst_val(min10_val));
counter_enb_ovf #(4,10) hr1_counter (.clock(clock) , .reset_p(reset_sig),
.enable(ovf_1hr), .ovf(ovf_10hr), .cnst_val(hr1_val));
counter_enb_ovf #(4,3) hr10_counter (.clock(clock) , .reset_p(reset_sig),
.enable(ovf_10hr), .ovf(), .cnst_val(hr10_val));

endmodule

7.8.3. Code for Digital Watch Core on LCD

`timescale 1ns/1ps
module digital_watch_lcd_core (// Port List
CLK,
BTN_SOUTH ,
SW,
LED,
LCD_RS ,
LCD_RW ,
LCD_E,
SF_D,
SF_CE0
);

//---- Port Declarations ----

input CLK;
input BTN_SOUTH ;
input [3:0] SW;
Lab 07: Implementation of Digital Watch on LCD P a g e | 12

output [7:0] LED;

output LCD_RS ;
output LCD_RW ;
output LCD_E;
output [11:8] SF_D;
output SF_CE0 ;

//-- Intermediate signals declaration

reg [7:0] LcdChar ;
wire [7:0] LcdIndex ;
wire [7:0] sec_out , min_out , hrs_out ;
assign SF_CE0 = 1'b1;
assign LED = min_out ;

always @(LcdIndex or hrs_out or min_out or sec_out )

begin
case (LcdIndex )
8'h00 : LcdChar = 8'h54; //-- char T (First line 1st char)
8'h01 : LcdChar = 8'h69; //-- char i
8'h02 : LcdChar = 8'h6d; //-- char m
8'h03 : LcdChar = 8'h65; //-- char e
8'h04 : LcdChar = 8'h3d; //-- char =
8'h05 : LcdChar = 8'h20; //-- char ''
8'h06 : LcdChar = {4'b0011 , hrs_out [7:4]}; //-- Hours
8'h07 : LcdChar = {4'b0011 , hrs_out [3:0]};
8'h08 : LcdChar = 8'h3a; //-- char :
8'h09 : LcdChar = {4'b0011 , min_out [7:4]}; //-- Min
8'h0a : LcdChar = {4'b0011 , min_out [3:0]};
8'h0b : LcdChar = 8'h3a; //-- char :
8'h0c : LcdChar = {4'b0011 , sec_out [7:4]}; //-- Sec
8'h0d : LcdChar = {4'b0011 , sec_out [3:0]};
8'h40 : LcdChar = 8'h50; //-- char P (second line 1st char)
8'h41 : LcdChar = 8'h41; //-- char A
8'h42 : LcdChar = 8'h4B; //-- char K
8'h43 : LcdChar = 8'h49; //-- char I
8'h44 : LcdChar = 8'h53; //-- char S
8'h45 : LcdChar = 8'h54; //-- char T
8'h46 : LcdChar = 8'h41; //-- char A
8'h47 : LcdChar = 8'h4E; //-- char N
default : LcdChar = 8'b00000000 ;
endcase
end

//-- Instantiation of the LCD Display driver

lcd_driver i_lcd_driver (// Port Connections
. Clk ( CLK ),
. rs ( LCD_RS ),
. rw ( LCD_RW ),
. enable ( LCD_E ),
. lcd_data ( SF_D ),
. index ( LcdIndex ),
Lab 07: Implementation of Digital Watch on LCD P a g e | 13

. char ( LcdChar )
);

//-- Instantiation of the Digital Watch Core

digital_watch_core i_digital_watch_core (// Port Connections
. clock ( CLK),
. reset_p ( BTN_SOUTH ),
. enable ( SW),
. sec_d ( sec_out ),
. min_d ( min_out ),
. hr_d ( hrs_out )
);

endmodule

7.8.4. Block Diagram for Digital Watch

Lab 07: Implementation of Digital Watch on LCD P a g e | 14

7.8.5. RTL Schematic for Digital Watch