Dr.

Youssef Iraqi 13 March 2023

§2.9 Communicating with People

Character Data
n Byte-encoded character sets
n ASCII: 128 characters
n 95 graphic, 33 control
n Latin-1: 256 characters
n ASCII, +96 more graphic characters
n Unicode: 32-bit character set
n Used in Java, C++ wide characters, …
n Most of the world’s alphabets, plus symbols
n UTF-8, UTF-16: variable-length encodings

Chapter 2 — Instructions: Language of the Computer — 66

66

ASCII representation of characters

Note that upper- and lowercase letters differ by exactly 32; this observation can lead to shortcuts in checking or changing
upper- and lowercase. Values not shown include formatting characters. For example, 8 represents a backspace, 9
represents a tab character, and 13 represents a carriage return. Another useful value is 0 for null, the value the
programming language C uses to mark the end of a string.

Chapter 2 — Instructions: Language of the Computer — 67

67

Chapter 2 — Instructions: Language of the Computer 1

Dr. Youssef Iraqi 13 March 2023

Byte/Halfword/Word Operations
n RISC-V byte/halfword/word load/store
n Load byte/halfword/word: Sign extend to 32 bits in rd
n lb rd, offset(rs1)
n lh rd, offset(rs1)
n lw rd, offset(rs1)
n Load byte/halfword/word unsigned: Zero extend to 32 bits in rd
n lbu rd, offset(rs1)
n lhu rd, offset(rs1)
n lwu rd, offset(rs1)
n Store byte/halfword/word: Store rightmost 8/16/32 bits
n sb rs2, offset(rs1)
n sh rs2, offset(rs1)
n sw rs2, offset(rs1)

Chapter 2 — Instructions: Language of the Computer — 68

68

§2.10 RISC-V Addressing for Wide Immediates and Addresses

32-bit Constants
n Most constants are small
n 12-bit immediate is sufficient
n For the occasional 32-bit constant
lui rd, constant
n Copies 20-bit constant to bits [31:12] of rd
n Clears bits [11:0] of rd to 0
lui x19, 976 // 0x003D0
0000 0000 0011 1101 0000 0000 0000 0000

addi x19,x19,1280 // 0x500

0000 0000 0011 1101 0000 0101 0000 0000

Chapter 2 — Instructions: Language of the Computer — 69

69

Chapter 2 — Instructions: Language of the Computer 2

Dr. Youssef Iraqi 13 March 2023

Branch Addressing
n Branch instructions specify
n Opcode, two registers, target address
n Most branch targets are near branch
n Forward or backward
n SB format:
imm imm
[10:5] rs2 rs1 funct3 [4:1] opcode

imm[12] imm[11]

n PC-relative addressing
n Target address = PC + immediate × 2

Chapter 2 — Instructions: Language of the Computer — 70

70

Jump Addressing
n Jump and link (jal) target uses 20-bit
immediate for larger range
n UJ format:
imm[10:1] imm[19:12] rd opcode
5 bits 7 bits
imm[20] imm[11]

n For long jumps, eg, to 32-bit absolute

address
n lui: load address[31:12] to temp register
n jalr: add address[11:0] and jump to target

Chapter 2 — Instructions: Language of the Computer — 71

71

Chapter 2 — Instructions: Language of the Computer 3

Dr. Youssef Iraqi 13 March 2023

Branching Far Away

Most conditional branches are to a nearby
location, but occasionally they branch far
away, farther than can be represented in the
12-bit address in the conditional branch
instruction.
Solution: inserts an unconditional branch to
the branch target, and inverts the condition
so that the conditional branch decides
whether to skip the unconditional branch.

Chapter 2 — Instructions: Language of the Computer — 72

72

Branching Far Away

Example:

Chapter 2 — Instructions: Language of the Computer — 73

73

Chapter 2 — Instructions: Language of the Computer 4

Dr. Youssef Iraqi 13 March 2023

RISC-V Addressing Summary

Chapter 2 — Instructions: Language of the Computer — 74

74

RISC-V Encoding Summary

Chapter 2 — Instructions: Language of the Computer — 75

75

Chapter 2 — Instructions: Language of the Computer 5

Dr. Youssef Iraqi 13 March 2023

Branch Offset in Machine Language

The while loop in slide 49 was compiled into this
RISC-V assembler code:
Loop: slli x10, x22, 2
add x10, x10, x25
lw x9, 0(x10)
bne x9, x24, Exit
addi x22, x22, 1
beq x0, x0, Loop
Exit: …
If we assume we place the loop starting at location
80000 in memory, what is the RISC-V machine
code for this loop?
Chapter 2 — Instructions: Language of the Computer — 76

76

Branch Offset in Machine Language

Chapter 2 — Instructions: Language of the Computer — 77

77

Chapter 2 — Instructions: Language of the Computer 6

Dr. Youssef Iraqi 13 March 2023

§2.11 Parallelism and Instructions: Synchronization

Synchronization
n Two processors sharing an area of memory
n P1 writes, then P2 reads
n Data race if P1 and P2 don’t synchronize
n Result depends of order of accesses
n Hardware support required
n Atomic read/write memory operation
n No other access to the location allowed between the
read and write
n Could be a single instruction
n E.g., atomic swap of register ↔ memory
n Or an atomic pair of instructions

Chapter 2 — Instructions: Language of the Computer — 78

78

Synchronization in RISC-V
n Load reserved: lr.w rd,(rs1)
n Load from address in rs1 to rd
n Place reservation on memory address
n Store conditional: sc.w rd,(rs1),rs2
n Store from rs2 to address in rs1
n Succeeds if location not changed since the lr.w
n Returns 0 in rd
n Fails if location is changed
n Returns non-zero value in rd

Chapter 2 — Instructions: Language of the Computer — 79

79

Chapter 2 — Instructions: Language of the Computer 7

Dr. Youssef Iraqi 13 March 2023

Synchronization in RISC-V
n Example 1: atomic swap (to test/set lock variable)
again: lr.w x10,(x20)
sc.w x11,(x20),x23 // X11 = status
bne x11,x0,again // branch if store failed
addi x23,x10,0 // X23 = loaded value

n Example 2: lock
addi x12,x0,1 // copy locked value
again: lr.w x10,(x20) // read lock
bne x10,x0,again // check if it is 0 yet
sc.w x11,(x20),x12 // attempt to store
bne x11,x0,again // branch if fails
n Unlock:
sw x0,0(x20) // free lock

Chapter 2 — Instructions: Language of the Computer — 80

80

Chapter 2 — Instructions: Language of the Computer 8