CS61C

Great Ideas
UC Berkeley
in UC Berkeley
Teaching Computer Architecture Teaching
Professor (a.k.a. Machine Structures) Professor
Dan Garcia Lisa Yan

RISC-V Instruction Formats, Part II

Garcia, Yan

cs61c.org
12-RISC-V Instruction Formats, Part II (1)
 Disassembling the S-Format (Last
lecture’s
Slide 33)
 What is the corresponding assembly
instruction? Store opcode
31 25 24 20 19 15 14 12 11 7 6 0
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
0000001 01110 00010 010 00100 0100011

S-Format Lookup table: funct3 opcode

imm[11:5] rs2 rs1 000 imm[4:0] 0100011 sb
imm[11:5] rs2 rs1 001 imm[4:0] 0100011 sh
imm[11:5] rs2 rs1 010 imm[4:0] 0100011 sw
Garcia, Yan

12-RISC-V Instruction Formats, Part II (2)

 Disassembling the S-Format (Last
lecture’s
Slide 33)
 What is the corresponding assembly
instruction? “store word” Store opcode
31 25 24 20 19 15 14 12 11 7 6 0
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
0000001 01110 00010 010 00100 0100011

rs2 rs1
(“source”) (“base”)
imm (“offset”)
14 2
The two “read”
0000001 00100 reg. fields for S-
+36ten sw rs2, imm(rs1) type and R-type
are at the same bit
sw x14, 36(x2) positions. Garcia, Yan

12-RISC-V Instruction Formats, Part II (3)

 Garcia, Yan

12-RISC-V Instruction Formats, Part II (4)

 • Updating the Program
Updating Counter (PC)
the • B-Format Layout
Program • J-Format Layout
Counter • U-Format: Long
Immediates
(PC) • jalr: I-Format
Garcia, Yan

12-RISC-V Instruction Formats, Part II (5)

 The Program Counter (PC)
Processor Memory
Enable? Input
The Program
Control Read/ Write
Counter (PC) is
a special
Address
Datapath internal
ProgramCounter (PC) Bytes
register inside
Registers processor
Write Data holding byte
address of the
Read Data
Arithmetic-Logic
Unit (ALU)
Output instruction being
executed.
It is separate
Processor-Memory Interface I/O-Memory Interfaces from the 32- Garcia, Yan
12-RISC-V Instruction Formats, Part II (6) registers
 PC = PC + 4 for most instructions
Addres Machine Registers before execution
s Code Original Assembly Code PC
0x0c 00A98863 Loop: beq x19,x10,End 0000 0010
0x10 00A90933 add x18,x18,x10
RegFile
0x14 FFF98993 addi x19,x19,-1 x10 0000 0001
0x18 FF5FF06F j Loop x18 0000 0000
0x1c 00A98863 End: … x19 0000 0002

Program
Address Space +4
Addres Machine PC
s Code Original Assembly Code
0000 0014
0x0c 00A98863 Loop: beq x19,x10,End
0x10 00A90933 add x18,x18,x10 RegFile
0x14 FFF98993 addi x19,x19,-1 x10 0000 0001
x18 0000 0001
0x18 FF5FF06F j Loop x19 0000 0002
0x1c 00A98863 End: … Garcia, Yan

12-RISC-V Instruction Formats, Part II (7)

 Branches Update PC to ”Jump”
Unconditional Branches Conditional Branch (if branch taken)
0x0c Loop: beq x19,x10,End 0x0c Loop: beq x19,x10,End
0x10 add x18 x18,x10 PC 0x10 add x18,x18,x10 PC
0x14 addi x19,x19,-1 0000 0018 0x14 addi x19,x19,-1 0000 000c
0x18 j Loop 0x18 j Loop
RegFile RegFile
0x1c End: … x10 0000 0001 0x1c End: … x10 0000 0001
x18 0000 0001 x18 0000 0001
x19 0000 0001 x19 0000 0001

0x0c Loop: beq x19,x10,End

-12 0x0c Loop: beq x19,x10,End +16
0x10 add x18,x18,x10 PC 0x10 add x18,x18,x10 PC
0x14 addi x19,x19,-1 0000 000c 0x14 addi x19,x19,-1 0000 001c
0x18 j Loop 0x18 j Loop
RegFile RegFile
0x1c End: … x10 0000 0001 0x1c End: … x10 0000 0001
x18 0000 0001 x18 0000 0001
x19 0000 0001
If branch not x19 0000 0001
taken, then PC = Garcia, Yan

PC + 4
12-RISC-V Instruction Formats, Part II (8)
 PC-Relative Addressing
 PC-Relative Addressing: Supply a signed offset to update
PC.
▫ PC = PC + byte_offset
0x0c Loop: beq x19,x10,End 0x400 Loop: beq x19,x10,End
▫ “Position-Independent Code”: If all of
Take branch: code moves, relative offsets
0x10 add x18, x18,x10 0x404 add x18, x18,x10
don’t
0x14 change!
addi x19, x19,-1 PC = PC + 16 0x408 addi x19, x19,-1
0x18 j Loop Don’t take branch: 0x40c j Loop
0x1c End: … PC = PC + 4 0x410 End: …

▫ Branches generally change the PC by a small amount, therefore

in RISC-V instructions we encode relative offsets as signed
immediates.
 Contrast with: Absolute Addressing Garcia, Yan

▫ Supply new address to overwrite

12-RISC-V Instruction PC. PC Part
Formats, = new_address
II (9)
 • Updating the Program
Counter (PC)
• B-Format Layout
B-Format • J-Format Layout
Layout • U-Format: Long
Immediates
• jalr: I-Format
Garcia, Yan

12-RISC-V Instruction Formats, Part II (10)

 RISC-V Conditional Branches
 Example: beq rs1,rs2,Label
 Conditional branches need:
▫ Two read registers, no destination register (like S-Format)
▫ Some way to encode label (i.e., where to jump to)
 RISC-V uses PC-relative addressing to encode labels.
▫ If we don’t branch: PC = PC + 4 bytes
▫ If we do branch: PC = PC + (relative byte offset to Label)
 B-Format Fields:
▫ 7b (opcode) + 3b (funct3) + 5b (rs1) + 5b (rs2) = 20b
▫ 12b immediate field to represent PC’s relative offset.
▪ Signed two’s complement means we can represent ± 211 “units” from the
PC.
Garcia, Yan

12-RISC-V Instruction Formats, Part II (11)

 Scaling the Offset to Maximize Branch Range
The 12-bit immediate field for conditional branches is:
A. In units of 1 byte.
▫ One branch reaches ± 211 bytes from PC  ± 29 x 32-bit
instructions.
▪ Never branch into middle of instruction.

B. In units of 2 bytes (16-bit “half-words”).

pollev.com/yanl
▫ One branch reaches ± 2 x 32-b instructions from PC.
10

▪ Multiply the offset by 2 before adding to the PC.

C. In units of 4 bytes (32-bit words).

▫ One branch reaches ± 211 x 32-b instructions from PC.
▪ Multiply the offset by 4 before adding to the PC. Garcia, Yan

12-RISC-V Instruction Formats, Part II (12)

 Garcia, Yan

12-RISC-V Instruction Formats, Part II (13)

 Scaling the Offset to Maximize Branch Range
The 12-bit immediate field for conditional branches is:
❌A. In units of 1 byte.
▫ One branch reaches ± 211 bytes from PC  ± 29 x 32-bit
instructions.
▪ Never branch into middle of instruction.
▫ Wasteful! Lower 2 bits would always be wasted (always 00).
✅
B. In units of 2 bytes (16-bit “half-words”).
Branch immediate
▫ One branch reaches ± 210 x 32-b instructions from rangePC.
▪ Multiply the offset by 2 before adding to the PC. [-2048, +2047]
❌ represents PC
C. In units of 4 bytes (32-bit words).
relative offsets [-
▫ One branch reaches ± 2 x 32-b instructions from
11
4096,PC.
+4094] in 2-
▪ Multiply the offset by 4 before adding to the PC. byte increments. Garcia, Yan
12-RISC-V Instruction Formats, Part II (14)
 RISC-V Feature: 16-bit
instructions
 RISC-V Base ISA for RV32, RV64, RV128 all
have 32-bit wide instructions, but it supports
extensions:
▫ 16b compressed instructions
▫ Variable-length instructions that are multiples of 16b in
length
 RISC-V therefore scales the branch offset by 2
bytes, even when there are no 16b
instructions!
 Implications for this class (which uses RISC-V
processors that only support 32-bit Garcia, Yan

12-RISC-V Instruction Formats, Part II (15)

 B-Format Instruction Layout
All conditional
 B-Format (textbook: SB-Type) close to S-Format: branch
instructions have
opname rs1,rs2,Label opcode 1100011.
31 25 24 20 19 15 14 12 11 7 6 0
imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode
7 5 5 3 5 7

Immediate represents relative offset in increments of 2 bytes

(“half-words”) (Lowest bit of
▫ To compute new PC: PC = PC + byte_offset. offset is always
▫ 12 immediate bits imply ±210 32-bit instructions reachable: zero, so no
need to store
▫ 1 bit: 2’s complement (allow +/– offset)
31▫ 1 bit: half-word/16-b
25 11 7 support
in instruction.)
instruction 12 11 10 9 8 7 6 5 4 3 2 1 0
imm[12|10:5] imm[4:1|11]
z y x x x x x x w w w w 0
zxxxxxx wwwwy
byte_offset (“imm“) Garcia, Yan

12-RISC-V Instruction Formats, Part II (16)

 B-Format Example (1/2)
Loop: beq x19,x10,End How do we
add x18,x18,x10
addi x19,x19,-1
encode the
j Loop beq instruction in
End: … # target instr this RISC-V code?
Fill in fields (other than immediate).
BRANCH opcode
“beq”
31 25 24 20 19 15 14 12 11 7 6 0
imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode
01010 10011 000 1100011

rs2 rs1
10 19 Garcia, Yan

12-RISC-V Instruction Formats, Part II (17)

 B-Format Example (2/2)
Loop: beq x19,x10,End How do we
+4 add x18,x18,x10
instruc addi x19,x19,-1
encode the
t-ions j Loop beq instruction in
End: … # target instr this RISC-V code?
nstruct branch offset (in bytes), then encode immedia

31 25 24 20 19 15 14 12 11 7 6 0
imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode

0000000 01010 10011 000 10000 1100011

12 11 10 9 8 7 6 5 4 3 2 1 0
▫ +4 32-bit instructions = +16 byte
0 0 0 0 0 0 0 0 1 0 0 0 0
offset
13-bit signed byte_offset (“imm“) Garcia, Yan

12-RISC-V Instruction Formats, Part II (18)

 Why Swirl Immediate Bits Around? HW Design!
 Recall: RISC-V register field positions consistent
across instr. formats.
 RISC-V
31
also tries
25 24
to keep
20 19
bit positions
15 14 12 11
of immediates
7 6 0
I-type imm[11:5]
imm[11:5] imm[4:0] rs1
imm[4:0] funct3
rs1 rd funct3opcode rd opcode
consistent:
yxxxxxx wwwwv
S-type imm[11:5] rs2 rs1 funct3 imm[4:0] opcode

yxxxxxx wwwwv
B-type imm[12|10:5]
imm[12|10:5] rs2
rs2 rs1
rs1 funct3
funct3 imm[4:1|11]
imm[4:1|11] opcode
opcode
zxxxxxx wwwwy
▫ Instruction Bit 31 is always the Between S and B, only two bits change
sign bit (highest bit to sign extend meaning:
in immediate) Instruction Bit 7  S: Imm Bit 0;
▫ B-type has a 13-bit immediate RISC-V immediateB:bit encoding
Imm Bit 11
encoding b/c of implicit zero in is optimized
Instruction to
Bitreduce
31 S: Imm Bit
Imm bit 0. 11; B: Imm
hardware cost.Bit 12 Garcia, Yan

12-RISC-V Instruction Formats, Part II (19)

 All six RV32 B-Format Instructions
funct3 opcode
imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 beq
imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 bne
imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 blt
imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 bge
imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 bltu
imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 bgeu

Garcia, Yan

12-RISC-V Instruction Formats, Part II (20)

 Conditionally Branching Even
Further
 Conditional Branches are typically used for
if-else statements, for/while loops.
▫ Usually pretty small (<50 lines of C code)
 B-Format has limited range:
▫ ± 210 32-bit instructions from current instruction
 What if destination is further away?
▫ Enter the unconditional jump!

beq x10, x0, far if not bne x10, x0, next

# next instr functionally equal
equivalent
j far
next: # next instr
if
if Garcia, Yan
equal
12-RISC-V Instruction Formats, Part II (21) equal
 • Updating the Program
Counter (PC)
• B-Format Layout
J-Format • J-Format Layout
Layout • U-Format: Long
Immediates
• jalr: I-Format
Garcia, Yan

12-RISC-V Instruction Formats, Part II (22)

 Review
The jal instruction and j pseudoinstruction
 jal does a Jump And Link (i.e., “link and jump”):
jal rd, Label
▫ Jump to Label
▫ Write address of the following instruction to rd.
 Two use cases:
1.Call a function (and simultaneously jal ra, FuncLabel
save return address in named register)

2.Unconditional branch j Label

▪ j pseudoinstruction: jump and discard return address
jal x0, Label
Garcia, Yan

12-RISC-V Instruction Formats, Part II (23)

 The jal instruction and j pseudoinstruction
 jal does a Jump And Link (i.e., “link and jump”):
jal rd, Label
▫ Jump to Label (i.e., add relative offset to PC)
PC = PC + offset
▫ Write address of the following instruction tordrd.
= PC + 4
 Two use cases:
1.Call a function (and simultaneously jal ra, FuncLabel
save return address in named register)

2.Unconditional branch j Label

▪ j pseudoinstruction: jump and discard return address
▪ Often used to conditionally branch further than B-Types
jal x0, Label
Garcia, Yan

12-RISC-V Instruction Formats, Part II (24)

 J-Format Instruction Layout
 J-Format (textbook: UJ-Type) used only for jal:
jal rd, Label opcode 1101111

31 25 24 20 19 15 14 12 11 7 6 0
imm[20|10:5] imm[4:1,11] imm[19:12] rd opcode
7 5 8 5 7

“Destination”
Register
Immediate represents relative offset in increments of 2 gets “return
bytes. address.”
▫ To compute new PC: PC = PC + byte_offset. rd = PC + 4
▫ 20 immediate bits imply ±218 32-bit instructions
reachable:
▫ 1 bit: 2’s complement (allow +/– offset), 1 bit: half-word/16-b
What about jumping
instruction support further ? Garcia, Yan

▫ Immediate bit encoding optimized

12-RISC-V Instructionto reduce
Formats, Part HW cost
Next:
II (25) How to load 32-bit
 • Updating the Program
U-Format: Counter (PC)
• B-Format Layout
Long • J-Format Layout
Immediate • U-Format: Long
s Immediates
• jalr: I-Format
Garcia, Yan

12-RISC-V Instruction Formats, Part II (26)

 U-Format Instruction Layout
U-Format
 “Upper Immediate” instructions: opcodes:
lui 0110111
opname rd,immed auipc
0010111
31 25 24 20 19 15 14 12 11 7 6 0
imm[31:12] rd opcode
7 5 8 5 7

“Destination”
Register
Immediate represents upper 20 bits of a 32-bit
Saves result of
immediate
operation.
operand imm 31= immed << 12.
12 11 0
imm[31:12] 0x00 00 00
20 12
Long Immediate (“imm“)
Garcia, Yan

12-RISC-V Instruction Formats, Part II (27)

 lui and addi creates Long
Immediates
lui rd,immed
 The lui instruction, Load Upper Immediate:
▫ Write a 20-bit immediate value into
the upper 20-bits of register rd. rd = immed << 12
▫ Clear the lower 12 bits.

 lui together with an addi (to set lower 12

The li
bits) can create any 32-bit valuepseudoinstruction
in a register: (Load
lui x10, 0x87654 # x10 = 0x87654000 Immediate) resolves to
addi x10, x10, 0x321 # x10 = 0x87654321 lui + addi as needed,
e.g., li
x10,0x87654321. Garcia, Yan

12-RISC-V Instruction Formats, Part II (28)

 lui Edge Case: addi Extends Sign
 How should we set the immediate 0xB0BACAFE?
▫ Unfortunately: 0xB0BAC000
⚠️ lui x10, 0xB0BAC # x10 = 0xB0BAC000 + 0xFFFFFAFE
addi x10, x10, 0xAFE # x10 = 0xB0BABAFE
▪ Recall: addi sign-extends the 12-bit immediate.0xB0BAC 0x000
+ 0xFFFFF -1 + 0xAFE
▪ If “sign bit” set, subtracts 1 from the upper 20-bits!
0xB0BAB 0xAFE
concat
0xB0BABAFE

Garcia, Yan

12-RISC-V Instruction Formats, Part II (29)

 lui Edge Case: addi Extends Sign
 How should we set the immediate 0xB0BACAFE?
▫ Unfortunately: 0xB0BAC000
⚠️ lui x10, 0xB0BAC # x10 = 0xB0BAC000 + 0xFFFFFAFE
addi x10, x10, 0xAFE # x10 = 0xB0BABAFE
▪ Recall: addi sign-extends the 12-bit immediate.0xB0BAC 0x000
+ 0xFFFFF -1 + 0xAFE
▪ If “sign bit” set, subtracts 1 from the upper 20-bits!
0xB0BAB 0xAFE
concat
0xB0BABAFE

✅ Solution: If 12-bit immediate is negative,
Use
add 1 to the upper 20-bit load. pseudoinstructions!
li automatically
lui x10, 0xB0BAD # x10 = 0xB0BAD000
handles this edge
addi x10, x10, 0xAFE # x10 = 0xB0BACAFE
case. Garcia, Yan

12-RISC-V Instruction Formats, Part II (30)

 auipc loads the PC into the
Register File
auipc rd,immed
 The auipc instruction
rd = PC + (immed << 12)
Adds an Upper Immediate to the PC.
 Example:
auipc x5, 0xABCDE # x5 = PC + 0xABCDE
 In Practice:
Label: auipc x5, 0 # puts address of Label in x5
▫ Loads the PC into a register auipc is most often used
accessible by other instructions. together with jalr to do PC-
relative addressing with super
large offsets.
Garcia, Yan

12-RISC-V Instruction Formats, Part II (31)

 • Updating the Program
Counter (PC)
• B-Format Layout
jalr: • J-Format Layout
I-Format • U-Format: Long
Immediates
• jalr: I-Format
Garcia, Yan

12-RISC-V Instruction Formats, Part II (32)

 Review
The jalr instruction and jr pseudoinstruction
 jalr does a Jump And Link Register:
jalr rd,rs1,imm
▫ Jump to rs1 + imm.
PC = rs1 + imm
▫ Write address of the following instruction tordrd.
= PC + 4
 Use cases (so far):
1.Return to caller jr ra jalr x0, ra, 0

Garcia, Yan

12-RISC-V Instruction Formats, Part II (33)

 I-Format Instruction Layout: jalr
 jalr uses I-Format:
jalr rd,rs1,imm opcode 1100111

31 20 19 15 14 12 11 7 6 0
imm[11:0] rs1 funct3 rd opcode
12 that load 5 3 5 7

Immediate Source Register “Destination”

Register gets
imm and rs1 are added together to update PC. “return address.”
PC = rs1 + imm rd = PC + 4
⚠ Note I-Type!
Unlike B-type, J-type, jalr will not multiply imm by 2.
▫ Immediate offset therefore must be written in units of bytes.
Garcia, Yan

12-RISC-V Instruction Formats, Part II (34)

 The jalr instruction and jr pseudoinstruction
 jalr does a Jump And Link Register:
jalr rd,rs1,imm
▫ Jump to rs1 + imm.
PC = rs1 + imm
▫ Write address of the following instruction tordrd.
= PC + 4
 Use cases:
1.Return to caller jr ra jalr x0, ra, 0
Unlike jal (relative to PC), jalr addresses are relative to rs1,
which is modifiable by arithmetic instructions. We can do
bigger jumps!
2.Call a function (and save return address) lui x1 <hi20bits>
at any 32-bit absolute address. jalr ra, x1, <lo12bits>
3.Jump PC-relative with a 32-bit offset. auipc x1 <hi20bits>
jalr x0, x1, <lo12bits>
Garcia, Yan

12-RISC-V Instruction Formats, Part II (35)

 “And in Conclusion…”
 We’ve covered (almost) the entire RV32 ISA!
 Practice assembling and disassembling!

https://riscv.org/technical/specifications/ Garcia, Yan

12-RISC-V Instruction Formats, Part II (36)