SOI DESIGN

ANALOG, MEMORY
AND
DIGITAL TECHNIQUES
 SOI DESIGN
ANALOG, MEMORY
AND
DIGITAL TECHNIQUES

by

Andrew Marshall
&
Sreedhar Natarajan

Texas Instruments Incorporated

KLUWER ACADEMIC PUBLISHERS

NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 0-306-48161-8
Print ISBN: 0-7923-7640-4

©2003 Kluwer Academic Publishers

New York, Boston, Dordrecht, London, Moscow

Print ©2002 Kluwer Academic Publishers

Dordrecht

All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Visit Kluwer Online at: http://kluweronline.com

and Kluwer's eBookstore at: http://ebooks.kluweronline.com
 SOI Design: Analog, Memory & Digital Techniques

To Judith, Amy and Elise for their enduring patience and encouragement.

-- Andrew Marshall

To my wife Chandra for her patience and support, my Parents, my brother

Sriram and his family, my wife’s family, and friends for their continued
encouragement.

-- Sreedhar Natarajan

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 SOI Design: Analog, Memory & Digital Techniques

Table of Contents

Preface xix
Acknowledgements xxi

Chapter 1: Overview 1

1.1 Silicon on Insulator – a brief Introduction 1

1.2 Circuits and SOI 2

1.3 Technology and SOI 3

Chapter 2: SOI Materials 5

2.1 Silicon on Heteroepitaxial Substrate 5

2.2 Silicon-Oxide-Silicon SOI substrates 6

2.2.1 Separation by Implantation of Oxygen 6
2.2.2 Wafer-Bonding methods for preparing SOI 8
2.2.3 SOI Materials Summary 11

2.3 Comparison of SOI and Bulk 11

2.3.1 Isolation Techniques 11

2.4 SOI Technology Advantages 16

2.4.1 Capacitance Reduction 16
2.4.2 Reduced Short Channel Effect 16
2.4.3 Lower Device Threshold 16
2.4.4 Soft Error Rate (SER) Effects 17

2.5 Performance 17

2.6 Partially and Fully Depleted-SOI 18

2.7 Technology Scaling 21

2.8 SOI Device Properties 22

2.8.1 Source/Drain-to-Substrate Capacitance 22
2.8.2 Gate Leakage 22

2.9 Body Effects 23

2.9.1 Bipolar Effect 23
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SOI Design: Analog, Memory & Digital Techniques

2.9.2 Kink Effect 24

2.9.3 Capacitive Body Effects 26

2.10 Body Ties 29

2.10.1 Body Tied to Substrate 31
2.10.2 Body-tied to gate Configurations 32
2.10.3 Resistive Body Tie 33

2.11 Device Noise 34

2.12 Self Heating 36

2.12.1 Self Heating from elsewhere on the same chip 38
2.12.2 Self Heating from within a sub-circuit 39

Chapter 3: Components 47

3.1 MOS devices 47

3.2 Diodes 49

3.3 Bipolar Transistors 49

3.4 Lateral DMOS 51

3.5 Drain Extended Devices 53

3.5.1 Design of an SOI high voltage DEMOS device. 55

3.6 Compound High Voltage SOI Structures 56

3.7 Passive Components 57

3.7.1 Resistors 57
3.7.2 Capacitors 58
3.7.3 Inductors 59

Chapter 4: SOI Modeling 63

4.1 Modeling Introduction 63

4.2 Example SOI spice deck 66

4.3 Models 68
4.3.1 BSIM 68

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 SOI Design: Analog, Memory & Digital Techniques

4.4 Alternative Model Options 70

Chapter 5: Layout for SOI 75

5.1 Introduction to Layout for SOI components 75

5.2 Converting designs from Bulk to SOI 77

5.2.1 Diodes 77
5.2.2 Bipolar Transistors 79

5.3 Layout for Minimization of Thermal Self Heating Effects 80

5.3.1 Cross coupling with thermal coupling 81

5.4 Output Stages 83

Chapter 6: Static SOI Design

6.1 Introduction 85
6.1.1 Lower Fan Out Capacitance 87

6.2 Decreased Body Effect 87

6.3 Gate Leakage 88

6.4 Static Inverter Characteristics 89

6.5 Body Voltages in SOI Inverters 92

6.6 Body Voltage Convergence 94

6.6.1 Delay vs. effective gate length 94

6.7 Noise Margin In Inverters 95

6.8 Nand Gate Response 96

6.8.1 Body Voltage Response in Nand Gates 101

6.9 Nor Gate response 103

6.10 Static OR-AND SOICMOS Circuit 104

6.11 XOR Gate response in SOI 107

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SOI Design: Analog, Memory & Digital Techniques

6.12 Ring Oscillator Performance 108

6.12.1 Nand Fan-out of 3 ring-Performance vs. 109
6.12.2 Nand fanout of three - Performance vs supply 110
6.12.3 Nand fan-out of one 110

6.13 Pass Gate Response 112

6.13.1 Pass transistor based circuits 114
6.13.2 Pass transistors based Multiplexers 115

6.14 History Dependence 117

6.15 SOI vs BULK : Performance benefits in Digital Circuits 118

6.16 Floating body and hysteresis effect 119

6.17 Non Ideal diode characteristics 120

Chapter 7: Dynamic SOI Design

7.1 Introduction 125

7.2 Dynamic Circuit Response 125

7.2.1 Dynamic History Effect 125
7.2.2 Dynamic Charge Sharing 126
7.2.3 Capacitive Coupling Effects 126
7.2.4 Keeper Devices or Bleeders 127

7.3 Dynamic Circuit Design Considerations 129

7.4 Re-ordering and Remapping 130

7.5 Logical Remapping 130

7.6 Complex Domino 132

7.6.1 Three-input Domino OR Gate 132
7.6.2 Dynamic AND-OR Domino Gate 133

7.7 No-Race Logic (NORA) 136

7.8 Dynamic Noise Suppression 141

7.9 Design Issues in Dynamic 2-way NAND Logic 142

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 SOI Design: Analog, Memory & Digital Techniques

7.10 Dynamic 2-Way OR Circuit 145

7.11 Dynamic Cascade Switch Logic 147

7.12 Clocked CMOS 149

7.13 Pulse Stretching in Dynamic Circuits 153

7.14 Dynamic Wide-OR 157

7.15 Non Overlapping Clocks 158

7.16 Pass transistor based Non-Overlapping Clocks 159

7.17 Low Power SOI Techniques 161

7.17.1 Dynamic Threshold SOI CMOS 161
7.17.2 Dynamic Threshold Multithreshold CMOS Logic 162
7.17.3 Dynamic Threshold Pass Transistor Logic 164
7.17.4 Dynamic threshold voltage Full Adder 165
7.17.5 Dynamically Body Bias SOI CMOS Inverter 174

Chapter 8: SOI SRAMs

8.1 Introduction 181

8.2 SRAM Cell structures 182

8.3 Design considerations and specifications for SRAM Cells 185

8.3.1 4T-2R Polysilicon resistor load SRAM 186
8.3.2 SRAM cell with 2 thin-film transistor loads 186
8.3.3 6T-PMOS Load SRAM cells 186

8.4 Four Transistor SRAM using Self-body biased MOSFET 187

8.5 Basic SOI SRAM Cell operation 189

8.5.1 READ Operation in a SRAM Cell 189
8.5.2 Write operation in SRAM Cell 193

8.6 Cell Stability 197

8.7 SRAM Junction & Bit line capacitance 201

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SOI Design: Analog, Memory & Digital Techniques

8.8 Decoders 201

8.9 SRAM Architecture 203

8.10 Bit Line Related Architecture 205

8.11 Sense Amplifiers 206

8.11.1 Differential Amplifier 207
8.11.2 Clocked Dual Slope Sense Amplifiers 211
8.11.3 Dynamic Body Charge Controlled Sense Amplifier 213
8.11.4 SenseAmplifier Techniques 218

8.12 Mismatches in Sense Amplifiers 220

8.12.1 Offset Considerations for High Speed Sensing 223

8.13 Mismatch in SRAM Cells 225

8.13.1 Body Bias 225
8.13.2 Supply Rail Droop 225
8.13.3 Body-to-Body Coupling 226
8.13.4 Common Mode Supply Rail 226
8.13.5 MOS Junction capacitance 226
8.13.6 Self Heating 226

8.14 SER Issues in SRAMs 227

8.15 SOI CMOS Memory Challenges 228

8.16 Destructive read-out characteristics of SRAM 229

Chapter 9: SOI DRAMs

9.1 Introduction 235

9.2 DRAM structure and Operation 237

9.3 Memory Array 238

9.4 DRAM cell storage 241

9.4.1 Storage to Bit Line Capacitance 243

9.5 SOI DRAM Process 244

9.5.1 Smart-cut for DRAM 246
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 SOI Design: Analog, Memory & Digital Techniques

9.5.2 Quasi- SOI technology 246

9.6 Influence Of SER on SOI DRAMs 246

9.7 Cosmic Ray induced Soft Errors in SOI DRAMs 247

9.8 DRAM Refresh and Data Retention 249

9.8.1 Static Data Retention 249
9.8.2 Dynamic Data Retention 250
9.8.3 Parasitic Leakage in DRAMs 254

9.9 High Density DRAMs with Body Contacts 258

9.10 Operating Voltage Reduction 259

9.10.1 Half-Vdd Data Line Pre-charge 259
9.10.2 Signal To Noise Ratio 260

9.11 Sense Amplifier Operation 260

9.11.1 Sensing with Dummy Cell Structure 263
9.11.2 Sensing with Body Contacts 264
9.11.3 Body-Pulse Sense Amplifier (BPS) 265

9.12 Word Line Boosting 267

9.12.1 Boosted Word Line with body contacts 268
9.12.2 Boot-strapped Word line Driver 268

9.13 Charge pumps and generators 269

9.14 Embedded DRAMS in SOI 274

9.15 DRAM operation problems 274

9.16 SOI DRAM READ Critical Path Body Contacts 275

9.17 Synchronous Interface on DRAMs 276

9.18 High Speed Modes for Synchronous DRAMs 277

9.19 Prefetch Architecture 279

9.20 Other Architectures 280

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SOI Design: Analog, Memory & Digital Techniques

9.21 Destructive read out characteristics of DRAM 281

Chapter 10: SOI Analog Design

10.1 Introduction 289

10.1.1 Benefits of SOI for Analog Design 289
10.1.2 Drawbacks of Analog Design on SOI 289

10.2 Body Voltage Regulation 292

10.2.1 Dynamic Body 292

10.3 Circuit Thermal Coupling Effects 294

10.3.1 DC Thermal Coupling in Current Mirrors 294
10.3.2 Transient Thermal Coupling in Current Mirrors 294

10.4 Band-gap Designs 295

10.4.1 helper circuitry 298
10.4.2 “Threshold Voltage Difference” Voltage Reference 300

10.5 Charge Pump Circuitry 301

10.6 Amplifiers 302

10.6.1 Sense Amplifier 302
10.6.2 Operational Amplifiers 303
10.6.3 Operational Transconductance Amplifier Design 309

10.7 Matching 310

10.8 Output Stages / Buffers 311

10.9 High Voltage and Power Applications 312

10.10 Sample and Hold Circuitry 312

10.11 Circuits for RF/Wireless Applications 313

10.11.1 Radio Frequency Low Noise Amplifier (LNA) 314
10.11.2 Mixers and Analog Multipliers 316
10.11.3 Delay Locked Loop 317
10.11.4 Phase Locked Loop 319
10.11.5 Phase Detector 319
10.11.6 Loop Filter 320
10.11.7 Oscillators 320
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 SOI Design: Analog, Memory & Digital Techniques

10.12 Microwave Applications 324

10.13 Voltage Regulation 325

10.13.1 Series Regulator 325
10.13.2 LDO Regulator 325

10.14 Analog to Digital Converters (ADC) 326

10.14.1 Successive Approximation ADC 326
10.14.2 Flash Converters 327
10.14.3 Pipelined ADCs 329

10.15 Digital-to-Analog Converters (DAC) 330

10.16 Sigma Delta Modulator 331

10.17 Interface between Digital and Analog Circuitry 332

10.18 Power Amplifiers 333

10.19 Sensors and Actuators 333

Chapter 11: Global Design Issues

11.1 Introduction to Global Design Issues 339

11.1.1 Cell Libraries 339
11.1.2 Clock Distribution 339
11.1.3 Decoupling Capacitance and Series Resistance 340
11.1.4 High Temperature Operation 340
11.1.5 Gate Leakage 341

11.2 Noise Immunity 341

11.2.1 Circuit Noise 341
11.2.2 Capacitive Coupling Noise 342
11.2.3 Delay Noise 343
11.2.4 Logic Noise 343
11.2.5 Decoupling Capacitors 343

11.3 Latchup Immunity 343

11.4 Self Heating 346

11.5 Electrostatic Discharge (ESD) 347

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SOI Design: Analog, Memory & Digital Techniques

11.5.1 ESD Protection in Output Structures 348

11.6 Radiation Hard (Rad-Hard) Circuits 349

11.7 Reliability 350

11.7.1 IDDQ (Quiescent 351
11.7.2 Delay Fault Testing 354

11.8 Package and Bond wire 355

Chapter 12: Low Power Design

12.1 Introduction 359

12.2 Clocking 360

12.2.1 Clock Generation 360
12.2.2 Clock Distribution 360
12.2.3 Clock Gating 361

12.3 Options for Low Power 361

12.3.1 Static vs. Dynamic Logic 362
12.3.2 Gate Sizing 362
12.3.3 Minimizing Switching 363
12.3.4 Interconnect 363
12.3.5 Low Voltage Swing 363

12.4 Analog Low Voltage Operation 364

12.5 Floating Voltage Schemes 364

12.5.1 Low Voltage Output Operation 365

12.6 System Performance 366

12.7 System Power Management 367

12.7.1 Low Power Standby Modes 367
12.7.2 Supply Voltage during Standby 367
12.7.3 Trade-Off for Power 368

12.8 Instruction Set Architecture 368

12.8.1 Instruction Complexity: RISC or CISC 368

12.9 Reduction of Voltage below 3.3V 368

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 SOI Design: Analog, Memory & Digital Techniques

Chapter 13: SOI in Development

13.1 SOI Technology Roadmap 371

13.2 Device Enhancements 371

13.2.1 Enhanced-gate SOI MOSFET 371
13.2.2 FinFET 373

13.3 Quantum Devices 373

13.4 Stacked SOI 373

13.5 Reduced Temperature Operation 374

13.6 High Temperature Operation 374

13.7 New Circuit Designs for SOI 375

13.7.1 Merged Bipolar / MOS 375
13.7.2 Body Driven Operational Amplifier 375
13.7.3 Body-input D-Flip-Flop 377
13.7.4 SOI Transistor as a DRAM 377

Appendix 1: Internet Sites (issue 1.0) 381

Appendix 2: Trade Mark / Technology Information (issue 1.0) 382

Index 383

About the Authors 393

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Preface
In the 1850’s my wife's great-great grandfather wrote a medical textbook. In
the year and a half that it has taken to complete this work I have grown to
appreciate not only how difficult it is to write a book, but also how much
more difficult it must have been back then. One hundred and fifty years ago
Dr. Julius Jeffreys had to write his entire tome by hand, without the aid of
error correcting word processing software or even electric light. More
obviously in electronics than in many other fields, the pace of technology
development since that time has been astounding. Even in just the past fifty
years semiconductor technology has progressed from little more than a
laboratory curiosity to an integral part of our daily lives.

Now silicon on insulator technology is becoming the process of choice for

high performance consumer electronics, it is appropriate that memory
systems and analog circuitry are considered in a single volume with the SOI
process and logic implementation. Such an overview helps put SOI into
perspective. What we see is a very impressive technology, which holds a
great deal of promise. There are applications where SOI does not appear to
be a good fit, but generally it appears that SOI has a bright future.

We have compiled this book, based on available literature and SOI circuit
development work at Texas Instruments.

Chapter 1 introduces the reader to silicon on insulator, with a very brief

review of the history of SOI technology and circuits.

Chapter 2 briefly reviews the materials of SOI, and methods used to generate
the most common forms of SOI material used commercially. Manufacturing
considerations and materials properties are highlighted in this section.

In chapter 3 we review silicon on insulator devices, with discussion of how

they differ from devices available to the designer of bulk silicon integrated
circuits. Electrical properties associated with SOI devices are introduced in
the discussion of MOS devices, diodes, bipolar transistors and passives.

Chapter 4 explores the challenges of modeling SOI material and devices,

with particular emphasis on circuit simulation. The chapter will be of
particular interest to the designer of analog circuits, as an introduction to
circuit simulation of SOI components.

Chapter 5 introduces some concepts for successful SOI circuit layout. We

review various options for the reduction of thermal self-heating effects and

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consider the conversion of designs from bulk to SOI from a layout
perspective.

Chapters 6 and 7 provide a review of static and dynamic logic circuits by

way of introduction into the memory sections. While this has been covered
in detail elsewhere (notably Kerry Bernstein and Norman Rohrer’ SOI
Circuit Design Concepts), the summary here permits a full understanding of
the possibilities and challenges of SOI essential to a good cognition of more
complex circuitry.

Chapters 8 and 9 are devoted to the dominant memory structures in current

use, the SRAM and DRAM. Methods to improve memory performance at
the memory cell and sense amplifier level are discussed.

Chapter 10 addresses techniques to permit the integration of analog circuitry

into SOI designs. This is an inevitable requirement as SOI use transfers from
just microprocessors to DSP and mixed signal applications.

Chapters 11 and 12 examine global design issues, those issues that affect
both digital and analog circuit design, and are more easily discussed in a
general setting. Low power and low voltage circuit design is of particular
importance to the industry, and is thus considered in a chapter by itself.

Chapter 13 takes a look at some of the possibilities for SOI in development,

both from the material and circuit viewpoints.

For updates, corrections etc., the web site associated with this publication is
given in appendix 1. This site also has contact information where you the
reader may communicate suggestions, errata etc. We hope this will prove to
be a valuable source of data in this rapidly evolving field.

In summary, we echo the words of Kerry Bernstein and Norman Rohrer,

when in the final words of their preface to "SOI Circuit Design Concepts"
they state, "Rather than designing to avoid SOI's idiosyncrasies, the true
benefit of the technology may be realized when these features are exploited".

Andrew Marshall
Sreedhar Natarajan

October 2001

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 SOI Design: Analog, Memory & Digital Techniques

Acknowledgements

It is inevitable with a work of this length and scope that a huge

number of individuals have had a hand in enhancing the content.
We thank everyone involved in the work, but would especially
like to thank the following:

We extend a special thanks to the reviewers, for their very helpful

suggestions: Brock Barton, Charvaka Duvvury, John Fattaruso,
David Scott, Howard Tigelaar, Tom Vrotsos.

For discussions and insight: Terry Blake, James Burns, Xiaowei

Deng, Olivier Faynot, Jim Gallia, Keith Green, Ted Houston,
Keith Joyner, Weideng Liu, Homi Mogul, Betty Prince.

For drafting, simulation, and silicon evaluation: Erich Caulfield,

Andres Diaz, Imran Hossain, Rick Little, Gary Mathews, Brian
Neal, Michelle Nguyen, Mouli Vaidyanathan.

For enabling the work: Randy McKee, Yoshio Nishi, David

Spratt, Tom Thorpe and especially Wah Kit Loh.

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