Sequential Circuits :

inputs X Combinational outputs Z

Circuits
present state next state
Memory

A sequential circuit:
A combinational circuit with feedback through memory
 The stored information at any time defines a state
Outputs depends on inputs and previous inputs
 Previous inputs are stored as binary information into memory
Next state depends on inputs and present state
Sequential Circuits :
Types of Sequential Circuits
• Two types of sequential circuits:
• Synchronous: The behavior of the circuit depends on
the input signal at discrete instances of time (also called
clocked)
• Asynchronous: The behavior of the circuit depends on
the input signals at any instance of time and the order
of the inputs change
• A combinational circuit with feedback
Sequential Circuits :
 The output of sequential logic circuits not only depends on
current inputs but also on the past sequence of inputs.
 Very simple sequential circuit with no inputs created using
inverters to form a feedback loop.
Sequential Circuits : Latches, Flip-Flops
 Latches and flip-flops are basicly single-bit memory
elements used to build sequential circuit with one or two
inputs/outputs, designed using individual logic gates and
feedback loops.
 Flip-Flips are built with latches.
 Latches: The output of a latch depends on its current inputs
and on its previous inputs and its change of state can happen
at any time when its inputs change (level-sensitive).
 Flip-Flop: The output of a flip-flop also depends on current
and previous input but the change in output (change of state
or state transition) occurs at specific times determined by a
clock input (edge-sensitive).
Sequential Circuits : Latches
Latches:
 S-R Latch
 S-R Latch With Enable
 D-Latch
Sequential Circuits : S-R Latch

What does this circuit do?

Sequential Circuits : S-R Latch

Qold = 1

Q old = 0

Two states: Set (Q = 1) and Reset (Q = 0)

When S=R=0, Q remains the same, S=R=1 is not allowed!
Normally, S=R=0 unless the state need to be changed (memory?)
State of the circuit depends not only on the current inputs, but also
on the recent history of the inputs
Sequential Circuits :S-R Latch
Sequential Circuits : S’ R’ Latch

Similar to SR latch (complemented)

Two states: Set (Q = 0) and Reset (Q = 1)
When S=R=1, Q remains the same
S=R=0 is not allowed!
Sequential Circuits :
Sequential Circuits :
State Diagram and Characteristic Equation Of SR latch

Q(n+1) = S +R’ Qn
Sequential Circuits : SR Latch with Clock

An SR Latch can be modified to control when it changes

An additional input signal Clock (C)
When C=0, the S and R inputs have no effect on the latch
When C=1, the inputs affect the state of the latch and
possibly the output
Sequential Circuits : SR Latch with Clock

How can we eliminate the undefined state?

Sequential Circuits : D Latch
•Ensure S and R are never
equal to 1 at the same time
•Add inverter
•Only one input (D)
•D connects to S
•D’ connects to R
•D stands for data
•Output follows the input
when C = 1
•Transparent
•When C = 0, Q remains the
same
Sequential Circuits : Graphic Symbols for Latches

For S’R’ (SR built with NANDs)

Sequential Circuits : Problem with Latches
inputs X Combinational outputs Z
Circuits

Latches?

clock

 What happens if Clock=1? What will be the value Example

of Q when Clock goes to 0?
 Problem: A latch is transparent; state keep
changing as long as the clock remains active D Q Q
 Due to this uncertainty, latches can not be reliably
used as storage elements. Clock C Q
Sequential Circuits :Flip Flops
 A flip-flop is a one bit memory similar to latches
 Solves the issue of latch transparency
 Latches are level sensitive memory element
 Active when the clock = 1 (whole duration)
 Flip-Flops are edge-triggered or edge-sensitive
memory element
 Active only at transitions; i.e. either from 0  1 or 1  0
level

positive (rising) edge negative (falling) edge

Sequential Circuits :Flip Flops
clk clk

 A flip flop can be built using two latches in a master-slave

configuration
 A master latch receives external inputs
 A slave latch receives inputs from the master latch
 Depending on the clock signal, only one latch is active at any
given time
 If clk=1, the master latch is enabled and the inputs are latched
 if clk=0, the master is disabled and the slave is activated to generate the
outputs
Sequential Circuits :SR Flip Flop
Built using two latches (Master
and Slave)
1. C = 1, master is active
2. C = 0, slave is active
Q is sampled at the falling edge
Data is entered on the rising edge
of the clock pulse, but the output
does not reflect the change until
the falling edge of the clock pulse.
Sequential Circuits :
Sequential Circuits : JK Flip Flop

•How does it work?

•Hint: D = ?
Sequential Circuits : JK Flip Flop

•D = J Q’ + K’ Q
•J sets the flip flop to ‘1’ ,,, J=1 &K=0 D = 1 ( whatever Q &Q’ value)
•K reset the flip flop to ‘0’ ,,,, J =0 &K=1 D=0 ( whatever Q &Q’ value)
•When J = K = 1, the output is complemented
( Qt =0 , Qt+1 =1 , Qt+2=0, Qt+3=0 …………….
Sequential Circuits : JK Flip Flop

•D = J Q’ + K’ Q
JK Flip Flop built with SR latches
•J sets the flip flop (1)
•K reset the flip flop (0)
•When J = K = 1, the output is complemented
Sequential Circuits : JK Flip Flop
case1 : When J=0 and K=0 No change to the output
Case2 : When J=1 and K=0 Output set(ie Q=1)
case3 : When J=0 and K=1 Output Reset(ie Q=0)
case4 : When J=1 and K=1 Output is toggled (ie
When Qn =1 then Qn+1 = 0)
Sequential Circuits : T Flip Flop

•T (toggle) flip flop is a

complementing flip flop
•Built with a JK or D flip flop
(as shown above)
• D-FF implementation, D = T  Q
• T = 0, no change, T = 1,
complement (toggle)
Sequential Circuits : T Flip Flop
case1: When T=1 , then output is toggled
case2: When T=0 , then output is not change
Sequential Circuits :Direct Inputs

•Some flip-flops have asynchronous inputs to set/reset their states

independently of the clock.
•Preset or direct set, sets the flip-flop to 1
•Clear or direct reset, set the flip-flop to 0
•When power is turned on, a flip-flop state is unknown; Direct inputs are
useful to put in a known state
•Figure shows a positive-edge D-FF with active-low asynchronous reset.
Sequential Circuits :Flip Flops Sheet
Excitation Table
The excitation table gives the value of the flip-flop’s inputs that are
necessary to change the flip-flop’s current state to the desired next state
at the next active edge of the clock signal.

SR flip-flop excitation table/ state table.

 Excitation tables are used in design.

State Table Characteristics
• State table – a multiple variable table with the following four sections:

– Present State – the values of the state variables for each allowed state.
– Input – the input combinations allowed.
– Next-state – the value of the state at time (t+1) based on the present state and
the input.
– Output – the value of the output as a function of the present state and sometimes)
the input.
• From the view point of a truth table:
– the inputs are Input, Present State
– and the outputs are Output, Next State
State Table Characteristics
The state table can be filled in using the next state and output equations:
A(t+1) = A(t) x(t) + B(t) x(t)
B(t+1) = A'(t) x(t)
y(t) = x'(t) (B(t) + A(t))

Present State Input Next State Output

A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 0 1
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 1 0 0
State Table Characteristics
Alternate State Table form for :
A(t+1) = A(t) x(t) + B(t) x(t)
B(t+1) = A'(t) x(t)
y(t) = x'(t) (B(t) + A(t))
State Diagrams
• The sequential circuit function can be represented in graphical
form as a state diagram with the following components:
State Diagram
is a graph that shows the flip-flop’s operations in terms of how it
transitions from one state to another.

Remember how the state diagram

arrows correspond to rows of the state
table:
present input/output next
state state

For example, to go from state Q = 0 to the state Q = 1, the two inputs S

and R have to be 1 and 0 respectively. Similarly, if the current state is Q
= 0 and we want to remain in that state, then SR need to be 00 or 01.
Analysis with D flip-flop

What is the input equation : …………………………………………….

what is the state table : ??
Analysis with D flip-flop (count)

What is the state diagram : ????

Analysis with D flip-flop (count)
Analysis with J K flip-flop
Analysis with J K flip-flop

Input equation :
Sequential Circuit Analysis
Example : analysis the following circuit:

Equations
– A(t+1) = ………
– Z =. ………
Sequential Circuit Analysis
Inputs
State/Output
Sequential Circuit Analysis
Example : analysis the following circuit:

Equations
– A(t+1) =
– B(t+1) =
– C(t+1) =
Z =
Sequential Circuit Analysis :
PRESENT STATE NEXT STATE OUTPUT

Equations A B C At+ Bt+ Ct+ Z(t)

– A(t+1) = 0 0 0

– B(t+1) = 0 0 1
0 1 0
– C(t+1) = 0 1 1
Z = 1 0 0
1 0 1
1 1 0
1 1 1

State table
Sequential Circuit Analysis
State diagram:
Sequential Circuit Analysis
Ex: Determine the
combinational circuit
which specifies the
external outputs and
the flip-flop inputs?
Sequential Circuit Analysis

State table
Sequential Circuit Analysis

State table
Input equation
Sequential Circuit Analysis
Design of Sequential Circuits
• Design Procedure:
• Obtain a state diagram from the word description
• State reduction if necessary
• Obtain State Table
• State Assignment
• Choose type of flip-flops
- The number of flip-flops is determined from the number of states in the circuit
- n flip-flops can represent up to 2n binary states.

• Use FF’s excitation table to complete the table

• Derive state equations
• Obtain the FF input equations and the output equations
• Use K-Maps
• Draw the circuit diagram
Design of Sequential Circuits

Design a clocked sequential circuit that

operates according to the state diagram.
Design of Sequential Circuits
 The next step is to create a state table and then select two D flip
flops to represent the four states, labeling their outputs as A and
B.
 There is one input, x, and one output, y, representing the input
sequence and the output value respectively.
 Remember that the characteristic equation of the D flip flop is
 Q(t + 1) = DQ
 This means that the next-state values in the state table
specify the D input condition for the flip flop.
Design of Sequential Circuits

oState table derived

from state diagram :

o Input equations can be obtained directly from the table using

minterms:
 A(t + 1) = DA(A, B, x) = ∑(2,4,5,6)

 B(t + 1) = DB(A, B, x) = ∑(1,3,5,6)

Design of Sequential Circuits
Design of Sequential Circuits
Design of Sequential Circuits

DA = AB’ + BX’

DB= A’X + B’X+ ABX’

Y = B’X
Design of Sequential Circuits

Example: No output 0
00
1
1
1
01 11
0

0 1
10

0
Design of Sequential Circuits
State Table
Present Next
State State
0 0
0 1

0 0
0 1

Fall 2012 ENG241/Digital Design 57

Design of Sequential Circuits
State Table Bx
00 01 11 10
A
0 0 0 0 1 JA = BX’
1 X X X X
Design of Sequential Circuits

59
Design of Sequential Circuits
Design of Sequential Circuits

Example: Design a circuit that detects a sequence of three

consecutive 1’s in a string of bits coming through an input line
(serial bit stream)
Design of Sequential Circuits

•Assign binary codes for the states

•We choose 2 D-FF
•Next state specifies what should be
the input to each FF
present state ‫تعتمد على‬
government input ‫مش ح نلقوا‬

Stat diagram
Design of Sequential Circuits
Design of Sequential Circuits

Using K-Maps
•A(t + 1) = DA = ∑(3,5,7) = A x + B x
•B(t + 1) = DB = ∑(1,5,7) = A x + B’ x
•y = ∑(6,7) = A B
Design of Sequential Circuits

•A(t + 1) = DA = ∑(3,5,7) = A x + B x
•B(t + 1) = DB = ∑(1,5,7) = A x + B’ x
•y = ∑(6,7) = A B
Examples for revision
Q3- a: Implement the following functions using 2-4 decoders then using 2-to-1 multiplexer
- f(a,b,c) = a' b'c' + ab'c + a' b' c + a b c'
Use NAND gate for the first circuit.

- f (x,z,w,y) = (x + y + z) (w + z + w +x' ) ( y' + z ) ( w' +z' + y' ) ( w' + x ).

Use NOR gates for the first circuit.
Q-4 Design a four bit multiplier using full adders, and AND gates.
Q3- Use four Full adders and a minimum additional gates to design the following circuits:
•4-bit increment circuit (adds 1 to 4 bit- binary number).

•4-bit decrement circuit (subtract 1 from 4 bit binary number).

•4-bit circuit that generates the 2's complement of the binary input number.

design a one 4-bit circuit equivalent to the above three circuit.

Q4- a: design a circuit that sums A1,A0 and B1,B0 ,where A and b are BCD numbers and
display the sum on a three seven- segment. Show all your work .