S1D13506 Color LCD/CRT/TV Controller

S5U13506B00C Evaluation Board

User Manual

Document Number: X25B-G-004-08

Copyright © 1999 - 2009 Epson Research and Development, Inc. All Rights Reserved.

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
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Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1.1 On-Board PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.2 Utility Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Non-PCI Host Interface Support . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 LCD Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.1 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.2 Buffered LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.3 16-bit Passive Color Panel Support with MediaPlug Enabled . . . . . . . . . . . . 17
4.3.4 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . . . 18
4.3.5 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . . . . 18
4.4 CRT/TV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.1 CRT/TV Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2 CRT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.3 TV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 MediaPlug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 Clock Synthesizer and Clock Options . . . . . . . . . . . . . . . . . . . . . 21
4.6.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1 EPSON LCD/CRTControllers (S1D13506) . . . . . . . . . . . . . . . . . . . 32

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1 Introduction
This manual describes the setup and operation of the S5U13506B00C Evaluation Board.
The S5U13506B00C is designed as an evaluation platform for the S1D13506 Color
LCD/CRT/TV Controller chip.

This user manual will be updated as appropriate. Please check the Epson Research and
Development Website at http://www.erd.epson.com for the latest revision of this document
before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at

documentation@erd.epson.com.

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2 Features
The S5U13506B00C features the following:
• S1D13506 Color LCD/CRT/TV controller chip.
• Headers for connecting to a 3.3V or 5V host bus interface.
• 1Mx16 EDO DRAM.
• Configuration options.
• Adjustable positive LCD bias power supplies from +24V to +40V.
• Adjustable negative LCD bias power supplies from -23V to -14V.
• 4/8-bit 3.3V or 5V monochrome passive LCD panel support.
• 4/8/16-bit 3.3V or 5V color passive LCD panel support.
• 9/12/18-bit 3.3V or 5V TFT/D-TFD LCD panel support.
• Embedded RAMDAC for CRT and TV support.
• WINNOV VideumCam digital camera support at 320x240x256 colors at 30 frames per
second.
• Clock synthesizer for maximum clock flexibility.
• Software initiated Power Save Mode.
• Selectable clock source for BUSCLK and CLKI.

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3 Installation and Configuration

The S5U13506B00C is designed to support as many platforms as possible. The
S5U13506B00C incorporates a DIP switch and several jumpers which allow both evalu-
ation board and S1D13506 LCD controller settings to be configured for a specified evalu-
ation platform.

3.1 Configuration DIP Switches

The S1D13506 LCD controller has 16 configuration inputs (MD[15:0]) which are read on
the rising edge of RESET#. Where appropriate, the S5U13506B00C hard-wires some of
these configuration inputs, but in order to configure the S1D13506 for multiple host bus
interfaces a ten-position DIP switch is required. The following DIP switch settings
configure the S1D13506.

Table 3-1: Configuration DIP Switch Settings

value of this pin at rising edge of RESET# is used to configure:(1/0)
Switch Signal
Closed/On=1 Open/Off=0
S1-1 MD1
S1-2 MD2 See Table 3-2:, “Host Bus Selection” on page 8
S1-3 MD3
S1-4 MD4 Little Endian Big Endian
S1-5 MD5 WAIT# is active high WAIT# is active low
S1-6 MD10 Reserved. This switch must be in the closed position.
S1-7 MD11 See Table 3-2:, “Host Bus Selection” on page 8
S1-8 MD12 BUSCLK input divided by 2 BUSCLK input not divided
MD13: FPDAT[15:8] is MediaPlug interface;
MD13, MD13: support 16-bit STN panels directly.
S1-9 external latches required for 16-bit STN panels.
MD14 MD14: MA11 is GPIO2.
MD14: MA11 is VMPEPWR.
S1-10 MD15 WAIT# is always driven. WAIT# is tristated when S1D13506 is not selected.

= Required configuration when used in a PCI environment with MediaPlug disabled

Note
MD13 and MD14 are configured using the same switch, for further information see Sec-
tion 7, “Schematic Diagrams” on page 25.

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The following table shows the Host Bus Interface options available. The Host Bus Interface
chosen will depend on the evaluation platform to be used.

Table 3-2: Host Bus Selection

MD11 MD3 MD2 MD1 Host Bus Interface
0 0 0 0 SH-4/SH-3
0 0 0 1 MC68K Bus 1
0 0 1 0 MC68K Bus 2
0 0 1 1 Generic
0 1 0 0 Reserved
0 1 0 1 MIPS/ISA
0 1 1 0 PowerPC
0 1 1 1 PC Card
1 1 1 1 Philips PR31500/PR31700 / Toshiba TX3912

= Required configuration when used in a PCI environment

3.2 Configuration Jumpers

The S5U13506B00C has seven jumper blocks which configure various board settings. The
jumper positions for each function are shown below.

Table 3-3: Jumper Settings

Jumper Function Position 1-2 Position 2-3 Jumper Off
S1D13506 VDD
JP1 3.3V 5V n/a
Selection
JP2 LCD panel signalling 5V 3.3V n/a
MediaPlug interface (eight jumpers at 1-2, 16-bit LCD panel MSBs
JP3 FPDAT[15:8] function
3-4, 5-6, 7-8, 9-10, 11-12, 13-14 and 15-16) (all jumpers disconnected)
JP4 BUSCLK Buffered 33MHz from PCI bus From header n/a
JP5 GPIO2 to VMPEPWR MediaPlug interface used n/a MediaPlug interface not used
JP6 CLKI From clock synthesizer From header n/a
JP7 IREF for CRT/TV DAC 4.6mA for CRT 9.2mA for TV n/a
JP8 FPDAT[15:8] output Always use this position Do not use this position n/a
JP9 PCI bridge FPGA Disabled for non-PCI host n/a Enabled for PCI host

= Default configuration

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4 Technical Description
The S5U13506B00C operates with both PCI and non-PCI evaluation platforms. It supports
display types such as, passive LCD panels (4/8/16-bit), TFT/D-TFD panels (9/12/18-bit),
CRT and TV (NTSC and PAL). Additionally, it supports a variety of clock options.

4.1 PCI Bus Support

As a PCI device, the S5U13506B00C has the following characteristics.

• 33MHz bus clock.
• Target with no interrupts.
• Non-cacheable memory read and write.
• 3.3V or 5V PCI signalling.

Note
In a 3.3V PCI system, the S1D13506 must be powered at 3.3V by setting jumper JP1. In
a 5V PCI system, the S1D13506 may be powered at either 3.3V or 5V.

Although the S1D13506 does not support the PCI bus directly, the S5U13506B00C
supports the PCI bus using a PCI Bridge Adapter FPGA. The FPGA translates PCI accesses
into PC Card accesses which are then decoded by the S1D13506.

A 4M byte PCI address range is allocated to the S5U13506B00C by the system BIOS. The
S1D13506 uses this address range to map the internal registers and the 2M byte display
buffer. The following table shows the memory mapping of the PCI address block.

Table 4-1: S1D13506 Memory Mapping onto 4M byte PCI Address Block
PCI Memory Offset Description S1D13506 M/R# S1D13506 AB[20:0]
00 0000h to 00 01FFh General registers (512 byte) 0 00 0000h to 00 01FFh
00 1000h to 00 1FFFh MediaPlug registers (4K byte) 0 00 1000h to 00 1FFFh
10 0000h to 1F FFFFh BitBlt data registers (1M byte) 0 10 0000h to 1F FFFFh
20 0000h to 3F FFFFh Display Buffer (2M byte) 1 00 0000h to 1F FFFFh

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4.1.1 On-Board PCI Configuration Registers

Read-Only Registers

The PCI Bridge Adapter FPGA provides configuration registers which contain
identification information required by the PCI interface. The following values are
hard-wired into these registers.

Table 4-2: PCI Configuration Register Read Values

Name Address Register size Value
Vendor ID 0h 16 bits 10F4h
Device ID 2h 16 bits 1300h
Status 6h 16 bits 400h
Revision ID 8h 8 bits 1
Class Code 9h 24 bits FF 0000h
Subsystem Vendor ID 2Ch 16 bits 10F4h
Subsystem ID 2Dh 16 bits 8000h
Header Type Eh 8 bits 0
n/a Fh-FFh 32 bits 0

Read/Write Registers

The PCI Bridge Adapter FPGA provides two read/write registers which are used for access
enabling and memory mapping as follows.

Table 4-3: PCI Configuration Register Write Values

Name Address Register size Valid bits Meaning
Command 4h 16 bits Bit 1 only; other bits are zero. Access enabled if high
Base Address 10h 32 bits Bits 31 to 22; other bits are zero. Position of 4M byte reserved window

4.1.2 Utility Software

All utility software for the S5U13506B00C evaluation board is fully PCI compliant and
handles the PCI configuration registers automatically.

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4.2 Non-PCI Host Interface Support

The S5U13506B00C is specifically designed to support a standard PCI bus environment

(using the PCI Bridge Adapter FPGA). However, the S5U13506B00C can directly support
many other Host Bus Interfaces. When the FPGA is disabled (using jumper JP9), headers
H1 and H2 provide the necessary IO pins to interface to the Host Bus Interfaces listed in
Table 4-4:, “CPU Interface Pin Mapping”. The S1D13506 power supply must be set to
3.3V or 5V (using jumper JP1) according to the host CPU signalling voltage.

4.2.1 CPU Interface Pin Mapping

The functions of the S1D13506 host interface pins are mapped to each host bus interface
according to the following table.
Table 4-4: CPU Interface Pin Mapping
S1D1350
Motorola Motorola Philips
6 Hitachi Motorola Toshiba
Generic MIPS/ISA MC68K MC68K PC Card PR31500
Pin SH-4/SH-3 PowerPC TX3912
Bus 1 Bus 2 /PR31700
Names
AB20 A20 A20 LatchA20 A20 A20 A11 A20 ALE ALE
AB19 A19 A19 SA19 A19 A19 A12 A19 /CARDREG CARDREG*
AB18 A18 A18 SA18 A18 A18 A13 A18 /CARDIORD CARDIORD*
AB17 A17 A17 SA17 A17 A17 A14 A17 /CARDIOWR CARDIOWR*
AB[16:13] A[16:13] A[16:13] SA[16:13] A[16:13] A[16:13] A[15:18] A[16:13] Connected to VDD
AB[12:1] A[12:1] A[12:1] SA[12:1] A[12:1] A[12:1] A[19:30] A[12:1] A[12:1] A[12:1]
AB0 A01 A01 SA0 LDS# A0 A31 A01 A0 A0
DB[15:8] D[15:0] D[15:8] SD[15:0] D[15:8] D[31:24] D[0:7] D[15:0] D[23:16] D[23:16]
DB[7:0] D[7:0] D[7:0] SD[7:0] D[7:0] D[23:16] D[8:15] D[7:0] D[31:24] D[31:24]
WE1# WE1# WE1# SBHE# UDS# DS# BI -CE2 /CARDxCSH CARDxCSH*
M/R# External Decode Connected to VDD
CS# External Decode Connected to VDD
BUSCLK BCLK CKIO CLK CLK CLK CLKOUT CLK DCLKOUT DCLKOUT
Connected Connected to Connected
BS# to VDD
BS# VDD
AS# AS# TS to VDD
Connected to VDD
Connected to
RD/WR# RD1# RD/WR# VDD
R/W# R/W# RD/WR -CE1 /CARDxCSL CARDxCSL*
Connected
RD# RD0# RD# MEMR# to VDD
SIZ1 TSIZ0 -OE /RD RD*
Connected
WE0# WE0# WE0# MEMW# to VDD
SIZ0 TSIZ1 -WE /WE WE*

RDY#
WAIT# WAIT# IOCHRDY DTACK# DSACK1# TA -WAIT /CARDxWAIT CARDxWAIT*
/WAIT#
inverted inverted
RESET# RESET# RESET# RESET# RESET# RESET# RESET# PON*
RESET RESET

Note
1 A0 for these busses is not used internally by the S1D13506.

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4.2.2 CPU Bus Connector Pin Mapping

The pinouts for Connector H1 are listed in the following table.

Table 4-5: CPU/BUS Connector (H1) Pinout

Pin No. Function
1 Connected to DB0 of the S1D13506
2 Connected to DB1 of the S1D13506
3 Connected to DB2 of the S1D13506
4 Connected to DB3 of the S1D13506
5 Ground
6 Ground
7 Connected to DB4 of the S1D13506
8 Connected to DB5 of the S1D13506
9 Connected to DB6 of the S1D13506
10 Connected to DB7 of the S1D13506
11 Ground
12 Ground
13 Connected to DB8 of the S1D13506
14 Connected to DB9 of the S1D13506
15 Connected to DB10 of the S1D13506
16 Connected to DB11 of the S1D13506
17 Ground
18 Ground
19 Connected to DB12 of the S1D13506
20 Connected to DB13 of the S1D13506
21 Connected to DB14 of the S1D13506
22 Connected to DB15 of the S1D13506
23 Connected to RESET# of the S1D13506
24 Ground
25 Ground
26 Ground
27 +12 volt supply, required in non-PCI applications
28 +12 volt supply, required in non-PCI applications
29 Connected to WE0# of the S1D13506
30 Connected to WAIT# of the S1D13506
31 Connected to CS# of the S1D13506
32 Connected to MR# of the S1D13506
33 Connected to WE1# of the S1D13506
34 S1D13506 supply, provided by the S5U13506B00C

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The pinouts for Connector H2 are listed in the following table.

Table 4-6: CPU/BUS Connector (H2) Pinout
Pin No. Function
1 Connected to AB0 of the S1D13506
2 Connected to AB1 of the S1D13506
3 Connected to AB2 of the S1D13506
4 Connected to AB3 of the S1D13506
5 Connected to AB4 of the S1D13506
6 Connected to AB5 of the S1D13506
7 Connected to AB6 of the S1D13506
8 Connected to AB7 of the S1D13506
9 Ground
10 Ground
11 Connected to AB8 of the S1D13506
12 Connected to AB9 of the S1D13506
13 Connected to AB10 of the S1D13506
14 Connected to AB11 of the S1D13506
15 Connected to AB12 of the S1D13506
16 Connected to AB13 of the S1D13506
17 Ground
18 Ground
19 Connected to AB14 of the S1D13506
20 Connected to AB15 of the S1D13506
21 Connected to AB16 of the S1D13506
22 Connected to AB17 of the S1D13506
23 Connected to AB18 of the S1D13506
24 Connected to AB19 of the S1D13506
25 Ground
26 Ground
27 +5 volt supply, required in non-PCI applications
28 +5 volt supply, required in non-PCI applications
29 Connected to RD/WR# of the S1D13506
30 Connected to BS# of the S1D13506
31 Connected to S1D13506 BUSCLK if JP4 is in position 2-3
32 Connected to RD# of the S1D13506
33 Connected to AB20 of the S1D13506
34 Connected to S1D13506 CLKI if JP6 is in position 2-3

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4.3 LCD Support

The S1D13506 supports 4/8-bit dual and single passive monochrome panels, 4/8/16-bit
dual and single passive color panels, and 9/12/18-bit active matrix color TFT/D-TFD
panels. All necessary signals are provided on the 40-pin LCD connector (J1). The interface
signals are alternated with grounds on the cable to reduce cross-talk and noise. When
supporting an
18-bit TFT/D-TFD panel, the S1D13506 can display 64K of a possible 256K colors
because only 16 of the18 bits of LCD data are available from the S1D13506. For details,
refer to the S1D13506 Hardware Functional Specification, document number X25B-A-
001-xx.

For S1D13506 FPDAT[15:0] pin mapping for various types of panel see Table 4-7:, “LCD
Signal Connector (J1)” on page 15.

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4.3.1 LCD Interface Pin Mapping

Table 4-7: LCD Signal Connector (J1)
Monochrome Passive
Color Passive Panels
Panels Color TFT/D-TFD
S1D13506 Connector
Single Single Panels
Pin Names Pin No. Single Dual Single Single Dual
Format 1 Format 2

4-bit 8-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 8-bit 16-bit 9-bit 12-bit 18-bit
FPDAT0 1 D0 LD0 D0 D0 D0 LD0 LD0 R2 R3 R5
FPDAT1 3 D1 LD1 D1 D1 D1 LD1 LD1 R1 R2 R4
FPDAT2 5 D2 LD2 D2 D2 D2 LD2 LD2 R0 R1 R3
FPDAT3 7 D3 LD3 D3 D3 D3 LD3 LD3 G2 G3 G5
FPDAT4 9 D0 D4 UD0 D0 D4 D4 D8 UD0 UD0 G1 G2 G4
FPDAT5 11 D1 D5 UD1 D1 D5 D5 D9 UD1 UD1 G0 G1 G3
FPDAT6 13 D2 D6 UD2 D2 D6 D6 D10 UD2 UD2 B2 B3 B5
FPDAT7 15 D3 D7 UD3 D3 D7 D7 D11 UD3 UD3 B1 B2 B4
FPDAT8 17 D4 LD4 B0 B1 B3
FPDAT9 19 D5 LD5 R0 R2
FPDAT10 21 D6 LD6 R1
FPDAT11 23 D7 LD7 G0 G2
FPDAT12 25 D12 UD4 G1
FPDAT13 27 D13 UD5 G0
FPDAT14 29 D14 UD6 B0 B2
FPDAT15 31 D15 UD7 B1
FPSHIFT 33 FPSHIFT
DRDY 35 and 38 MOD FPSHIFT2 MOD DRDY
FPLINE 37 FPLINE
FPFRAME 39 FPFRAME
2-26
GND GND
(Even Pins)
N/C 28 N/C
VLCD 30 Adjustable -23 to -14V negative LCD bias
LCDVCC 32 +5V or +3.3V according to JP2
+12V 34 +12V
VDDH 36 Adjustable +24 to +40V positive LCD bias
NC (pin 75)2 40 Panel Enable, active low (LCDPWR)2

= Driven low

Note
1
For FPDATxx to LCD interface hardware connections refer to the Display Interface
AC Timing section of the S1D13506 Hardware Functional Specification, document
number X25B-A-001-xx.
2
The S5U13506B00C was designed using S1D13506 pin 75 (LCDPWR) to control the
LCD bias power. This design is no longer supported. Applications should use one of
the available GPIO pins to control the LCD bias power allowing for software control

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of power sequencing delays. For further information on LCD power sequencing, see
the S1D13506 Programming Notes and Examples, document number X25B-G-003-
xx.

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4.3.2 Buffered LCD Connector

J1 provides the same LCD panel signals as those directly from S1D13506, but with
voltage-adapting buffers which can be set to 3.3V or 5V. Pin 32 on this connector provides
power for the LCD panel logic at the same voltage as the buffer power supply.

4.3.3 16-bit Passive Color Panel Support with MediaPlug Enabled

When the MediaPlug option is enabled, (MD13 and MD14 set to “On”, see Table 3-1:,
“Configuration DIP Switch Settings” on page 7) S1D13506 pins FPDAT[15:8] are used for
the MediaPlug interface and are not available for panel connection. Instead, S1D13506 pins
FPDAT[7:0] are multiplexed for 16-bit panel operation. If the MediaPlug option is selected
and 16-bit panel operation is desired, demultiplexing circuitry must be built externally
according to the schematic below. Refer to Table 4-7:, “LCD Signal Connector (J1)” on
page 15 for connector pin mapping.

Single color 16-bit passive panels can be used with the following modifications.

D[7:0]
To 16-bit panel
FPDAT[7:0] D[15:8]
D Q
FROM
S5U13506B00C
FPSHIFT
CK

74AHC374

Figure 4-1: External Circuit for Color Single 16-Bit Panel with MediaPlug Enabled

Dual color 16-bit passive panels can be used with the following modifications.

UD [3:0]
LD [3:0]
FPDAT[7:4] To 16-bit panel
UD [7:4]
D Q
FPDAT[3:0] LD [7:4]
FROM
S5U13506B00C
FPSHIFT CK

74AHC374

Figure 4-2: External Circuit for Color Dual 16-Bit Panel with MediaPlug Enabled

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4.3.4 Adjustable LCD Panel Positive Power Supply

For LCD panels which require a positive bias voltage between +24V and +40V
(Iout=45mA), a power supply has been provided as an integral part of the S5U13506B00C
design. The voltage on VDDH can be adjusted using R15 to provide an output voltage from
+24V to +40V and can be enabled and disabled by LCDPWR (S1D13506 pin 75).

The S5U13506B00C was designed using LCDPWR (pin 75) to control the LCD bias
power. This design is no longer supported. Applications should use one of the available
GPIO pins to control the LCD bias power allowing for software control of power
sequencing delays. For further information on LCD power sequencing, see the S1D13506
Programming Notes and Examples, document number X25B-G-003-xx.

Note
Before connecting the panel, set the potentiometer according to the panel’s specific
voltage requirements.

4.3.5 Adjustable LCD Panel Negative Power Supply

For LCD panels which require a negative bias voltage between -23V and -14V
(Iout=25mA), a power supply has been provided as an integral part of the S5U13506B00C
design. The voltage on VLCD can be adjusted using R21 to provide an output voltage from
-23V to -14V, and can be enabled and disabled by LCDPWR (S1D13506 pin 75).

The S5U13506B00C was designed using LCDPWR (pin 75) to control the LCD bias
power. This design is no longer supported. Applications should use one of the available
GPIO pins to control the LCD bias power allowing for software control of power
sequencing delays. For further information on LCD power sequencing, see the S1D13506
Programming Notes and Examples, document number X25B-G-003-xx.

Note
Before connecting the panel, set the potentiometer according to the panel’s specific
voltage requirements.

S1D13506 S5U13506B00C Evaluation Board User Manual

X25B-G-004-08 Issue Date: 2009/03/02
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Vancouver Design Center

4.4 CRT/TV Support

4.4.1 CRT/TV Interface Pin Mapping

CRT/TV signals are supplied on a standard CRT connector (J3), Composite Video
connector (J2), and S-Video connector (J4):

Table 4-8: CRT/TV Interface Pin Mapping

S1D13506
CRT Composite Video S-Video
Pin Name
HRTC Horizontal retrace N/A N/A
VRTC Vertical retrace N/A N/A
RED Red N/A Luminance
GREEN Green Composite N/A
BLUE Blue N/A Chrominance

4.4.2 CRT Support

CRT support is provided on connector J3 via the S1D13506 embedded RAMDAC. An

external current reference is implemented to provide the necessary RAMDAC output gain.
The reference current (IREF) should be set to 4.6mA using jumper JP7.

Note
When IREF is set to 4.6mA, the DAC Output Select bit (REG[05Bh] bit 3) must be set
to 1.

CRT output is not available when TV output is enabled.

4.4.3 TV Support

The S1D13506 supports PAL or NTSC TV output. Composite Video is available on

connector J2 and S-Video is available on connector J4. An external current reference is
implemented to provide the necessary RAMDAC output gain. The reference current should
be set to 9.2mA using jumper JP7.

TV output is not available when CRT output is enabled. PAL and NTSC modes cannot be
enabled at the same time.

S5U13506B00C Evaluation Board User Manual S1D13506

Issue Date: 2009/03/02 X25B-G-004-08
Page 20 Epson Research and Development
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4.5 MediaPlug Interface

The S5U13506B00C supports the Winnov Videum®Cam digital camera through the
S1D13506 built-in MediaPlug interface. The Winnov Videum®Cam digital camera inputs
are TTL compatible and can be driven by the S1D13506 powered at 3.3V or 5V. Therefore,
the power supply to the camera is 5V while the S1D13506 can powered at 3.3V or 5V.
However, if the S1D13506 is powered at 5V, then 150nH inductors must be added at
locations L8, L10, L11, L12 and L13.

Jumper JP5 selects whether MA11/GPIO2 is used to enable the video camera power. For
more information, see the note from Section 3.2, “Configuration Jumpers” on page 8. Eight
jumpers identified globally as JP3 must be set for MediaPlug operation.

The table below describes the S1D13506 pin mapping for the MediaPlug interface.

Table 4-9: MediaPlug Connector (J5) Pin Mapping

S1D13506 Connector Pin
IO Type MediaPlug I/F
Pin Names No.
FPDAT8 1 O VMPLCTL
FPDAT9 2 I VMPRCTL
FPDAT10 3 IO VMPD0
FPDAT11 4 IO VMPD1
FPDAT12 6 IO VMPD2
FPDAT13 5 IO VMPD3
FPDAT14 8 O VMPCLK
FPDAT15 7 O VMPCLKN
MA11/GPIO2 9 O VMPEPWR
GND Shield - Ground

Note
When MediaPlug is enabled, 16-bit passive panels support requires an external circuit.
See Section 4.3.3, “16-bit Passive Color Panel Support with MediaPlug Enabled” on
page 17.

S1D13506 S5U13506B00C Evaluation Board User Manual

X25B-G-004-08 Issue Date: 2009/03/02
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Vancouver Design Center

4.6 Clock Synthesizer and Clock Options

For maximum flexibility, the S5U13506B00C implements a Cypress ICD2061A Clock

Generator. MCLKOUT from the clock chip is connected to CLKI of the S1D13506 and
VCLKOUT from the clock chip is connected to CLKI2 of the S1D13506. A 14.31818MHz
crystal (Y1) is connected to XTALIN of the clock chip and a 17.734475MHz oscillator
(U14) is connected to the FEATCLK input of the clock chip. The diagram below shows a
simplified representation of the clock synthesizer connections.

ICD2061A
Synthesizer reference
14.31818 MHz XTALIN MCLKOUT CLKI

Feature clock for PAL TV

17.734475 MHz FEATCLK VCLKOUT CLKI2

Figure 4-3: Symbolic Clock Synthesizer Connections

Upon power-up, CLKI (MCLKOUT) is 40MHz and CLKI2 (VCLKOUT) is configured to

25.175MHz.

4.6.1 Clock Programming

The S1D13506 utilities automatically program the clock generator. If manual programming
of the clock generator is required, refer to the source code for the S1D13506 utilities
available on the internet at www.eea.epson.com.

For further information on programming the clock generator, refer to the Cypress
ICD2061A specification.

Note
When CLKI and CLKI2 are programmed to multiples of each other (e.g. CLKI =
20MHz, CLKI2 = 40MHz), the clock output signals from the Cypress clock generator
may jitter. Refer to the Cypress ICD2061A specification for details.

To avoid this problem, set CLKI and CLKI2 to different frequencies and configure both
LCD PCLK and CRT/TV PCLK to use the same clock input (CLKI or CLKI2).Then use
the S1D13506 internal clock divides (LCD PCLK Divide Select REG[014h] bits 5-4,
CRT/TV PCLK Divide Select REG[018h] bits 5-4) to obtain the lower frequencies.

S5U13506B00C Evaluation Board User Manual S1D13506

Issue Date: 2009/03/02 X25B-G-004-08
Page 22 Epson Research and Development
Vancouver Design Center

5 References

5.1 Documents
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
• Cypress Semiconductor Corporation, ICD2061A Data Sheet.

5.2 Document Sources

• Epson Research and Development Website: http://www.erd.epson.com.
• Cypress Semiconductor Corporation Website: http://www.cypress.com.

S1D13506 S5U13506B00C Evaluation Board User Manual

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Vancouver Design Center

6 Parts List
Table 6-1: Parts List
Item Quantity Reference Part Description
C1-C6,C10,C13-C16,C32-C34,
1 22 0.1uF 1206 capacitor +/-20% 50V
C46-C49,C52,C54,C55,C57
2 4 C7,C8,C9,C38 0.01uF 1206 capacitor +/-20% 50V
3 6 C11,C12,C40,C45,C53,C56 10uF/16V Tantalum size C, 10uF 16V +/-10%
4 2 C17,C21 47uF/10V Tantalum size C, 47uF 10V +/-10%
5 3 C18,C19,C20 4.7uF/50V Tantalum size D, 4.7uF 50V +/-10%
6 1 C22 56uF/35V Low-ESR radial electrolytic capacitor
C23,C24,C25,C26,C27,C28,C29,
7 9 0.22uF 1206 capacitor +/-20% 50V
C30,C31
8 6 C35,C36,C37,C39,C41,C42 33pF 1206 capacitor +/-20% 50V
9 2 C43,C44 220pF 1206 capacitor +/-20% 50V
10 2 C50,C51 not populated 1206 capacitor, not populated
11 4 D1,D2,D3,D5 BAV99L Diode BAV99L
12 1 D4 BAT54 Diode BAT54
13 2 H1,H2 Header 17X2 0.1" x 0.1" 2 rows by 17 header
14 2 JP5,JP9 Header 2 0.1" 1 row by 2 header
15 6 JP1,JP2,JP4,JP6,JP7,JP8 Header 3 0.1" 1 row by 3 header
16 1 JP3 Header 8X2 Not populated
2x20, .025" sq. shrouded connector,
17 1 J1 Header 20x2
ctr-key, t/h
18 1 J2 C-Video Keystone 901 or equivalent
19 1 J3 CRT AMP 749264 or equivalent
20 1 J4 S-Video Assman A-HDF 15 A KG/T or equivalent
CUI Stack P/N:MD-90S or Digi-Key
21 1 J5 MediaPlug Connector
P/N:CP-2490-ND
22 8 L1,L2,L3,L5,L6,L7,L14,L15 Ferrite Philips BDS3/3/8.9-4S2
RCD MCI-1812 1uH MT or MSI-1812 1uH
23 1 L4 1uH
MT
Panasonic ELJNCR15JF or
24 1 L9 150nH
Delevan 1008-151K
25 3 Q1,Q5,Q6 MMBT2222A Transistor MMBT2222A
26 1 Q2 MMBT3906 Transistor MMBT3906
27 1 Q3 MMBT3904 Transistor MMBT3904
28 1 Q4 NDS9400A National Semi NDS9400A
29 16 R1-R11,R17,R26,R29,R61,R62 15K 1206 resistor +/-5%
30 1 R13 470K 1206 resistor +/-5%
31 6 R14,R16,R18,R19,R47,R50 10K 1206 resistor +/-5%
32 1 R15 200K potentiometer Spectrol 63S204T607
33 4 R20,R21,R23,R56 100K 1206 resistor +/-5%

S5U13506B00C Evaluation Board User Manual S1D13506

Issue Date: 2009/03/02 X25B-G-004-08
Page 24 Epson Research and Development
Vancouver Design Center

Table 6-1: Parts List (Continued)

Item Quantity Reference Part Description
34 1 R22 100K potentiometer Spectrol 63S104T607
35 3 R24,R25,R30 1K 1206 resistor +/-5%
36 3 R31,R32,R33 150 1% 1206 resistor +/-1%
37 1 R34 6.04K 1% 1206 resistor +/-1%
38 6 R35,R38,R41,R44,R48,R53 68 Ohms 1206 resistor +/-5%
39 1 R36 1.5K 1% 1206 resistor +/-1%
40 3 R37,R43,R46 316 1% 1206 resistor +/-1%
41 3 R39,R45,R49 357 1% 1206 resistor +/-1%
42 2 R40,R42 137 1% 1206 resistor +/-1%
43 2 R51,R54 22 Ohms 1206 resistor +/-5%
44 2 R52,R55 33 Ohms 1206 resistor +/-5%
45 1 R57 1.5K 1% 1206 resistor +/-1%
46 1 R58 1K 1% 1206 resistor +/-1%
47 1 R59 140 Ohms 1% 1206 resistor +/-1%
48 1 R60 69.8 Ohms 1% 1206 resistor +/-1%
49 1 R63 4.7K 1206 resistor +/-5%
50 1 S1 SW DIP-10 10-position DIP switch
51 1 S2 SW DIP-4 Not populated
52 1 U1 S1D13506F00A Epson S1D13506F00A
Alliance AS4LC1M16E5-50JC or
53 1 U2 DRAM 1Mx16-SOJ ISSI IS41LV16100K-50 or
OKI MSM51V18165D50-JS
54 1 U3 RD-0412 Xentek RD-0412
TI 74AHC04 or National 74VHC04 SO-14
55 1 U4 74AHC04
package
56 1 U5 EPN001 Xentek EPN001
57 1 U6 EPF6016TC144-2 Altera EPF6016TC144-2
58 1 U7 EPC1441PC8 Altera EPC1441PC8
TI 74AHC244 or National 74VHC244
59 3 U8,U9,U10 74AHC244
SO-20 package
Linear Technology LT1117CST-5 or
60 1 U11 LT1117CST-5
SGS-Thomson LD1117S50C
61 1 U12 ICD2061A Cypress ICD2061A
Linear Technology LT1117CST-3.3 or
62 1 U13 LT1117CST-3.3
SGS-Thomson LD1117S33C
Linear Technology LT1117CM-3.3 or
63 1 U15 LT1117CM-3.3
SGS-Thomson LD1117DT33C
17.734475MHz 14-DIP
64 1 U14 DIP-14 oscillator
oscillator
TI 74AHC374 or National 74VHC374,
65 1 U16 74AHC374
SO-20 package
14.31818MHz crystal HC-49 Fox
66 1 Y1 14.31818MHz crystal
FoxS/143-20

S1D13506 S5U13506B00C Evaluation Board User Manual

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A B C D E

AB[20:0] MA[9:0]
P2,4 AB[20:0] MA[9:0] P3
U1
AB0 3 61 MA0
AB1 AB0 MA0 MA1
2 AB1 MA1 63
AB2 1 65 MA2
AB3 AB2 MA2 MA3
128 67
Epson Research and Development

AB4 AB3 MA3 MA4

127 AB4 MA4 66
AB5 126 64 MA5
AB6 AB5 MA5 MA6
125 AB6 MA6 62
AB7 124 60 MA7
4 AB8 AB7 MA7 MA8 4
123 AB8 MA8 58
AB9 122 56 MA9
AB10 AB9 MA9/GPIO3
121 AB10 MA10/GPIO1 59
AB11 GPIO1 P7
120 AB11 MA11/GPIO2 57
AB12 GPIO2 P7
119 AB12
AB13 118 35 MD0

S5U13506B00C Evaluation Board User Manual

AB14 AB13 MD0 MD1
117 AB14 MD1 37
AB15 116 39 MD2
AB16 AB15 MD2 MD3
115 AB16 MD3 41
AB17 114 43 MD4
AB18 AB17 MD4 MD5
113 AB18 MD5 45
AB19 112 47 MD6
DB[15:0] AB20 AB19 MD6 MD7
111 AB20 MD7 49
P2,4 DB[15:0] MD8
MD8 48
DB0 31 46 MD9
DB1 DB0 MD9 MD10
30 DB1 MD10 44
DB2 29 42 MD11
DB3 DB2 MD11 MD12
28 DB3 MD12 40
7 Schematic Diagrams

DB4 27 38 MD13
DB5 DB4 MD13 MD14
26 DB5 MD14 36
DB6 25 34 MD15 MD[15:0]
DB7 DB6 MD15 MD[15:0] P3
24 DB7
DB8 23 54
DB9 DB8 RAS# RAS# P3
3 22 DB9 LCAS# 51 3
DB10 LCAS# P3
21 DB10 UCAS# 52
DB11 UCAS# P3
20 DB11 WE# 53 WE# P3
DB12 19
DB13 DB12 FPDAT[15:0]
18 DB13
DB14 FPDAT[15:0] P5,6
17 DB14
DB15 16 79 FPDAT0
DB15 FPDAT0 FPDAT1
FPDAT1 80
13 81 FPDAT2
P7 BUSCLK BUSCLK FPDAT2
82 FPDAT3
FPDAT3 FPDAT4
P2,4 CS# 4 CS# FPDAT4 83
5 84 FPDAT5
P2,4 M/R# M/R# FPDAT5
10 85 FPDAT6
P2,4 RD/WR# RD/WR# FPDAT6
9 86 FPDAT7
P2,4 WE1# WE1# FPDAT7
8 88 FPDAT8
P2,4 WE0# WE0# FPDAT8
7 89 FPDAT9
P2,4 RD# RD# FPDAT9
6 90 FPDAT10
P2,4 BS# BS# FPDAT10
91 FPDAT11
FPDAT11 FPDAT12
P2,4 RESET# 11 RESET# FPDAT12 92
93 FPDAT13
FPDAT13 FPDAT14
P2,4 WAIT# 15 WAIT# FPDAT14 94
95 FPDAT15
FPDAT15

P7 CLKI 69 CLKI FPFRAME 73 FPFRAME P5

2 FPLINE 74 2
FPLINE P5
P7 CLKI2 71 CLKI2 FPSHIFT 77
FPSHIFT P5
DRDY 76
DRDY P5

NC 75 LCDPWR P3,5
70 TESTEN

RED 100
JP1 RED P5
ChipVdd 12 VDD GREEN 103 GREEN P5
1 +3.3V ChipVdd 33 VDD BLUE 105 BLUE P5
2 ChipVdd 55 VDD
ChipVdd
3 +5V 72 VDD HRTC 107
ChipVdd HRTC P5 L1
97 VDD VRTC 108
ChipVdd VRTC P5
ChipVdd 109 VDD +3.3V AVDD
HEADER 3

Figure 7-1: S5U13506B00C Schematic Diagram (1 of 7)

IREF 101 IREF P7
14 Ferrite
VSS
32 VSS
50 99 C10
VSS DACVDD AVDD
68 VSS DACVDD 102 AVDD 0.1u
78 104 L2
VSS DACVDD AVDD
87 VSS
ChipVdd ChipVdd ChipVdd ChipVdd ChipVdd ChipVdd 96 98 AVDD AVDD AVDD
VSS DACVSS Ferrite
110 VSS DACVSS 106
1 C1 C2 C3 C4 C5 C6 C7 C8 C9 1
S1D13506F00A
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.01u 0.01u 0.01u

Title
S5U13506B00C Evaluation Board

Size Document Number Rev

B {Doc} 1

Date: Thursday, April 01, 1999 Sheet 1 of 7

A B C D E

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S1D13506
Page 25
 Page 26

S1D13506
X25B-G-004-08
A B C D E

AD[31:0] P1,4 DB[15:0] DB[15:0]

P4 AD[31:0]

4 4
+5V +12V +5V +12V +12V
PCIA1 PCIB1
1 1 H1
TRST# -12V DB0 DB1
2 +12V TCK 2 1 2
3 3 DB2 DB3
TMS GND 3 4
4 4
TDI TDO DB4 5 6 DB5
5 +5V +5V 5 7 8
6 6 DB6 DB7
INTA# +5V 9 10
7 INTC# INTB# 7 11 12
8 8 DB8 DB9
+5V INTD# DB10 13 14 DB11
9 RESERVED PRSNT#1 9 15 16
10 +VI/O RESERVED 10 17 18
11 11 DB12 DB13
RESERVED PRSNT#2 DB14 19 20 DB15
21 22
P1,4 RESET# 23 24
14 RESERVED RESERVED 14 25 26
P4 RST# 15 15
RST# GND 27 28
16 +VI/O CLK 16 CLK P4 P1,4 WE0# 29 30 WAIT# P1,4
17 GNT# GND 17 P1,4 CS# 31 32 M/R# P1,4
18 18 P1,4 WE1# ChipVdd
GND REQ# 33 34
19 RESERVED +VI/O 19
AD30 20 20 AD31 (Provided by the S5U13506B00C)
AD30 AD31 HEADER 17X2
3 21 21 AD29 3
AD28 +3.3V AD29
22 AD28 GND 22
AD26 23 23 AD27
AD26 AD27 AD25
24 GND AD25 24
AD24 25 25 +5V +5V
AD24 +3.3V
P4 IDSEL 26 26 C/BE3# P4
IDSEL C/BE3# AD23 H2
27 +3.3V AD23 27
AD22 28 28 AB0 AB1
AD20 AD22 GND AD21 AB2 1 2 AB3
29 AD20 AD21 29 3 4
30 30 AD19 AB4 AB5
AD18 GND AD19 AB6 5 6 AB7
31 AD18 +3.3V 31 7 8
AD16 32 32 AD17
AD16 AD17 AB8 9 10 AB9
33 +3.3V C/BE2# 33 C/BE2# P4 11 12
34 34 AB10 AB11
P4 FRAME# FRAME# GND 13 14
35 35 AB12 AB13
GND IRDY# IRDY# P4 15 16
P4 TRDY# 36 TRDY# +3.3V 36 17 18
37 37 AB14 AB15
GND DEVSEL# DEVSEL# P4 19 20
38 38 AB16 AB17
P4 STOP# STOP# GND 21 22
39 39 AB18 AB19
+3.3V LOCK# 23 24
40 SDONE PERR# 40 PERR# P4 25 26
41 SBO# +3.3V 41 27 28
42 GND SERR# 42 SERR# P4 P1,4 RD/WR# 29 30 BS# P1,4
P4 PAR 43 PAR 3.3V 43 P7 EXTBCLK 31 32 RD# P1,4
AD15 44 44 AB20
AD15 C/BE1# C/BE1# P4 33 34 EXTCLKI P7
2 45 45 AD14 2
AD13 +3.3V AD14
46 AD13 GND 46 HEADER 17X2
AD11 47 47 AD12
AD11 AD12 AD10
48 GND AD10 48
AD9 49 49 AB[20:0]
AD9 GND P1,4 AB[20:0]

52 52 AD8
P4 C/BE0# C/BE0# AD8
53 53 AD7
AD6 +3.3V AD7
54 AD6 +3.3V 54
AD4 55 55 AD5
AD4 AD5 AD3
56 GND AD3 56
AD2 57 57
AD0 AD2 GND AD1
58 AD0 AD1 58
59 +VI/O +VI/O 59
60 REQ64# ACK64# 60
61 +5V +5V 61
62 +5V +5V 62

PCI-A PCI-B

Figure 7-2: S5U13506B00C Schematic Diagram (2 of 7)

+5V +5V

1 1
+ C11 + C12
10uF/16V 10uF/16V

Title
S5U13506B00C Evaluation Board

Size Document Number Rev

B {Doc} 1

Date: Thursday, April 01, 1999 Sheet 2 of 7

A B C D E

Issue Date: 2009/03/02

S5U13506B00C Evaluation Board User Manual
Epson Research and Development
Vancouver Design Center
 A B C D E

Issue Date: 2009/03/02

ChipVdd
Vancouver Design Center

MD[15:0]
P1 MD[15:0] R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
MA[9:0] 15K 15K 15K 15K 15K 15K 15K 15K 15K 15K
P1 MA[9:0] U2
MA0 17 2 MD0 S1
MA1 A0 DQ0 MD1 MD1
18 A1 DQ1 3 1 20
MA2 19 4 MD2 MD2 2 19
MA3 A2 DQ2 MD3 MD3
4
20 A3 DQ3 5 3 18 4
MA4 23 7 MD4 MD4 4 17
MA5 A4 DQ4 MD5 MD5
24 A5 DQ5 8 5 16
Epson Research and Development

MA6 25 9 MD6 MD10 6 15

MA7 A6 DQ6 MD7 MD11
26 A7 DQ7 10 7 14
MA8 27 33 MD8 MD12 8 13
MA9 28 A8R/A8 DQ8 34 MD9 MD13 9 12
A9R/A9 DQ9 MD10 MD15
16 A10/NC DQ10 35 10 11
15 36 MD11
A11/NC DQ11 MD12
DQ12 38 SW DIP-10 ChipVdd
39 MD13
P1 RAS# 14 /RAS
30 /UCAS DQ13 40 MD14
P1 UCAS# DQ14 MD15 R11 R12
P1 LCAS# 31 /LCAS DQ15 41

S5U13506B00C Evaluation Board User Manual

15K n/p
P1 WE# 13 /W VCC 1 ChipVdd
11 NC VCC 6 MD6
VCC 21 MD14
12 NC
32 NC VSS 22 C13 C14 C15
VSS 37 MD13
29 /OE VSS 42 0.1u 0.1u 0.1u

DRAM 1Mx16-SOJ R63

3 4.7K 3

U3
MD14
RD-0412

Rework

DC_IN
REMOTE
GND
GND
GND
GND
GND
GND
GND
NC
VOUT_ADJ
DC_OUT

2
3
4
5
6
7
8
10
11
9
1
12
L4
L3
+5V VDDH P5
+5V 1uH
Ferrite C16 + C17 R13
0.1u 47uF/10V 470K
R14
10K
2 + C18 + C19 + C20 2
R15 4.7uF/50V 4.7uF/50V 4.7uF/50V
200K Pot.

ChipVdd U4A
R16 3
1 2 1 Q1 R17
P1,5 LCDPWR +5V
2MMBT2222A 15K
74AHC04 10K
R18 2
U5 1 Q2
3 MMBT3906
EPN001
10K

R19
10K +5V
R20

DC_IN
DC_IN
VOUT_ADJ
GND
GND
NC
NC
NC
NC
DC_OUT
DC_OUT
R21
1

100K

Figure 7-3: S5U13506B00C Schematic Diagram (3 of 7)

11
10
6
5
4
9
8
7
3
2
1
100K
1 2 3 1
VLCD P5
Q3
MMBT3904
+ C21 + C22
47uF/10V Title
R22 56uF/35V S5U13506B00C Evaluation Board
100K Pot. Low ESR
Size Document Number Rev
B {Doc} 1
Date: Monday, June 14, 1999 Sheet 3 of 7
A B C D E

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S1D13506
Page 27
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S1D13506
X25B-G-004-08
A B C D E

BCLK P7
RD# P1,2
BS# P1,2
RD/WR# P1,2
WE1# P1,2
M/R# P1,2
CS# P1,2
4 WAIT# P1,2 4
ChipVdd
WE0# P1,2
RESET# P1,2
AB[20:0]
AB[20:0] P1,2

AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
DATA

DCLK
+5V DB[15:0]
DB[15:0] P1,2

DB15
DB14
DB13
DB12
DB11
DB10
R23
100K

144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
U6 EPF6016TC144-2 +5V +5V

GND
Vccio
DATA

DCLK

IO144
IO143
IO142
IO141
IO140
IO139
IO138
IO137
IO136
IO135
IO134
IO133
IO132
IO131
IO130
IO129
IO124
IO123
IO122
IO121
IO120
IO119
IO118
IO117
IO116
IO115
IO114
IO113
IO112
IO111
IO110
IO109
R24 R25
AB14 1 108 DB9 1K 1K
AB15 IO1 IO108
2 IO2 IO107 107 DB8
AB16 3 106 DB7
IO3 IO106
4 nCE CONF_DONE 105 CONF_DONE
U7
5 GND Vccio 104
6 103 DATA 1 8 +5V
Vccint Vccint DATA VCC +5V
7 102 DCLK 2 7
Vccio GND DCLK VCC +5V
AB17 8 101 DB6 nSTATUS 3 6
AB18 IO8 IO101 CONF_DONE OE nCASC C23
3 9 IO9 IO100 100 DB5 4 nCS GND 5 3
AB19 10 99 DB4 0.22u
IO10 IO99
11 IO11 IO98 98 DB3 EPC1441PC8
12 IO12 IO97 97
13 IO13 IO96 96 DB2
14 IO14 IO95 95 DB1 FPGA configuration EPROM
AB20 15 94
IO15 IO94
16 IO16 IO93 93 DB0
17 I17 I92 92
18 GND Vccio 91
19 Vccio GND 90
20 89 S2
P2 CLK I20 I89
21 IO21 IO88 88 1 8 +5V
22 IO22 IO87 87 2 7 +5V
23 IO23 IO86 86 3 6 +5V
24 IO24 IO85 85 4 5 +5V
25 IO25 IO84 84
26 83 AD0
P2 RST# AD31 IO26 IO83 AD1 R26 R27 R28 R29 SW DIP-4
27 IO27 IO82 82
AD30 28 81 AD2 15K 15K 15K 15K
AD29 IO28 IO81 AD3
29 IO29 IO80 80
30 79 AD4
GND IO79
31 Vccint Vccio 78
32 Vccio Vccint 77
2 33 76 +5V +5V +5V +5V 2
AD28 MSEL GND AD5
34 IO34 IO75 75
AD27 35 74 AD6
AD26 IO35 IO74 AD7 C24 C25 C26 C27
36 IO36 IO73 73

IO37
IO38
IO39
IO40
IO41
IO42
IO43
IO44
IO45
IO46
IO47
IO48
IO49
IO50
IO51
IO52
nCONFIG
GND
Vccio
nSTATUS
IO57
IO58
IO59
IO60
IO61
IO62
IO63
IO64
IO65
IO66
IO67
IO68
IO69
IO70
IO71
IO72
0.22u 0.22u 0.22u 0.22u

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
ChipVdd ChipVdd ChipVdd ChipVdd

C28 C29 C30 C31

0.22u 0.22u 0.22u 0.22u

AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

nSTATUS
+5V

AD[31:0]
P2 AD[31:0] R30
1K
P2 C/BE3#
P2 IDSEL

Figure 7-4: S5U13506B00C Schematic Diagram (4 of 7)

P2 C/BE2#
JP9
P2 FRAME# nCONFIG
1 P2 IRDY# 1 1
P2 TRDY# 2
P2 DEVSEL#
HEADER 2
P2 STOP#
P2 PERR#
P2 SERR# Title
P2 PAR Place jumper to disable FPGA
S5U13506B00C Evaluation Board
P2 C/BE1#
P2 C/BE0# Size Document Number Rev
B {Doc} 1

Date: Thursday, April 01, 1999 Sheet 4 of 7

A B C D E

Issue Date: 2009/03/02

S5U13506B00C Evaluation Board User Manual
Epson Research and Development
Vancouver Design Center
 A B C D E

Issue Date: 2009/03/02

FPDAT[15:0]
P1,6 FPDAT[15:0] U8 J1
Vancouver Design Center

FPDAT0 2 18 BFPDAT0 BFPDAT0

FPDAT1 1A1 1Y1 BFPDAT1 BFPDAT1 1 2
4 1A2 1Y2 16 3 4
FPDAT2 6 14 BFPDAT2 BFPDAT2
FPDAT3 1A3 1Y3 BFPDAT3 BFPDAT3 5 6
8 1A4 1Y4 12 7 8
FPDAT4 11 9 BFPDAT4 BFPDAT4
FPDAT5 2A1 2Y1 BFPDAT5 BFPDAT5 9 10
13 2A2 2Y2 7 11 12
FPDAT6 15 5 BFPDAT6 BFPDAT6
FPDAT7 2A3 2Y3 BFPDAT7 BFPDAT7 13 14
17 2A4 2Y4 3 15 16
4 BFPDAT8 4
LCDVCC BFPDAT9 17 18
1 1G VCC 20 19 20
19 10 BFPDAT10
Epson Research and Development

2G GND BFPDAT11 21 22
C32 BFPDAT12 23 24
74AHC244 25 26
0.1u BFPDAT13 JP2
BFPDAT14 27 28 +5V
29 30 VLCD P3 1
BFPDAT15 LCDVCC
BFPSHIFT 31 32 2
33 34 +12V 3
BDRDY +3.3V
35 36 VDDH P3
BFPLINE HEADER 3
BFPFRAME 37 38
U9 39 40
U16

S5U13506B00C Evaluation Board User Manual

FPDAT8 3 2 BFPDAT8 FPDAT8 2 18 BFPDAT8
FPDAT9 D0 Q0 BFPDAT9 FPDAT9 1A1 1Y1 BFPDAT9 Header 20x2
4 D1 Q1 5 4 1A2 1Y2 16
ChipVdd FPDAT10 7 6 BFPDAT10 ChipVdd FPDAT10 6 14 BFPDAT10
FPDAT11 D2 Q2 BFPDAT11 FPDAT11 1A3 1Y3 BFPDAT11
8 D3 Q3 9 8 1A4 1Y4 12
FPDAT12 13 12 BFPDAT12 FPDAT12 11 9 BFPDAT12
R61 FPDAT13 D4 Q4 BFPDAT13 R62 FPDAT13 2A1 2Y1 BFPDAT13
14 D5 Q5 15 13 2A2 2Y2 7
JP8 15K FPDAT14 17 16 BFPDAT14 15K FPDAT14 15 5 BFPDAT14
DIRECT FPDAT15 D6 Q6 BFPDAT15 FPDAT15 2A3 2Y3 BFPDAT15
1 18 D7 Q7 19 17 2A4 2Y4 3
2 MUXED LCDVCC DIRECT LCDVCC
3 1 OC VCC 20 1 1G VCC 20
3 11 CLK GND 10 19 2G GND 10 3
HEADER 3 74AHC374 C57 C33
74AHC244
0.1u 0.1u

U10
FPSHIFT 2 18 BFPSHIFT
P1 FPSHIFT DRDY 1A1 1Y1 BDRDY
4 1A2 1Y2 16
P1 DRDY FPLINE BFPLINE
6 1A3 1Y3 14
P1 FPLINE FPFRAME BFPFRAME
P1 FPFRAME 8 1A4 1Y4 12
LCDPWR 11 9 BLCDPWR
P1,3 LCDPWR 2A1 2Y1
13 2A2 2Y2 7
15 2A3 2Y3 5
17 2A4 2Y4 3

1 20 LCDVCC
1G VCC
19 2G GND 10
C34 J2
74AHC244
0.1u
1 C-VIDEO
2 2
2

J3
L5 6
1
P1 RED Ferrite 11
L6 7
P1 GREEN 2
Ferrite 12
L7 8
3
P1 BLUE Ferrite J4
13
9
2
2
2

AVDD AVDD AVDD 4 4 3

R31 R32 R33 14 C Y
150 1% 150 1% 150 1% 10 2 1
G G
5
15
3 3 3

Figure 7-5: S5U13506B00C Schematic Diagram (5 of 7)

S-VIDEO
D1 D2 D3
BAV99L BAV99L BAV99L CRT
1
1
1

1 1

P1 HRTC
Title
P1 VRTC S5U13506B00C Evaluation Board

Size Document Number Rev

B {Doc} 1

Date: Thursday, April 01, 1999 Sheet 5 of 7

A B C D E

X25B-G-004-08
S1D13506
Page 29
 Page 30

S1D13506
X25B-G-004-08
A B C D E

ChipVdd ChipVdd L8

3
2 D4 R34 n/p
6.04K 1%
BAT54

1
R35
VMPRCTL
4 68 4
R36
1.5K 1% C35
33pF

L9
VMPLCTL

VMPD0 150nH
C36
33pF
ChipVdd

R37
316 1%

VMPD1 R38

3 3
68 J5
ChipVdd R39 MPLCTL
L10 1
357 1% C37 MPRCTL
33pF MPD0 2
MPD1 3
R40 n/p MPD3 4
137 1% MPD2 5
MPCLKN 6
C38 R41 MPCLK 7
MPPWR 8
9
10

3
0.01u 68 Q4
ChipVdd R42 L11 +5V NDS9400A
P1,5 FPDAT[15:0] FPDAT[15:0] 137 1% 8 MediaPlug Conn.
2 1 C39 3 7
JP3 33pF 2 6
FPDAT9 R43 n/p 1 5
1 2 316 1% D5
FPDAT8 + C40
FPDAT10 3 4
5 6 4 10uF/16V
FPDAT11 BAV99L R44
FPDAT13 7 8 VMPD3
FPDAT12 9 10
FPDAT15 11 12 68
FPDAT14 13 14 R45 ChipVdd +5V
2 15 16 L12 2
357 1%
HEADER 8X2 C41
33pF
R46 n/p
316 1% R47

R48 10K
VMPD2

68
R49 L13
357 1%
C42
33pF
n/p U4B
ChipVdd
R50 3
3 4 1 Q5
P7 VMPEPWR
R51 R52 2MMBT2222A
VMPCLKN
74AHC04 10K
22 33

Figure 7-6: S5U13506B00C Schematic Diagram (6 of 7)

C43
220pF R53
1 68 1

R54 R55
VMPCLK
Title
22 33 S5U13506B00C Evaluation Board
C44
220pF Size Document Number Rev
B {Doc} 1

Date: Wednesday, June 16, 1999 Sheet 6 of 7

A B C D E

Issue Date: 2009/03/02

S5U13506B00C Evaluation Board User Manual
Epson Research and Development
Vancouver Design Center
 A B C D E

Issue Date: 2009/03/02

U11
L14 LT1117CST-5
Vancouver Design Center

3 2 OSCVDD
+12V VIN VOUT JP4

ADJ
HEADER 3
Ferrite
+ C45

1
2
3

1
10uF/16V C46 C47
0.1u 0.1u
4 4
Epson Research and Development

EXTBCLK P2

JP5
P4 BCLK BUSCLK P1
HEADER 2

1
2
JP6

S5U13506B00C Evaluation Board User Manual

HEADER 3

1
2
3
VMPEPWR P6 L15
Ferrite

P1 GPIO2
P1 GPIO1 EXTCLKI P2
U4C
C48 C49 ChipVdd
R56

13
3
3 0.1u 0.1u 5 6 CLKI P1 3
100K
U12

VDD
1 74AHC04
S0/CLK

AVDD
2 S1/DATA
OSCVDD 12 8 U4D
INIT0 MCLKOUT ChipVdd
14 INIT1
VCLKOUT 9 9 8 CLKI2 P1
16 PWRDWN#
4 OE
74AHC04
Y1 6 XTALIN
7 XTALOUT ERROUT# 10

14.31818MHz 11

GND
C50 C51 FEATCLK
15 INTCLK
n/p n/p

5
ICD2061A

U13
IREF P1
LT1117CST-3.3
+5V 3 VIN VOUT 2
2 2
U14
ADJ

+5V 14 VCC NC 1
C52 + C53 JP7
1

7 8 0.1u 10uF/16V
GND OUT HEADER 3
C54 R57
1.5K 1%
1
2
3

0.1u
17.734475MHz
3
1 Q6
2
MMBT2222A
R58
1K 1%
U15
LT1117CM-3.3 R59 R60
U4E 3 2 140 1% 69.8 1%
ChipVdd +5V VIN VOUT +3.3V
11 10
ADJ

C55 + C56
1

0.1u

Figure 7-7: S5U13506B00C Schematic Diagram (7 of 7)

74AHC04 10uF/16V

1 1
U4F
ChipVdd
13 12

Title
74AHC04 S5U13506B00C Evaluation Board

Size Document Number Rev

B {Doc} 1

Date: Thursday, April 01, 1999 Sheet 7 of 7

A B C D E

X25B-G-004-08
S1D13506
Page 31
Page 32 Epson Research and Development
Vancouver Design Center

8 Technical Support

8.1 EPSON LCD/CRTControllers (S1D13506)

AMERICA ASIA
EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD.
2580 Orchard Parkway 7F, Jinbao Bldg., No.89 Jinbao St.,
San Jose, CA 95131,USA Dongcheng District,
Phone: +1-800-228-3964 FAX: +1-408-922-0238 Beijing 100005, CHINA
Phone: +86-10-6410-6655 FAX: +86-10-6410-7320

SHANGHAI BRANCH
7F, Block B, High-Tech Bldg., 900, Yishan Road,
EUROPE Shanghai 200233, CHINA
EPSON EUROPE ELECTRONICS GmbH Phone: +86-21-5423-5522 FAX: +86-21-5423-5512
Riesstrasse 15, 80992 Munich,
GERMANY SHENZHEN BRANCH
Phone: +49-89-14005-0 FAX: +49-89-14005-110 12F, Dawning Mansion, Keji South 12th Road,
Hi-Tech Park, Shenzhen 518057, CHINA
Phone: +86-755-2699-3828 FAX: +86-755-2699-3838

EPSON HONG KONG LTD.

20/F, Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
Phone: +852-2585-4600 FAX: +852-2827-4346
Telex: 65542 EPSCO HX

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

14F, No. 7, Song Ren Road,
Taipei 110, TAIWAN
Phone: +886-2-8786-6688 FAX: +886-2-8786-6660

EPSON SINGAPORE PTE., LTD.

1 HarbourFront Place,
#03-02 HarbourFront Tower One, Singapore 098633
Phone: +65-6586-5500 FAX: +65-6271-3182

SEIKO EPSON CORP.

KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: +82-2-784-6027 FAX: +82-2-767-3677

SEIKO EPSON CORP.

SEMICONDUCTOR OPERATIONS DIVISION

IC Sales Dept.
IC International Sales Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814 FAX: +81-42-587-5117

S1D13506 S5U13506B00C Evaluation Board User Manual

X25B-G-004-08 Issue Date: 2009/03/02
Epson Research and Development Page 33
Vancouver Design Center

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S5U13506B00C Evaluation Board User Manual S1D13506

Issue Date: 2009/03/02 X25B-G-004-08