$255 Programmable peripheral Interface (PPL) = SS a | erour croura |. _PA —T con wor KS ke Porta: KS CONTROL e power{—- sv | SUPPLIES|—+ GND J, PArPAy | | | | GROUP A | rey, 1 porTG [ALA Y BI-OIRECHONAL | Upper Dawe @ J Pop PCy — oan [aL __ _. —__ | aus ——— in | INTERNAL DATA BUS roar ig | eae o,PCy ices [ oR ear tare rou crours * contxon |-* +} ae PORTS 8 CONTROL @) oy} So Fig. 14.2 Block diagram of 82554 \) 6258 PPL 1% a progeammable peripheval clevice - 9+ can be osed. to transfer data under 3) Simple ‘Input | outpa Condition 2%) Strobed ( Inre Tsuph) Input] output Condition 2) The denice have %) 2 ports #) Two 4-bit ports ( Port Cuppa bit ports can be Used Independe together as one- S bit port yol word Tegistes COWR) ( pert and Fert B , each of S bit) Q Port Crower) . these 4~ otly oF tt canbe usec %*) 8 bit cont 3) post A and port B canbe used to precess $ bit parallel data 44) Port can operate 16 #) Single bit BSR Coit set] Reset) mede #) to generate handshakiag signals for Port A and Port B. ® PCO to PCS generates handshaking signal fox Port 8. *) PC4 to Ply generates fandshaeig Agnat for Pert A5) Ao and Ax line Is Used to elect the ports or CWR Ay Ao © 0 —- PortA of Port 8 1 © —~ Poste tL L — CWR 6) WR-2 When WR 20, then 9085 ustites He cata cn pest pins When RD =O, $085 can cad he data of ports through data bus buffers. Medes cf Operation 4) Bit set/ Reset (BSR) Mede -& pales ee x) Only port C operated fp Mis mode 3) We can transfer legic't’ or legic ‘0’ en any one pin of Rite - Without changing the status of siest of the pins to de the operation wwe have to transfer & bit control word 19 belew format 07 De Os Py pa Os Oi _ oe fo [ xT Tx E T oF the Value ef De if 0% oan Port ¢ pin selection is transferred into poo Peo selecl&d pest ¢ pid if 1 Tlo mode coL— PCL iti Gey Exp> Reset Posty pio of 8255 having port A address EocoH: sel?> aime ou = OGH . sk a oo 9 . Reset means O soe, PCy pi 6000H — festA address 6oo1n — fost B . 6co2zH —— Porc * nee vegisley address Program - Mvr A, OEH STA €0O3H HLTControl word for Parallel Tlo mode -2 kK Group A —__>1 <& Greup 8 —>1 D: | De \ Ds | Pe on Di] 00 ut {Se > Port Crowen 0 = BSRmade 42 cle Os 0lP mode Selection. L—> fost 8 of Pont A 2clp 00- made Oo o-olp OL - mode t > mode of 1x - mode 2 post B O= mode 0 1= mode it Port C upper, 12tle o- olp > Port A is tlp 0=0lP4 2) Parallel L/o Mode -3 ‘In this mede @ bit paraliel dato cwill be =e = tronsferred blur zip and Zo device there are 3 types of modes il) Modeo ( Simple Input [output )~ #) There & no handshaking ee 2) All ports. can be used *) Outputs ane Latched ©) Input ports ave not latched Port c Can eithes be used as & bit post on UbS Upper /iower parts can eperate endepenctently ll) Mede £ ( strobedt Inpur/output) - In this mode handshaking Signals ave exchanged between MPL (eR) and external peripheral before actual data transfer. main features Of this mede included %) Port A and Port 8 actas § bit parallel To ports. they con be used elthes as cnput om eutput port- *) Each port cses 3 lines of portC as handshake signals. *) Intemupt logic 15 supported %*) Input and cutput data will be latched *) PCs, PCy 4 PEs generates handshakiig signal fpr Port a PCo,PCy , PCa generates handshaking fox Post B cohen tach pert Used as tnput port ‘ : hen both * PCs, pce, PCy generates handshaking Segnol fer PA perruwd Plo, PCs, PCa, generedtes handshaking Cagrag fev PB [as eae 8255A MODE 1: INPUT CONFIG pe STB PORT A INPUT] Ter (Buller full) (NTR Interrupt request) Data strobed Dataread by into port microprocessor Timing Drageomvy 8255A MODE 1: OUTPUT CONFIG PORT A OUTPUT Data sent Data removed topo from port Timing Diagrom This mode IS used when Lle) -8 ——~———" data has to be transferred blur two computers (ox processovs) o¥ data stovage derfces Such ab pen daive or hard dist. %) Only portA can operate 1h mode2 #) Pls —PC% will provide handshaking signal fos port A , #) Pert B Can operate Ih mode-O oF mode-1. When post B operate 10 snede-4 , PCO toPCg will provide handshaking signal. for Port B Control word for mode-2 i) When Post B 1s medeo TILT XTX XTOTT 1 pte-re; | bteue Ports o=ele moda -O ii) Wlhen Port B 15 mode-1 xT to 221 XTX Port mode - 1.Control word fox mode —4 é eae eee a) When PA and PB OS input post =: ESCAESESCORMES Es > net defined aa they provid hands hdieing cic posta gl mode - 4 > Port B input eae ——> port Bo mode- 1 Post mode- 4 + PCe, PCy as tnput(s) or as Lnpat output (0) b) When PA anc PB as outpet port -2 —— porta 16 mede- 4 — Fort A as output isi @ leet [tLe x ° —> Fort B ad output Port B mode-4 PL4 > Pls ad input( 4) or outpar (©) Exp> Detine Peet Aas tnpat powk 18 mode o, Port B as Sutpat 1h rede £ aod poxke Upper a8 Lapet - goss adaress starts from 6oH. TH |reas [naan] pa [Pou] Me] ee] Pe / (ealealeal t lox =,3¢ Cif xo) 7 * Ls otwill provide hondshakig for pest B Pregrom— mvt A,9cH our 63H *) 6O— Feat A aactdrese 6l — FetkB on 62— foto 43a— CwRegrcler ada essProgrammable Intesval Timer ( 8254]63) > SS Tt fs not possible to generate an arbitrary time del i i f n itrary tim lay precisely using delay voutines- o a Intel's programmable counter) timer ( 8254) Is used togenerale precise time delays %®) When S284 IS used for timing and delay qenecation > the micsoprecesso becomes free fromthe task related tothe counting poocess and can execute PIOgFOM Ip Memory. This minimises the software overhead on the processor - Architectuye -* crate | Counter ne a suey Replat eee) Garten _ ovT a Block diagram of 6254/<3 FQ: Pin Aiagracn i: ntecs + %) B2rs4|shas 3 lodependent 16 bit cour *) eo have max count vate ot 1oMHe tere %) These 3 countess can be Contsolled by 3 command word reg! a 26) All Pnese counters are Udentical 5 presettable to opescte either in BCD or in hexadecimal mode - 3 down counters ,able 4) Arand Ao are used to select the counter Ay Ao oO counter © Ce counten. 1 1 00 counter 2 1 L Control word operation== S254 WD Mon. cloum freq 18 26MHZ 9) max: clown Frey BMAg yf) O0es net have read back command A’) g+ has read back Command # Read back Commanct allows the uses to chet he count Value, current Stafes of ovt pin ond programmed mede - %) Read and waite of the same %) Reed and waite of fhe same Gunter can be lteleaved (mixed) counter Con not be jsterleared (mixed) CLIK-t Clock Isput 1% the timing source for each of the inteanal county This isput 1s often connected to the PCLK Signa from the ‘microprocessor System. BUS Conhoiienr - 2k) 9+ 1S also used to decsement count - GATE-% Qt is Used to enable He Counter When Gate = 4, counter will get enabled out —t ulse output pi of Hoe Counter - eur: |p P Control Word Register. -5 | sca | Sco RLt|RLO ma] mi Mo &cD —— ~ L,. wy i Z aa - decimel Counteh selechen ener ec ees ta scr os count0 ‘Y= Bep county a ° me 1 counts! © 0 O— mode O 4 0 Counter 2 0 O4— mode L yo XK (Read bak © 4 O-— mode 2 Command) O11 mode 3 1 oo — mode 4 tol] mode 5 4 to- % Lair x Read | Load (tonite) Bit definition RLo ° Rp Fe e Latch Counter for "oN THE FLY" steading C Counter Latch Cornma L —— Rood] wrile jeast Significant byte only © = Read | wAute Mask &xgnificant byte only 1 — Reea/watke LSB frst then MSB. Kr ooMode 2 € Rate Generator) eee ee ee ®) St IS Olso Known ag divide by N counter. % If N Is loaded as the count Value, Hren after (N~L) cycles , the oudput betomes low for one clock cycle ® The count Is leaded again and the olp remains high for(N-1) cycles. ® It Gare pulse goes low , the counter stoxts counting from initial Value oe LDA Eee eee ‘starts Coubting « : — Mode 3( squore Wave Generator) =e Of ~Gperattion Similan to rhe mode 2 P nb pues Ht vena low ond fo *) *) it Count value Nf even then for 2 \cex ie remains high: : . ae fos (htt) pulses output remains high Gs) * 4 nee er ylces cuspat remains loud (0). ana ty (Nat) P = SUT ETE ae : . 4 — 4 i : . OUT WRK our10 (8 loaded Ihbetween the operation 3 3 What happen if another cover volue Mede 4 ( Programmable Monoshet) -s aie ornare 3) In this mode $254 Can used as monostoble ™ # Gate input is used as tagger input #) OvT (on output) Femains high till the leeding of count and trigger i/p y Apter appling triggenLon rhe +¥e ecge ot a) , the ole goes low aad cremains low till the count reaches AED + ¥) So low state of ole depends 09 Hhe count int value, Hen cb will oof distusb He opermba e fs applied ot the GATE tesminal- ultivibrator: value. ¥) If we load a new cou till a new tmgger pule cLK [7] re Aly Trigger Ue# Gare Sperating, | Modes of 8254 -3 0 fdcceiinetiied aad i) Mode o Mode 0-3 (Intenupt on terminal Count) #) output 18 initially Low after setting He mode #) output remains low even after loading Hye count value. %*) on the next tolling edge of cleck C apter loading count valve), the counter starts decremenhng He Count value. at tis time GATE pulse should be + ( Gate = +) g elk SU SAA WR Neng a earn ee : _ Gate count > count =4 OUT ee whent Countso is loaded into counter #) Attar leading and GaTe=4 , the counter stots decrementing from 374 clouk pulse - ® Apter 4 clock cycles (4th, 5h, ehh and 7) y the output will switch from © 6 4 which is known as interrupt on feaminal count: hat happen i$ Gate pulse goes low inbetween the operationy x x _. - eh gh nahn out : a ee ee ee : e—_—<$+_—_—_- f eme SE a ' . 7 1 ’ 1 OvT 7 :Mode 4 ( Sopt wore tnggered strobe) ~e %) Allows Hhe counter to produce q_ single pulse at Phe output. 38) if SK leaded hen cur will be high for *N? cycles and hen low for one clock cycle at He end- joaded again. 4) The cycle does not Fepeat untill the counter. 16 I . 46) Counter starts counttag after first falling edge ef cleck and si'sing edge. of write Signet - ck I A ae ert [ood Hye count value and stants Counting ig ig 2 we 1 fo. Fo? Mede S C Hardware triggered mede) ~F ete SO PON ONG I % This mede 1B used to generate a delayed strobe cohen a trigges pulse at the GATE pin by the excteinal hardware. 3) counting begins when GATE pulse 1% triggered from Low te HIGH: here Is cuk SLL ATE AAA ce sphsincomiy FT | Gate (tagge) “ . ae , b entenal device OvT — Gate Caan - 3823% DMA Controller ——* x— DMA stonds foy Direck Memory Access. Data transfer blo Lo and memory tokes place by 2 ways 1) Through iAshuctions ( Software mode) —8 Im pis mode of transfer transfer reteis very lew. rE Bt is net suited for bulk data tvonsfer 2) Through External Havdiwave (Oma) When a peripheral wonts to exchange heavy omount of dats with memory , ‘Ub tekes the helpof OMA conlreiien . the OMA controler transfers Fhe contrel ef buses from cpu to external priphers! Zo device: external peripheral devices like Hard disc, Sound cards , graphic cards ctc uses OMA Controller for dats trensfer Block Ciagrom and signals -! Deen SR nama Bus DMA Request © seit ey Data bus { nee DMA ACKNOWLEDGED eee “4 On : neset — pat sear me © Ao ae eure PORT 7 HPS AS) = To Rol devices a Sar fone haa 45<— A008 | PORE? pane READY — >} 190 yn KS spe | ah foros ways wo | som 1 = ose «| | pe t Prony CEBP) wank < resstvee Fig Bleck diggrom of 823% ) 23% Con tronsfer 64kB dats at a time iG odes — ff OMA ead x) St opestes 19 Sm £m at #OMA Voufy #) 823% hoo Bbit dete bud. 4) FOR , TOO ave used for Tlo eperation and MEMK ,MEMY signals are Uard for Memory sovate.) spuatins.* 8234 hannels hao a c el che to CH3.. each chenne] ¢ Connected vith only one pempheral device jan be *) 8234 has Priority sesolver unit Init to Hesolve the ‘ chonreL 0 to chonnel3. " eee eee ¥%) Each chonnel has ‘ a5 16 bIt Current Addvess ‘eld le bik current wore Count RegisleA CCWR)- gil _CcAR) and CAR holds tre storting address ef memo OM cohere eee eee af om 0: of Byles that hae jo be transferred in DMA ope " CWC holds the 1 3) 223% Can perform Memory To Memorp » Memory to tlo + tio to memory transfer: *) 823F ppersites on MHz to SMHE 4) cascacting of 2234 Gan be Used fo lherense the number of clerrices *) 2 M86% of count Regislear Cer) defines the typeot Oma operechon Le bit [Seo Tool daloe[e: eee] — Fa Bits for Count val © © Oma Verity Oo 4 OMA Write LO oma read 4 4 legal (x) 2) Nowmolly one OMA Cycle comsumes 4 clock cycles (S41 t0 $4) but B23at provides compressed timing to improve thsoughpet of He tS. ce compvessed tiraing 5 pot valid during memory to memory +0: Function of Impostant Signals —* naeeee re Active Hig Sina B® Signal generated by externod te dewice 8S Fa] 3) DRQ= L meons external peripherot wools to Control of Syplém bused CDatO , address + CORRQO tO DRa3) conte) bus). | achive HIGH SisroP * DMA Acknowledge ( DACK)— ¥) if, goSs] Boke Meleases the conlval of, buses then 823% genesie PACK sign DAK [zIe| fo dicate zlo denice hot pnp, peamissia we qrentes: Coacko pAcKS) When OACK= L , thot means external t/o device can access MeMeTY without up BpU- Hold Request CHRQ) —: we) Active HIGH cignap - 3K) HRQ@= 4 Indicates Up tat any extern? Pele 2237 device usonts Me Control + Syslém Duce oma Request CORE)Hold Acknowledge ment ( HLDA) — ise # Active HIGH signal 3 When HLDA= 4 , microprocessor tells 823% that he & steady to transfer the Contre! of Syslém uans « Fermina| Count (Te) =! When the conte] word cont Cewe) valu # e exhousléd then 823% makes Te pid HIGH To21 indicates Mp that Complete detts byles han been +tronsferted End of Process CEOP )-* % Active Low signal - C Bidirectional ) 2) EOp20 means pmaA transfer process has been ended: © When up wonts to Stop the OMA process, it mokes EOP pis Low. Q) When BABF sieaches or exhousléd He coum’ ZoP pid active low + Valu , it makes rol Ay AY TS of 8234 aS pe ata Ant Callinee) ote cecent generate chip gelect logte for 8237 # Yo © selecléd when Aq As Ae are 000 4) for Eo te at loge O 2 Ay =O a Aq Ae AS At are alocys O000H ® Ag to Ao lines Ore ured to select different Regis)ers of S234. Aq Ac As 44 As Ar AAO o 0 ee 2060 0 = OCH CHO MAR 0% CAR ooo Lt oLH CHO CWE chip Select oo te o2H = CHL CAR ook t OSH cHS CWS ot) oF 2 cee cleor mask register 4h 4 F OFH Alt mask veqiste #) CWC = Current word count aw #) CAR = Current Address regutes, also Kaown ob Memory Address reyls'if Reset= 1, then b Register CCR pas C CCR) pu these registers will get cleared - Request Register Temporary Regi’sl@ 8234 will enter into slave mode if Reset= 4 Reset -= Ready -+ (REAOY) 3) Active HIGH Signal generated oy YP #) Used when 8237 operates lb Maoter mode- 4) Master 823¢ adds woit states th oma cycle if READY= O AEN-I( Address Enable) When AEN= 1, Higher order address bus (Ag- Ais) will be available - ADSTB -% C Address Strobe) This signal 1S used to contol Latching of upper address byte (Ag-Ris) - Ao- AisOma Data Tronsfer Modes ; a >=. 2 4) Single Transfer Mode = 5k) 823% tronsfers only one byte (Bits) ih this mode 24) After each transfer, word count register Oil! get Current address veqister cil get incremented or clecre mented ) After tronsferning one byfe , the 9237 disables HRQ and enters ine idle state or slave mode. gt is also called os “cycle srealing mode” » ut disables He corresponding channel decremented and 4) When Tc f reached 2) Burst oy Block Tronsfer Mode -! *) All bytes are transfered continuously + 4 HRQ= Active HIGH during all the DMA oO @ vy word Count register C yelling from 00 tO FFIO% EOP any external medium - OREQ must be held active aorill RES ° ones Sar oma fs acxnosletged 3) Demond Transfer Mode ee OACK OMA REB IS disabes: — wee * peration untill TC = © Back becomes active wed %& contsolled by zlo device - #) The number of bytes to be teansfe peration by *®) The Ilo device C0 terminate He | -5 activating gop signal Cre Eop=0) > Disabled DREO Cte DREg®=0) \& disabled), he 8237 stores ne intermediale *®) When DRQ=1 ( DREG Current Count and address value of Count and Memory address % og isl respect ivaly - 4) EOP’ signal & used when outoinitialigahon 1S Enobled - +) DREG i used when auto Inihaligation 1S dhisabled - 4) Cascade Mode -* Coe eee 4© ‘This mode fs Used to cascade ‘move thon © the number of channels. 2) Fig below (1 next page) shows the connections of meoter and Slave DMA contreliers. 3) In Cootedes! mede 823 activates only HRQ and DACK Signals - ne 823% to increqce24 Level a ra uP eal <—_ ——ee HOLD HRG on ———7]4-08 | HLOA HHLDA | | | pre PRO onsf on 3 HEDA Master S237 3) CHO and CH3 are 19 Cootaded ede Slave $237 Figs Capcading of 823% e234 openating Mestet our. value of current add re L) Autoinitiolization Mede-3 In this mede yy word count Cewe) ee are automatically sectored from base addnre regisla and ane wor count rrogisl® + The values are -eestored only cohen Heve (3 on Bop signa] gets activated of Her 1S TC- ©) Fora Auteinitiolization psepe> ‘mode should be Selected 4heough mode wegisler CMR). 2) Priovity Mode 623at operates th to pevowity medes Rotating Priovity 36) Chonne| hich 1S Cuvrently active hap highest poiostty: abe Sewice it will get lewest priovity . fr N cn CHL x cone Somce» jst 2nd Mot Fixed Priostty #) CHO has highest and cH3 hao Lowest pmowity currenth 9 2¥ 3 os hie ra ee 3 8 . © poonky and 3 a 3 being Seswited -. : OMA cycle has 4 clock pulses 1 3) Normal Timing Made “i =n y P me = = 4) In normal timing made IOR and MEMR signals ore ochvated during 374 clock cycle and ah clock cycle - ® TOW ond MEM will get activated during + dook cycle. T1051) T2(S2) 13 (54) Ty (54) LELFLE LIL *) S for stale (HR) Write 31 tF # Aclock cycles Compre ssed Timing Mode-+ In order to achieve greater, 4) oer ee een thwoogh put , 8237 can Compress the OMA cycle to 2 dock pulses - 3%) In compressed trening mode only S, and Sq. needed +o Complefe one oma cycle « S284 Sp 54 rerty | = 7 | RO Vt we #2 leek cycles 5) Extended vite mode -% 3k) Not Used 16 Compressed timing made. #) Nosmally used for slower clevices y BA by activating the ussite Senal CMEMW, TOW ) 1h 3™4 clock eycle C $a) - Si Sn S83 Sy LLL | mw | I WR ——y | Che write signal fs actimed ward dock cycle, denice usil] get move time +o write the data -Progvammoble Intertupt Controlley (Pic) 8259 /ae) x x *) 9259 IC f e@ programmable IC used to expond he intersuphs of 8085. *) One 8259 Con accept $ Intersupt requests ond allow one byone through INTR pin- 3) Cascading canbe used to expand the interrupts upto 64. %) 8259 manages the fntersupts according to the instructions . writen into (ts control register #) The peiovities of interrupts are programmable . How 8259 Works? ee A 8 First 8259 18 progrommed by sending Toitialigation Gmmor words C TCWS) and operational Command words (OCW Ss). These words will isferm $25q about © Type of interrupk Clevel triggered or Gage triggered) *®) Type of processor (o8c/ 26) %*) Call address and its ibtewal (4 or 3) #) Masking of interrupt 3 Priovity of linterrupr *) Type of End of Intensupt ( cot) once 9259 iS programmed with these Command worsls Lt becomes Teady for accepting (ntesrupr Stgrals Steps of Servicing -% eT A _ *) First 8259 Tecelves te iotessupt and et will check wheher_ creceived istersupt 1S mapked oY Unmasked: #0) 9t also Checks the priowity . 4) Th Here & po pending fnterrupt fom last stequest and Current srequest han highest priovity 8259 sends Signa) on INTR pla . %) T4 processor & ready fo accept Me vequsst 2+ ends & INTA Clow) pulses one by one- TRTA ('0' fors clock pulses)FuncHonal Block diagram ~2 25q hap ¢ functional blocs 2 FuncHonal Bleck diogt) gwar send INT signal to INTR pin of 808s + 4) When tne processor occepted Hhe request, BOBS £erdo 3 INTA (lees) one by one ie Tie — TZ TA yt ts lL NTA a i ~ es90~C~C<“‘<=~*wSY ual ““GpperwyTe of call addwess 1) Contre! loge - 1 lower byre Of Call address once processes receives CALL opcode and address » tr saves He Current content of PC 18 STACK and Start executing the TSK DATA ote CN) hus BUFFER INTERRUPT MASK REG (WR) INTERNAL BUS 2) Sbit data bus buffer tO %*) Send Control worel foorn Goes to Intessupk contsoller - 34) Read the status of B8S9 (by 8085) #) send datq B) Read write logic -sx)The BOBS uses RD, WOR and Ae to perform Sead wwe jon + *®) CS is used To gelecr 8259 TC- &) Interrupt Request Regisl& (IRR) ~EA)Ot is an 6 bit regisl® ye) Qt bas & lines CERO to Rt) *) Gf any of the line & high , t+ will get stored lithe Cowmesponeling bit of yesh Ne -e . 2 5) Interrupt Maok Regist CIMR)- gt 1S on wbit veglat ushich ee A Pe ee : ° e Contains isformahen about macking of any fntewmupt Ifne. This regisler gets datz trough ocWw1. 6) In Service Register (ISR)-2 gf keeps treck of ewhich interrupt fis ee Cupnanhly being saviced. 3) Priovity Resolver -g This block sesolves the psiovity ff Phere ave Re ee d ‘more Than one InFexupt at a time. 8) Cascade buffer /comparatyy -2 9t fs used when 8259 fs used 1 ~ _aer eer ‘master clave sede ( more than one gosg rc {5 conneclad to 0S).Initialize command words (rew*) we Toitialige Command words Lazcw ; ILcW Commands ave used to load Fhe inteanal conbrel vegisters of £259 to speaty the anes of cpenachon of B254- Hhere ane 4 command words configuration *) Tews ® Tow2 (stores details regancuing intereupt vector address ) *) Icw3 ( Used i) Masts /slove mode) *) ICW4 ( Used 16 8088/86) Hhese command coords are used to inihalize he S259 IC only: Operation command words Cocws) - eae ee , 7 Once he 8269 1s initialized , rhea 2+ becomes ready to seceive he intersupts : rhe 8269 acceprs rhe varercupt Request on its Own way called Gs mode of opashon- nese medes of operation can be clepred by 3 Command words #) OCWL — ( Used to access the content of Mask vregi'cles ) #) oc W2 selechive maskhg of idtesrupts se) cca . 4 Cused te select the priority schemes) Cat permits the Heading of content of ISK of IKK fisough Se¢t ware) 3) ICWs and LCW2 are Cumpolsacy Command words. iL A,z0 and D4 Ll, ten conte! word 13 recognized as ICWs- it contains . %) Edge/ level taggen9 #) sitgle/ Cascade mode %) Cal) address toterval ) Whethr Sean gs needed om not ICw4 Iewt - Ao itL , Cw4 needed Ifo’, TcWa met needa ——— used In Go@S only #®) Az toAs bits of intestupt Vector adaress 4) Dodt Care th BoR6 1 = Single © = Gascaded mode Address Infexval Ts 4.2 interval of 4 as Leas 0 = wtesval of @ bytes a9eng 3) for Bogs ,ADI =L sa, then srs are 4 byte apart (0200, 0204 ete)- if Aor<0 5 hen TSR* ave @ byte apart (0200, 0208 etc)ECGW2% if ays, then Conhel word I vecegnized as rena?" *) OF stores details oF Iotersupt vector addresses . Ao Dy De os D4 03 P2 OI Do CE] Gee TLS LAT AT 2 ont apes Sg OO ere lines of processor” 28) For B0RS Syslem All the bits ave filled by Aig “Ag of Totewcupt vector address - 3) For S086 Te = Ta ave the 5 mest Significant bits of Intessupt type by te of Beat Alo- Ag defines the type of ioteswupt for xp IRo = 000 bec oma IR, = OOL ete. : L These bits ave Onginally held at 000 Ciro). tf ony other | Wtertupr fs Here the 8254 automatically add rhe number to boat Co vralur of IRo to get the sight isterrupt: X) Icw2 isdicalés & bit vectos addwess 14 case ot S086 and higher weyte ef ISR address 14 case of PORK When SNaL bit of ICW1 =0 Hat means £259 15 16 Cascade amode ( Mastes/ Slave mode) - # TENS f the stead only Command coord when S259 openales 10 cascaded nede- %) rows holds the & bit address of Slave. ICcw3, legen Tasos ce (sh a co petsh ce MS = eis lew, ri the Bbit Slave vegisl® will be cet bit wise to'L for each slave 1h the Syslin- Sp represents IRo Ao b7 De Ds Py D3 Da 1 Do aa (2) [s]selss Sq [8 [s-[s,[=| és veprecents Ry seein if Syed then IRn has a slave © then IRq does mot have slave Exp- let IcWZ= 00000010 ‘ - L» IRL hada slave cane 2°: In slave mode C5P=0 ominsuffer mode M/s = 0 ,BUF=4 18 TOw4) . Ao = 1. (eleTe ° © [2,[z0,J 16] # Slave 4 on IRq Will have —_— ICws = 0000 of 0d (04H) ose — =Ro (Slave 4) s'ti— IRF (Slave 8)ICW4 -2 4 a x if req bit 6 ICWIs 4, then only Tewq will ee % Gt IS used only with Bosé/ Bose - © | © |o |senm| BUF [mis AGOT| mPM [5 02 S085 mode special Fully Nested come See S selected Popes if4 then Automatic End of y - Intersupt mode it enabled M|Z=0 then BaSq Isa Slave 4 then ©2859 189 Maoley »#) ifauF=0, MIS ts Neglecléa « ee ee 15 selected. lo Fhe wufferrd mode sP/EN actas enable and master, / slave | determined using MS bit of ICW4- OcWi ~*~ 9tis used fov yO Access the Content of monk vegest 36 Selective masking of intessupt inputs. Ao 1 [eng [ me] Me] my [ma [Me [on mo | if bit= 2 sthen Mask Set © 5 then Mask Reset ate let we want to mank ZR2 ythen Ma bik shouldbe 4 6o ocwi = 0000 OL00 =04H “8 Sel jowitie inte’ FS. Ochi2 <2 Used to Select priosities of intesvup T Bleeder eT) J Level of tntersuph End of 000 Z£RO Intessupt ool Ri specific. Rotation oO 10 tR2 Automatic Rotation Of ERB 1 0G 3Ry {or Rs 10 zRE 4 IR7R su €0L o ° ° 4 —= Non specific EOL Command (19 Fully Nested) ° :n— speci fe E0L command 1 ° 1 — Rotate on non specific GOL command 1 ° oO — Rotate 4 Automatic BOT mede (set) ° ° 5 — Rotate 19 Automatic BOr C clear) a L 1 —-Retate on specift EOL command e — set priority command (L2~Lo we used) * ‘ S : 8 ¢ 19 Hhis mode 6 4, Oo — No operation OCW3.- Gris used to stead the content of TSR om LRREhroUgh Softion Ao cy Ds De Os D2 Di Do L\o jest] smn] 0 | 4 ta ak ats] ——= oO oO V re ° Reset spedoL —> 1 0 1 0 — Read. IRR on next Mask, RB pulse Set special L iran! ae 4 oft Read. Wm ISR o7 next RB pulse ESsmMm- Enable spettat Maske mode P= 4 Poll command smi spesiak mask mode - © 0 poll CommandPriovity Modes at eee L) Fully Nested Mode -% )In this mode ail Intersupr Requests C ERS) a eee are arranged from highest to lowest ® Any IR canbe assigned the highest priovity Let IR has been assigned the highes priovity then IR, IR, IR2 Re TRe IRs TRe IR7 4 Ss 6 + ° L 2 3 t Lowest Highest Priovity Priority *) TE we hove not assigned the highest priority to ony TR then by default TRo will have the highest priority end IRz cil) hove the lowest priority 2) Automatic Rotation Mode-3 In this mode an IR being served, seceives the lowest privity. let IRy has Just been served , then Ike IR, IR, IRz IRy IRe TRe TIR7 s 6 t ° 4 2 3 4 Lowest Highest priovity priority 3) Specific Rotation Mode -3 #) Similar to automatic rotation mode ——— exeept thot He user Can select Ony ZR for the lowest priowity: thus fixing all other priosthes. Enp of Interrupt 1) Non= specifre EOL -t When this command iS sent to 8259, + rresets the highest priovity TsR bit. 2) specific EOL -2 This commond specifies which 1SR bit to reset. ae 3) Automatic EOL -2 %) No command required #) puving third (3°) ENTA pulse | ISR bit (8 reset.