TPS2062-1

D−8 DGN−8 D−16

TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009

CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES

1FEATURES TPS2065-1 TPS2062-1/TPS2066-1
• Output Discharge Function DGN PACKAGE DAND DGN PACKAGE
(TOPVIEW) (TOPVIEW)
• 70-mΩ High-Side MOSFET
• 1-A Continuous Current
• Thermal and Short-Circuit Protection
• Accurate Current Limit
(1.1 A min, 1.9 A max)
DESCRIPTION
• Operating Range: 2.7 V to 5.5 V
• 0.6-ms Typical Rise Time The TPS206x-1 power-distribution switches are
intended for applications where heavy capacitive
• Undervoltage Lockout loads and short-circuits are likely to be encountered.
• Deglitched Fault Report (OC) This device incorporates 70-mΩ N-channel MOSFET
• No OC Glitch During Power Up power switches for power-distribution systems that
require multiple power switches in a single package.
• 1-A Maximum Standby Supply Current Each switch is controlled by a logic enable input.
• Ambient Temperature Range: -40°C to 85°C Gate drive is provided by an internal charge pump
• ESD Protection designed to control the power-switch rise times and
fall times to minimize current surges during switching.
The charge pump requires no external components
APPLICATIONS and allows operation from supplies as low as 2.7 V.
• Heavy Capacitive Loads
• Short-Circuit Protections These switches provide a discharge function that
provides a controlled discharge of the output voltage
stored on the output capacitor.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1.5 A
typically.

GENERAL SWITCH CATALOG

TPS2042B 500 mA
33 mΩ, single TPS201xA 0.2 A − 2 A 80 mΩ, dual TPS2052B 500 mA 80 mΩ, dual 80 mΩ, triple 80 mΩ, quad 80 mΩ, quad
TPS202x 0.2 A − 2 A TPS2046 250 mA
TPS203x 0.2 A − 2 A TPS2056 250 mA
TPS2062 1A
TPS2066 1A
TPS2060 1.5 A
TPS2080 500 mA
TPS2064 1.5 A
TPS2081 500 mA TPS2043B 500 mA
80 mΩ, single TPS2014 600 mA 260 mΩ TPS2100/1 TPS2082 500 mA TPS2053B 500 mA TPS2085 500 mA
TPS2044B 500 mA
TPS2015 1A IN1 500 mA TPS2090 250 mA TPS2047 250 mA TPS2086 500 mA
IN1 TPS2054B 500 mA
TPS2041B 500 mA IN2 10 mA TPS2091 250 mA TPS2057 250 mA TPS2087 500 mA
OUT TPS2048 250 mA
TPS2051B 500 mA IN2 TPS2092 250 mA TPS2095 250 mA
TPS2102/3/4/5 TPS2058 250 mA
TPS2045 250 mA 1.3 Ω IN1 500 mA TPS2096 250 mA
TPS2055 250 mA IN2 100 mA TPS2097 250 mA
TPS2061 1A
TPS2065 1A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains Copyright © 2007–2009, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTION AND ORDERING INFORMATION (1)

RECOMMENDED TYPICAL PACKAGED
MAXIMUM SHORT-CIRCUIT NUMBER OF DEVICES (2)
TA ENABLE
CONTINUOUS CURRENT LIMIT SWITCHES
LOAD CURRENT AT 25°C MSOP (DGN) SOIC(D)
Active high Single TPS2065DGN-1
–40°C to 85°C Active low 1A 1.5 A TPS2062D-1
Dual
Active high TPS2066DGN-1

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2062-1DR).

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted (1)
UNIT
Input voltage range, VI(IN) (2) –0.3 V to 6 V
Output voltage range, VO(OUT) (2), VO(OUTx) -0.3 V to 6 V
Input voltage range, VI(EN), VI(EN), VI(ENx), VI(ENx) –0.3 V to 6 V
Voltage range, VI(OC), VI(OCx) –0.3 V to 6 V
Continuous output current, IO(OUT), IO(OUTx) Internally limited
Continuous total power dissipation See Dissipation Rating Table
Operating virtual junction temperature range, TJ -40°C to 125°C
Storage temperature range, Tstg –65°C to 150°C
Human body model MIL-STD-883C 2 kV
Electrostatic discharge (ESD) protection
Charge device model (CDM) 500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.

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DISSIPATING RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
D-8 585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW
DGN-8 1712.3 mW 17.123 mW/°C 941.78 mW 684.33 mW

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
Input voltage, VI(IN) 2.7 5.5 V
Input voltage, VI(EN), VI(EN), VI(ENx), VI(ENx) 0 5.5 V
Continuous output current, IO(OUT), IO(OUTx) 0 1 A
Steady state current through discharge. Device disabled, measured through output pin(s) 8 mA
Operating virtual junction temperature, TJ -40 125 °C

ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 1 A, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
POWER SWITCH
Static drain-source on-state resistance,
VI(IN) = 5 V or 3.3 V, IO = 1 A, –40°C ≤ TJ ≤ 125°C 70 135 mΩ
5-V operation and 3.3-V operation
rDS(on)
Static drain-source on-state resistance,
VI(IN) = 2.7 V, IO = 1 A, -40°C ≤ TJ ≤ 125°C 75 150 mΩ
2.7-V operation (2)
VI(IN) = 5.5 V 0.6 1.5
tr (2) Rise time, output
VI(IN) = 2.7 V 0.4 1
CL = 1 µF, RL = 5 Ω, TJ = 25°C ms
VI(IN) = 5.5 V 0.05 0.5
tf (2) Fall time, output
VI(IN) = 2.7 V 0.05 0.5
ENABLE INPUT EN OR EN
VIH High-level input voltage 2.7 V ≤ VI(IN) ≤5.5 V 2
V
VIL Low-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 0.8
II Input current VI(ENx) = 0 V or 5.5 V, VI(ENx) = 0 V or 5.5 V -0.5 0.5 µA
ton (3)
Turnon time CL = 100 µF, RL = 5 Ω 3
ms
toff (3) Turnoff time CL = 100 µF, RL = 5 Ω 10
CURRENT LIMIT

VI(IN) = 5 V, OUT connected to GND, TJ = 25°C 1.1 1.5 1.9

IOS Short-circuit output current A
device enabled into short-circuit -40°C ≤ TJ ≤ 125°C 1.1 1.5 2.1
IOC_TRIP (3) Overcurrent trip threshold VI(IN) = 5 V, current ramp (≤ 100 A/s) on OUT 2.4 3 A
SUPPLY CURRENT (TPS2065-1)

No load on OUT, VI(ENx) = 5.5 V, TJ = 25°C 0.5 1

Supply current, low-level output µA
or VI(ENx) = 0 V -40°C ≤ TJ ≤ 125°C 0.5 10

No load on OUT, VI(ENx) = 0 V, TJ = 25°C 43 60

Supply current, high-level output µA
or VI(ENx) = 5.5 V -40°C ≤ TJ ≤ 125°C 43 70
Reverse leakage current VI(OUTx) = 5.5 V, IN = ground (3) TJ = 25°C 0 µA
SUPPLY CURRENT (TPS2062-1, TPS2066-1)

No load on OUT, VI(ENx) = 5.5 V, TJ = 25°C 0.5 1

Supply current, low-level output µA
or VI(ENx) = 0 V -40°C ≤ TJ ≤ 125°C 0.5 20

No load on OUT, VI(ENx) = 0 V, TJ = 25°C 50 70

Supply current, high-level output µA
or VI(ENx) = 5.5 V -40°C ≤ TJ ≤ 125°C 50 90
Reverse leakage current VI(OUTx) = 5.5 V, IN = ground (3) TJ = 25°C 0.2 µA

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2) Not tested in production, specified by design.
(3) Not tested in production, specified by design.

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ELECTRICAL CHARACTERISTICS (continued)

over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 1 A, VI(/ENx) = 0 V, or VI(ENx) = 5.5 V (unless
otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN 2 2.5 V
Hysteresis, IN TJ = 25°C 75 mV
OVERCURRENT OC1 and OC2
Output low voltage, VOL(OCx) IO(OCx) = 5 mA 0.4 V
Off-state current (4) VO(OCx) = 5 V or 3.3 V 1 µA
OC deglitch (4) OCx assertion or deassertion 4 8 15 ms
Discharge resistance VCC = 5 V, disabled, IO = 1 mA 100 Ω
THERMAL SHUTDOWN (5)
Thermal shutdown threshold (4) 135 °C
Recovery from thermal shutdown (4) 125 °C
Hysteresis (4) 10 °C

(4) Not tested in production, specified by design.

(5) The thermal shutdown only reacts under overcurrent conditions.

DEVICE INFORMATION

Pin Functions
PIN
I/O DESCRIPTION
NAME TPS2065-1 TPS2062-1 TPS2066-1
EN 4 – – I Enable input, logic high turns on power switch
EN1 – 3 – I Enable input, logic low turns on channel 1
EN2 – 4 – I Enable input, logic high turns on channel 2
EN1 – – 3 I Enable input, logic high turns on channel 1
EN2 – – 4 I Enable input, logic high turns on channel 2
GND 1 1 1 Ground connection
IN 2, 3 2 2 I Input voltage; connect a 0.1 µF or greater ceramic capacitor from IN to GND
as close to the IC as possible
OC 5 – – O Active-low open-drain output, asserted during over-current
OC1 – 8 8 O Active-low open-drain output, asserted during over-current for channel 1
OC2 5 5 O Active-low open-drain output, asserted during over-current for channel 2
OUT 6, 7, 8 – – O Power-switch output
OUT1 – 7 7 O Power-switch output for channel 1
OUT2 – 6 6 O Power-switch output for channel 2

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FUNCTIONAL BLOCK DIAGRAM (TPS2065-1)

(See Note A)
IN CS OUT

Charge
Pump EN Discharge
Control
Current
EN Driver
Limit

OC
UVLO

Thermal Deglitch
GND Sense

Note A: Current sense

FUNCTIONAL BLOCK DIAGRAM (TPS2062-1 and TPS2066-1)

FUNCTIONAL BLOCK DIAGRAM (TPS2062-1 and TPS2066-1)

OC1

GND Thermal
Deglitch
Sense

EN1
(See Note B)
Current
Driver
Limit

Charge
Pump
(See Note A)
CS OUT1

UVLO
EN Discharge
Control

(See Note A)
IN CS OUT2

Charge
Pump
EN Discharge
Current Control
Driver
Limit

EN2 OC2
(See Note B)

Thermal Deglitch
Sense
Note A: Current sense
Note B: Active low (ENx) for TPS2062. Active high (ENx) for TPS2066

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PARAMETER MEASUREMENT INFORMATION

OUT

tr tf
RL CL
VO(OUT) 90% 90%
10% 10%
TEST CIRCUIT

VI(EN) 50% 50% VI(EN) 50% 50%

ton toff ton toff

VO(OUT) 90% VO(OUT) 90%

10% 10%

VOLTAGE WAVEFORMS

Figure 1. Test Circuit and Voltage Waveforms

RL = 5 W,
VI(EN) CL = 1 mF VI(EN)
5 V/div TA = 255C 5 V/div

VO(OUT) RL = 5 W,
2 V/div CL = 1 mF
VO(OUT) TA = 255C
2 V/div

t − Time − 500 ms/div

t − Time − 500 ms/div
Figure 2. Turnon Delay and Rise Time With 1-µF Load Figure 3. Turnoff Delay and Fall Time With 1-µF Load

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PARAMETER MEASUREMENT INFORMATION (continued)

RL = 5 W,
CL = 100 mF VI(EN)
VI(EN) TA = 255C 5 V/div
5 V/div

RL = 5 W,
VO(OUT) CL = 100 mF
2 V/div TA = 255C
VO(OUT)
2 V/div

t − Time − 500 ms/div t − Time − 500 ms/div

Figure 4. Turnon Delay and Rise Time With 100-µF Load Figure 5. Turnoff Delay and Fall Time With 100-µF Load

VIN = 5 V
RL = 5 W,
VI(EN) VI(EN) TA = 255C
5 V/div 5 V/div

220 mF
470 mF

IO(OUT) IO(OUT)
500 mA/div 100 mF
500 mA/div

t − Time − 500 ms/div t − Time − 1 ms/div

Figure 6. Short-Circuit Current, Figure 7. Inrush Current With Different
Device Enabled Into Short Load Capacitance

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PARAMETER MEASUREMENT INFORMATION (continued)

VO(OC) VO(OC)
2 V/div 2 V/div

IO(OUT) IO(OUT)
1 A/div 1 A/div

t − Time − 2 ms/div t − Time − 2 ms/div

Figure 8. 2-Ω Load Connected to Enabled Device Figure 9. 1-Ω Load Connected to Enabled Device

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TYPICAL CHARACTERISTICS
TURNON TIME TURNOFF TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
1.0 2
CL = 100 mF, CL = 100 mF,
0.9 RL = 5 W, RL = 5 W,
TA = 255C TA = 255C
0.8 1.9

0.7
Turnon Time − ms

Turnoff Time − mS
0.6 1.8

0.5

0.4 1.7

0.3

0.2
1.6
0.1

0 1.5
2 3 4 5 6 2 3 4 5 6
VI − Input Voltage − V VI − Input Voltage − V
Figure 10. Figure 11.

RISE TIME FALL TIME

vs vs
INPUT VOLTAGE INPUT VOLTAGE
0.6 0.25
CL = 1 mF, CL = 1 mF,
RL = 5 W, RL = 5 W,
0.5 TA = 255C TA = 255C
0.2

0.4
Rise Time − ms

Fall Time − ms

0.15

0.3

0.1
0.2

0.05
0.1

0 0
2 3 4 5 6 2 3 4 5 6
VI − Input Voltage − V VI − Input Voltage − V
Figure 12. Figure 13.

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TYPICAL CHARACTERISTICS (continued)

TPS2061, TPS2065-1 TPS2062-1, TPS2066-1

SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT ENABLED
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
60 70
I I (IN) − Supply Current, Output Enabled − µ A

I I (IN) − Supply Current, Output Enabled − µ A

VI = 5.5 V VI = 5.5 V
50 60
VI = 5 V
50
40 VI = 5 V
VI = 3.3 V
40
30
30
VI = 2.7 V VI = 2.7 V
20
VI = 3.3 V 20

10
10

0 0
−50 0 50 100 150 −50 0 50 100 150
TJ − Junction Temperature − 5C TJ − Junction Temperature − 5C
Figure 14. Figure 15.

TPS2065-1 TPS2062-1, TPS2066-1

SUPPLY CURRENT, OUTPUT DISABLED SUPPLY CURRENT, OUTPUT DISABLED
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
1.6 10

9
1.4
8
1.2
I − Off-State Current − mA

I − Off-State Current − mA

7
1
6

0.8 5

4
0.6
3
0.4
2
0.2
1

0 0
−50 0 50 100 150 −50 0 50 100 150
o o
TJ − Junction Temperature − C TJ − Junction Temperature − C
Figure 16. Figure 17.

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TYPICAL CHARACTERISTICS (continued)

STATIC DRAIN-SOURCE ON-STATE RESISTANCE SHORT-CIRCUIT OUTPUT CURRENT

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
120 1.56
IO = 0.5 A VI = 2.7 V
1.54
Out1 = 5 V

I OS − Short-Circuit Output Current − A

100 1.52
VI = 3.3 V
On-State Resistance − mΩ
r DS(on) − Static Drain-Source

1.5
Out1 = 3.3 V
80
Out1 = 2.7 V 1.48

1.46
60
1.44 VI = 5 V
1.42
40
1.4 VI = 5.5 V

20 1.38

1.36

0 1.34
−50 0 50 100 150 −50 0 50 100 150
TJ − Junction Temperature − 5C TJ − Junction Temperature − 5C
Figure 18. Figure 19.

THRESHOLD TRIP CURRENT UNDERVOLTAGE LOCKOUT

vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
2.5 2.3
TA = 255C UVLO Rising
Load Ramp = 1A/10 ms
UVOL − Undervoltage Lockout − V

2.3 2.26
Threshold Trip Current − A

2.1 2.22 UVLO Falling

1.9 2.18

1.7 2.14

2.1
1.5
−50 0 50 100 150
2.5 3 3.5 4 4.5 5 5.5 6
TJ − Junction Temperature − 5C
VI − Input Voltage − V
Figure 20. Figure 21.

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TYPICAL CHARACTERISTICS (continued)

CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
200
VI = 5 V,
TA = 255C

Current-Limit Response − µ s
150

100

50

0
0 2.5 5 7.5 10 12.5
Peak Current − A
Figure 22.

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APPLICATION INFORMATION

POWER-SUPPLY CONSIDERATIONS
TPS2062-1
Power Supply 2
IN
2.7 V to 5.5 V 7
OUT1 Load
0.1 µF
0.1 µF 22 µF

8
OC1
3 6
EN1 OUT2 Load
5
OC2 0.1 µF 22 µF
4
EN2
GND
1

Figure 23. Typical Application

A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.

OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 15). The TPS206x-1 senses the short and
immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 17). The TPS206x-1 is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its constant-current
mode.

OC RESPONSE
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS206x-1 is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates
the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned
off due to an overtemperature shutdown.

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V+

Rpullup
TPS2062-1

GND OC1
IN OUT1
EN1 OUT2
EN2 OC2

Figure 24. Typical Circuit for the OC Pin

POWER DISSIPATION AND JUNCTION TEMPERATURE

The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power
dissipation per switch can be calculated by:
PD = rDS(on) × I2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ = PD ×RθJA + TA
Where:
TA= Ambient temperature °C
RθJA = Thermal resistance
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.

THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS206x-1 implements a thermal sensing to monitor the operating junction
temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature
rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to
overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power
switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.

UNDERVOLTAGE LOCKOUT (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and
voltage overshoots.

14 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1

 TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009

UNIVERSAL SERIAL BUS (USB) APPLICATIONS

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
• Hosts/self-powered hubs (SPH)
• Bus-powered hubs (BPH)
• Low-power, bus-powered functions
• High-power, bus-powered functions
• Self-powered functions
SPHs and BPHs distribute data and power to downstream functions. The TPS206x-1 has higher current
capability than required by one USB port; so, it can be used on the host side and supplies power to multiple
downstream ports or functions.

HOST/SELF-POWERED AND BUS-POWERED HUBS

Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see
Figure 25). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream
connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection
and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,
and stand-alone hubs.

Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com

Downstream
USB Ports

D+

D−
VBUS
0.1 µF 33 µF GND
Power Supply

3.3 V 5V TPS2062-1 D+
2
IN D−
7
OUT1 VBUS
0.1 µF 0.1 µF 33 µF GND

8
OC1
3
USB EN1
5
Controller OC2 D+
4
EN2 D−
6
OUT2 VBUS
0.1 µF 33 µF GND
GND
1
D+

D−
VBUS
0.1 µF 33 µF GND

Figure 25. Typical Four-Port USB Host / Self-Powered Hub

BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to
power up with less than one unit load. The BPH usually has one embedded function, and power is always
available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up,
the power to the embedded function may need to be kept off until enumeration is completed. This can be
accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 µF at power up, the device must implement inrush current limiting (see Figure 26). With TPS206x-1, the
internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving
circuits.

16 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1

 TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009

Power Supply
D+ 3.3 V
TPS2062-1
D−
2
VBUS IN
10 µF 0.1 µF 7
OUT1 Internal
GND
0.1 µF 10 µF Function

8
OC1
3
USB EN1
Control 5
OC2
4 6
EN2 OUT2 Internal
GND 0.1 µF 10 µF Function
1

Figure 26. High-Power Bus-Powered Function

USB POWER-DISTRIBUTION REQUIREMENTS

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
• Hosts/SPHs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
• BPHs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µF)
• Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS206x-1 allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and
controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input
ports for bus-powered functions (see Figure 27).

Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com

TUSB2040
Hub Controller

SN75240 BUSPWR Tie to TPS2041 EN Input

Upstream A C Downstream
Port GANGED Ports
B D
DP0 DP1 D+
D+
DM0 DM1 D−
D− Ferrite Beads
A C
GND
GND B D
SN75240
DP2 5V
TPS2041B DM2
OC EN 5-V Power 33 µF†
Supply DP3
5V IN OUT DM3
D+
A C
1 µF B D D−
TPS76333 Ferrite Beads
SN75240 GND
IN DP4
0.1 µF DM4
3.3 V VCC 5V
4.7 µF 4.7 µF TPS2062-1
GND
GND PWRON1 EN1 OUT1 33 µF†
OVRCUR1 OC1 OUT2
48-MHz PWRON2 EN2
XTAL1
Crystal D+
OVRCUR2 OC2 IN
D−
0.1 µF Ferrite Beads
Tuning GND
XTAL2
Circuit
5V
OCSOFF

33 µF†
GND

D+
D−
Ferrite Beads
GND

5V

33 µF†
Note: USB rev 1.1 requires 120 mF per hub.

Figure 27. Hybrid Self / Bus-Powered Hub Implementation

GENERIC HOT-PLUG APPLICATIONS

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS206x-1, these devices can be used to
provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the
TPS206x-1 also ensures that the switch is off after the card has been removed, and that the switch is off during
the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card
or module.

18 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1

 TPS2062-1
TPS2065-1
TPS2066-1
www.ti.com................................................................................................................................................ SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009

PC Board

Power TPS2062-1
Supply GND OC1 Block of
Circuitry
2.7 V to 5.5 V IN OUT1
1000 µF 0.1 µF EN1 OUT2
Optimum EN2 OC2
Block of
Circuitry
Overcurrent Response

Figure 28. Typical Hot-Plug Implementation

By placing the TPS206x-1 between the VCC input and the rest of the circuitry, the input power reaches these
devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage
ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.

DETAILED DESCRIPTION

Power Switch
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a
minimum current of 1 A.

Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.

Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.

Enable (ENx or ENx)

The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 1 µA when a logic high is present on ENx, or when
a logic low is present on ENx. A logic zero input on ENx, or a logic high input on ENx restores bias to the drive
and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic
levels.

Overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A
10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown
occurs, the OCx is asserted instantaneously.

Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1
TPS2062-1
TPS2065-1
TPS2066-1
SLVS714A – FEBRUARY 2007 – REVISED MARCH 2009................................................................................................................................................ www.ti.com

Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.

Thermal Sense
The TPS206x-1 implements a thermal sensing to monitor the operating temperature of the power distribution
switch. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises
to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch,
thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has
cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the
fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature
shutdown or overcurrent occurs.

Undervoltage Lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.

Discharge Function
When the device is disabled (when enable is deasserted or during power-up power-down when VI < UVLO) the
discharge function is active. The discharge function offers a resistive discharge path for the external storage
capacitor. This is suitable only to discharge filter capacitors for limited time and cannot dissipate steady state
currents greater than 8 ma.

20 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS2062-1 TPS2065-1 TPS2066-1

 PACKAGE OPTION ADDENDUM

www.ti.com 26-Feb-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS2062D-1 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2062-1

TPS2062DR-1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2062-1

TPS2065DGNR-1 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 2065
-1
TPS2066DGN-1 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 2066
-1
TPS2066DGNR-1 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2066
-1

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Feb-2022

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS2062-1, TPS2065-1, TPS2066-1 :

• Automotive : TPS2062-Q1, TPS2065-Q1, TPS2066-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2062DR-1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2065DGNR-1 HVSSOP DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS2066DGNR-1 HVSSOP DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2062DR-1 SOIC D 8 2500 340.5 336.1 25.0
TPS2065DGNR-1 HVSSOP DGN 8 2500 346.0 346.0 35.0
TPS2066DGNR-1 HVSSOP DGN 8 2500 346.0 346.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS2062D-1 D SOIC 8 75 507 8 3940 4.32
TPS2066DGN-1 DGN HVSSOP 8 80 322 6.55 1000 3.01
TPS2066DGN-1 DGN HVSSOP 8 80 330 6.55 500 2.88

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DGN 8 PowerPAD VSSOP - 1.1 mm max height
3 x 3, 0.65 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225482/A

www.ti.com
 PACKAGE OUTLINE
DGN0008C SCALE 4.000
HVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.37
8X
0.26
3.1 0.1 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
1.92
1.66 9 1.1 MAX

8
1 0.15
0.7
0 -8 0.4 0.05
DETAIL A
A 20

1.60
1.34 TYPICAL

4218838/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGN0008C HVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.6)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(1.92)
(1.1)
6X (0.65)

4 5

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4218838/A 11/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGN0008C HVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.6)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(1.92)
SYMM BASED ON
0.125 THICK
STENCIL

6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 1.79 X 2.15
0.125 1.60 X 1.92 (SHOWN)
0.15 1.46 X 1.75
0.175 1.35 X 1.62

4218838/A 11/2017
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
TM
DGN0008G SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
2.15
1.95 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.846
TYPICAL
1.646

4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.846)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(2.15)
6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225480/A 11/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(2.15)
SYMM BASED ON
0.125 THICK
STENCIL

6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.06 X 2.40
0.125 1.846 X 2.15 (SHOWN)
0.15 1.69 X 1.96
0.175 1.56 X 1.82

4225480/A 11/2019
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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