INTELLECTUAL PROPERTY DIVISION

DDR SDRAM Roadmap and an Overview of DDR3

Peter Gillingham, CTO, MOSAID Technologies

March 2007
Outline

> DRAM Standards

> Evolution DRAM > SDRAM > DDR > DDR2 > DDR3
> DDR3 Features
» Packaging
» Pinout
» Functional changes
» Built-in calibration features
> Beyond DDR3

March 2007 2
JEDEC Standards

> Organization under EIA – Electronics Industry Association

> Participation by memory manufacturers, memory users,
packaging, test companies ~ 280 companies
> Relevant committees
» JC16 – interface and signalling
» JC42 – RAM features and functions
» JC45 - modules
> Before SDRAM JEDEC focused mainly on package and pinout
> JEDEC now standardizes virtually entire datasheet
» JESD79-2C – DDR2
» JESD79-3 – DDR3, not yet published
> JEDEX – annual JEDEC sponsored trade show
» Silicon Valley, Asia

March 2007 3
Asynchronous DRAM
Vdd

Row decoder
Addr. row column

Column decoder
RAS#

Sense amps

Word line
CAS# Memory
array
DQ Data out

» Multiplexed Address bus

» Control clocks RAS#, CAS#, etc. Vss
» RAS# directly controls wordline activation,
bitline sensing, and precharge
» Bi-directional data bus

March 2007 4
Synchronous DRAM - SDRAM
Vdd

Row decoder
CLK
Word line

Instruction Decoder
Addr. row column Bank 0

RAS# Sense amps

Column decoder

CAS# Column decoder

Sense amps
DQ 0 1 2 3

Row decoder
Bank 1

» Multiple independent banks

» Continuous free running clock
» All inputs sampled on rising edge of clock Vss

» RAS#, CAS#, etc. encoded instructions

» Configurable burst length, latency

March 2007 5
Double Data Rate - DDR SDRAM
Vtt

Vddq Vdd
R

DLL
CK/CK# Bank 0

Addr. row column

Instruction Decoder
RAS# Bank 1

CAS#

DQ 0 1 2 3 Bank 2

DQS

Vref Bank 3
» Data on both edges of clock
» Command and Address on rising edge only
» Differential clock Vssq Vss
» Source synchronous bi-directional DQS clock
» Terminated, reduced swing I/O
» Delay Locked Loop – DLL
March 2007 6
DDR2 SDRAM
Vtt

Vddq Vdd
R

CK/CK#

DLL
Bank 0
Addr. row col.

Instruction Decoder
RAS# Bank 1

CAS#

DQ 0 1 2 3
Bank 2
DQS/DQS#

ODT
Bank 3
Vref
» Data strobe pair – DQS/DQS#
» On die termination for DQ, DQS Vssq Vss

» ODT pin to enable/disable termination

March 2007 7
DDR3 SDRAM Vtt

R# Vddq Vdd
R

CK/CK# Bank 0

DLL
Addr. row col. Bank 1

Bank 2

Instruction Decoder
RAS#
Bank 3
CAS#

0 1 2 3 Bank 4
DQ

DQS/DQS# Bank 5

ODT Bank 6
» Reset pin - R#
Vref Bank 7
» ZQ for ODT and output driver
impedance calibration ZQ Vssq Vss
» True differential DQS
» Timing calibration features – write
leveling and predefined read pattern
March 2007 8
The Evolution of the SDRAM Interface
Feature/Option SDRAM DDR SDRAM DDR2 SDRAM DDR3 SDRAM
Density 64Mb – 512Mb 128Mb – 1Gb 256Mb – 4Gb 512Mb – 8Gb
Organization x4, x8, x16, x32 x4, x8, x16 x4, x8, x16 x4, x8, x16
Data Rate (Mb/s/pin) 100, 133 200, 266, 333, 400 400, 533, 667, 800, 1066 800, 1066, 1333, 1600
VDD / VDDQ 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.1V 1.5V ± 5%
Interface LVTTL SSTL_2 SSTL_18 SSTL_15
# Banks 2, 4 4 4, 8 8
Prefetch 1 2 4 8
Burst Length 1, 2, 4, 8, page 2, 4, 8 4, 8 8, 4 with BC
Differential, Bi-dir.
Data Strobe None Single ended, Bi-dir. Single or Diff. RDQS opt.
WR Leveling
DQ Driver Wide range Narrow range OCD (unused) ZQ Calibration
Termination None Ω on board Ω on board/ODT ODT with ZQ
DLL aligns DQ & DQS to DLL aligns DQ, DQS, DQSb, DLL aligns DQ, DQS, DQSb to
Read DQ Timing Native tAA
CK RDQS to CK CK
Write DQ Timing Setup/hold to CK Setup/hold to DQS Setup/hold to DQS, DQSb Setup/hold to DQS, DQSb
CAS Latency (CL) (1), 2, 3 2, 2.5, 3 (2), 3, 4, 5 5, 6, 7, 8, 9, 10, (11)
Additive Latency (AL) none None 0, 1, 2, 3, 4 0, CL-1, CL-2
Read Latency (RL) CL CL CL + AL CL + AL
Write Latency (WL) 0 1 RL - 1 5, 6, 7, 8
Reset No No No Yes
Package TSOP TSOP/BGA BGA BGA with mirroring

March 2007 9
DDR3 Introduction

> Smaller package

> x4, x8, x16 devices
> 800 – 1600 Mbps bandwidth per pin
» Will DDR2-1066 push out DDR3?
> Lower power
» 1.5V versus 1.8V for DDR2
> 8 banks
> Data prefetch of 8
» Access too much data per address?
» Gaps at BL=4
> Reset pin (finally)
> System calibration features
» ZQ output impedance reference
» Write leveling
» Read data training
» Temperature dependant refresh interval

March 2007 10
DDR3 Packaging

> Smaller!
> DDR3 expected to use WLP or flip chip
on laminate substrate, not wire bond
» WLP = Wafer level Package
> WLP builds the package layer directly
on the wafer by incorporating
fabrication process
» Enhances electrical properties
(shorter circuit-routing)
» Smaller form factor
> WLP uses patterned inter-layer
dielectrics, and a metal layer that
replaces the conventional package
substrate
> Ball grids give the appearance of a
chip scale package (CSP) that is truly
scaled down to the actual die size

March 2007 11
DDR3 Packaging vs. DDR2

DDR3

DDR2

March 2007 12
DDR2 To DDR3 Pinout Changes
> BA3
» Extra Bank address pin muxed with A15
» No devices defined yet for 16 banks
> ZQ
» Pin for on-chip driver calibration via external precision resistor
> RESETb
» Active low asynchronous reset
» LVCMOS type input, no termination
» No data retained
> TDQS/TDQSb
» Termination Data Strobe (optional)
» Muxed on DM pin
» Optional for x8 devices only
> A12/BCb
» Burst Chop sampled on read & write commands
» Chops a burst of 8 into a burst of 4 on the fly
> VREFDQ, VREFCA
» Separate VREF pins for DQ & Command/Address

March 2007 13
DDR3 “8n Rule” Introduces Gaps at BL=4

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13

CK#
CK

COMMAND READ NOP NOP NOP READ NOP NOP NOP NOP NOP NOP NOP NOP NOP

BANK BAn BAn

ADDRESS

COLUMN COLx COLy

ADDRESS

DQS, DQS#
READ CAS Latency = 5
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
DQ (BL = 8) x x+1 x+2 x+3 x+4 x+5 x+6 x+7 y y+1 y+2 y+3 y+4 y+5 y+6 y+7

READ CAS Latency = 5

Dout Dout Dout Dout Dout Dout Dout Dout
DQ (BL = 4) x x+1 x+2 x+3 y y+1 y+2 y+3

Gaps at BL=4
Prefetch size finally gets in the way

March 2007 14
DDR3 ZQ Calibration
> DDR3 include a ZQ pin that is connected to
an external precision resistor
» Precisely sets the “on” impedance of the
output drivers and the ODT impedances
» Minimize mismatch to the PCB trace
impedance
• Minimize reflections & ringing
> RZQ = 240Ω ± 1%
Impedance Mismatch
» O/P driver impedance = RZQ/7 (34Ω)
• Other settings reserved / TBD
» ODT value programmable to RZQ/2 (120Ω),
RZQ/4 (60Ω) or RZQ/6 (40Ω)
» Much tighter tolerances vs. DDR2
» Better PVT immunity
> Long & short calibration sequence
> Improves the timing budget for the memory
channel Better Impedance Match
March 2007 15
Command to Data Skew on DIMMs

Address, Command, Clock in

“Fly By” Topology in DDR3 DIMM

DQ, DQS

VTT
DQ, DQS
DQ, DQS
DQ, DQS
DQ, DQS
DQ, DQS

Data Skew
DQ, DQS
DQ, DQS
DQ, DQS

Data
DataSkew
SkewCalibrated
CalibratedOut
OutatatInitialization
Power Up with withWrite
WriteLeveling
Leveling

March 2007 16
DDR3 Write Leveling
Clock signals at controller
> Controller puts DRAM in
CK
write leveling mode by
writing to mode register DQS

> Controller sends continuous Clock signals at memory

DQS clocks initially aligned CK

with CK DQS
> DRAM internally samples CK DQ0
with DQS rising edge which
is initially ‘0’ due to larger controller memory
delay on CK CK
> Controller gradually adds clk
DQS D
delay to DQS clock until 0 to delay Q

1 transition observed on
DQ0
DQ0

March 2007 17
DDR3 Multi-Purpose Register (MPR)

> MPR is used to output data on the DQ

pins. The MPR is enabled via
extended mode register EMR3.
> Currently 2 uses are defined; DRAM
» Predefined read data pattern for Memory
system level read calibration purposes,
“01010101” in BL8, “0101” in BL4 Core
» Output ODTS (On Die Thermal Sensor) MPR
reading for refresh period optimization
EMR3 A2

> Predefined read data pattern

» DRAM outputs a “known good data
pattern” to the memory controller
without a requirement for write DQ, DQS/DQSb Pads
operations
» memory controller calibrates read data
capture by shifting DQS data strobes
into the middle of the ‘0101’ data eye

March 2007 18
DDR3 On Die Thermal Sensor (ODTS)
> Optional feature – may not be supported by all
manufacturers
> Addresses inverse relationship between the memory Refresh
array temperature and the rate at which the DRAM cells Interval
leak
» Higher temperature = more leakage = shorter refresh 3.9μs

TCASE
interval
> DDR3 SDRAMs have two self refresh modes that scale
the refresh rate according to case temperature, TCASE 7.8μs
» TCASE ≤ 85ºC  7.8us refresh interval
» 85ºC < TCASE ≤ 95ºC  3.9us refresh interval
> Controller can obtain ODTS temperature status by MPR
read operation and adjust refresh interval accordingly
> Controller can also enable automatic adjustment of
refresh interval during self-refresh based on ODTS
reading

March 2007 19
Looking ahead to DDR4

> JEDEC is currently discussing DDR4 proposals

> JEDEC discussions are confidential among members
> Expect to double the data rate once again, to 1.6 –
3.2Gb/s
> SERDES data rates imply new challenges
» Coding for error detection and correction
» Timing recovery
> GDDR4 (2.8Gb/s) features
» Point-to-point operation
» Data bus inversion to reduce SSO noise
» Unidirectional read and write DQS strobes
» Extended preamble with multiple transitions

March 2007 20
DRAM core
BLn BLn* DB DB* BLn+2 BLn+2*

WLx+1
cell
WLx array

bitline
EQ
equalize

ISO isolation

PR

sense
amplifier

PS*

column
access
Y0
Y2

March 2007 21
DRAM Peak Bandwidth Evolution

1600 2011

1400
2010
Peak Bandwidth (Mb/s/pin)

1200
2008
1000
2007
800
2006
600 2005
2003
400
2001
200
1997 1998 2000
1992 1994
0
FPM DRAM

EDO DRAM

SDRAM

DDR-200

DDR-400

DDR2-533

DDR2-667

DDR2-800

DDR2-1066

DDR3-1333

DDR3-1600
PC100

PC133

March 2007 22