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Lecture 4
Field Effect Transistors (FETs)
Classifications
The FET is another major class of transistor, often referred to as a unipolar transistor, because conduction occurs as
a result of a single type of charge carrier (holes or electrons). This is in contrast to the bipolar junction transistor,
where conduction occurs as a result of both types of charge carriers.

The operation of the FET is very similar to a triode valve in that current through the device is controlled by an input
voltage.

There are certain similarities and significant differences between the BJT and the FET:

(1) The BJT is considered as a current-controlled device, while the FET is a voltage-controlled device.

(2) The control terminal of a BJT draws a moderate current, so the effective input resistance is relatively low. In
contrast, the control terminal of an FET requires virtually no current, so the input resistance is very high.

The FET classification structure is shown in Figure 1.

There are two main classes of FETs:

(1) JFETs

(2) MOSFETs

Family Tree showing different classifications of FETs.

FIELD EFFECT TRANSISTORS
(FETs)

JUNCTION FETs Metal Oxide Silicon FETs

(JFETs) MOSFETs

ENHANCEMENT
DEPLETION MODE DEPLETION MODE
MODE

N P N P N P

Figure 1

All JFETs operate in what is called the depletion mode while MOSFET is further classified as either a depletion-mode
device or an enhancement-mode device. A depletion-mode MOSFET functions in the same manner as a JFET.

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Depletion-mode devices (either JFETs or MOSFETs) are referred to as normally on devices, since they are capable of
some conductivity with no control voltage. Enhancement-mode devices are referred to as normally off devices,
since they will not conduct without an enhancement voltage which is similar to BJTs. Similar to BJTs all FETs are
available as either n-channel or p-channel types.

Junction FETs
A simplified construction of an n-channel JFET is indicated by the sketch. The schematic symbol for N and P channel
JFETs is also shown.

Construction Circuit Symbol

N-channel JFET by Zedh, CC BY-SA 4.0

P-channel JFET by Zedh, CC BY-SA 4.0

JFET by Rparle, CC BY-SA 3.0

A lightly doped bar of n-type semiconductor material (usually silicon) forms the channel and contacts are placed at
both ends. These are designated the source and the drain. Two segments of heavily doped p-type semiconductor
are embedded in the sides and are internally connected and constitute the gate. Current flow along the channel is
heavily influenced by the voltage at the gate through a depletion layer. The p-type gate and the n-type channel
constitute a p-n junction diode. In the normal operation of the n-type channel JFET, the gate is reverse biased and
hence there are zero current flow into the gate during conduction of the n-type channel.

Drain characteristics of an n-channel JFET

N channel JFET VI characteristics by Phirosiberia, CC BY-SA 3.0

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Operation
PINCH-OFF CUT-OFF

(SATURATION)

Id = Idss Id = 0

mA
mA V DD
VDD
Vgs = Vgs
OFF
Vgs = 0V

As VDS increases, the voltage between gate and drain (i.e., VGD) becomes increasingly negative. This negative voltage
results in a depletion region along the drain end of the channel. The result is that the current flow becomes
saturated and very little further increase can occur. The channel is said to be “pinched-off” and any further increase
in 𝑉𝑉𝐷𝐷𝐷𝐷 will have no effect on the current flow. This give rise to the saturation (or active) region of the JFET
characteristic. This slope of the saturation region represents the output resistance of the device.

The thickness of the channel is controlled by the voltage applied at the gate and also influenced by 𝑉𝑉𝐷𝐷𝐷𝐷 . For small
𝑉𝑉𝐷𝐷𝐷𝐷 the thickness of the channel increase as the gate voltage increase which results in the reduction of effective
resistance of the channel. This resembles that of a resistor with 𝐼𝐼𝐷𝐷 proportional to 𝑉𝑉𝐷𝐷𝐷𝐷 . This effective resistance is
controlled by 𝑉𝑉𝐺𝐺𝐺𝐺 and therefore this region is known as the ohmic region on the characteristic.

As the gate voltage decrease the channel width will start to decrease and eventually cut-off all current through the
channel. The gate voltage required for this to occur is known as the gate cut-off voltage 𝑉𝑉𝐺𝐺𝐺𝐺(𝑂𝑂𝑂𝑂𝑂𝑂) .

Note that in each case the depletion region extends across the entire channel width due to the reverse bias voltage.
In the case of the pinch-off condition, this only occurs at the drain end of the channel due to VDS ≥ VP , thus giving
rise to a constant current. Cut-off occurs when VGS = VT.

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JFET datasheet – J112

Characteristics in the saturation region

The drain current in the beyond pinch-off or constant-current region follows a square-law function relationship and
can be closely approximated for many JFETs as:
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𝑉𝑉𝐺𝐺𝐺𝐺 2
𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 �1 − 𝑉𝑉𝑇𝑇
�

𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷
OR 𝐼𝐼𝐷𝐷 = 𝛽𝛽[𝑉𝑉𝑇𝑇 − 𝑉𝑉𝐺𝐺𝐺𝐺 ]2 where 𝛽𝛽 = 𝑉𝑉𝑇𝑇2
is the transconductance coefficient

NOTE: For an n-channel JFET, VGS(OFF) is negative, and VGS is either negative or zero.

Transfer characteristic
The transfer characteristic is a plot of ID versus VGS in the conduction region. There are three identifiable regions for a
JFET:

• Linear: The JFET is acting like a resistor in this region. In the Linear region, the JFET assumes the role of a
voltage-controlled resistor.
• Saturation: As VDS is further increased; there is very little additional change in ID. This region is referred to as
the saturation or constant-current region.
• Cut-off (Channel off): At some negative value of VGS, the effective conduction width of the channel will be
reduced completely to zero by depletion. The value of gate-source voltage is called the gate-source cut-off
voltage, denoted by VGS(OFF). 𝑉𝑉𝐺𝐺𝐺𝐺(𝑂𝑂𝑂𝑂𝑂𝑂) can also be represented as the threshold voltage 𝑉𝑉𝑇𝑇 . In this lecture 𝑉𝑉𝑇𝑇
and 𝑉𝑉𝐺𝐺𝐺𝐺(𝑂𝑂𝑂𝑂𝑂𝑂) are interchangeable.

N channel JFET VI characteristics by Phirosiberia, CC BY-SA 3.0

Example : plot the transfer characteristic of a n-channel JFET if 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 = 12𝑚𝑚𝑚𝑚 and 𝑉𝑉𝑇𝑇 = −4𝑉𝑉.

JFET bias analysis:

There are two methods for analysing a JFET bias circuit:

(1) mathematical (2) graphical

In each case, the transfer characteristic of the JFET is equated with the bias line of the circuit which can be derived
from:

𝑽𝑽𝑮𝑮𝑮𝑮 = 𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑺𝑺

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To design a JFET bias circuit using a “rule of thumb” (ROT):
1 1 1 2
let 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝑇𝑇 then 𝑉𝑉𝑇𝑇 ⇒ 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 since 𝐼𝐼𝐷𝐷 ∝ 𝑉𝑉𝐺𝐺𝐺𝐺
2 2 4

JFET self bias analysis

V_DD

Since a JFET requires −𝑉𝑉𝐺𝐺𝐺𝐺 to operates in the linear region. Therefore we can
bias the JFET by grounding the Gate terminal. As the bias current flow from the
RD1 drain terminal to the source terminal, the source current will become a voltage
at the source terminal.

Since 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑆𝑆 and 𝑉𝑉𝐺𝐺 = 𝐺𝐺𝐺𝐺𝐺𝐺 = 0𝑉𝑉. 𝑉𝑉𝐺𝐺𝐺𝐺 = −𝑉𝑉𝑆𝑆 which is the required
negative voltage for the JFET to operates in the linear region.
Q2

RG1 RS1
The drain voltage can be determined using KVL: 𝑉𝑉𝐷𝐷𝐷𝐷 = 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 + 𝑉𝑉𝐷𝐷 → 𝑉𝑉𝐷𝐷 =
𝑉𝑉𝐷𝐷𝐷𝐷 − 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 .

Transconductance
The FET is a trans-conductance device (similar to a BJT) such that the input voltage controls the output current. This
can be expressed as:

𝑖𝑖𝑑𝑑 𝑑𝑑𝐼𝐼𝐷𝐷
𝑔𝑔𝑚𝑚 = =
𝑣𝑣𝑔𝑔𝑔𝑔 𝑑𝑑𝑉𝑉𝐺𝐺𝐺𝐺

𝑉𝑉𝐺𝐺𝐺𝐺 2
Since 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 �1 − 𝑉𝑉𝑇𝑇
� , then

𝑑𝑑𝐼𝐼 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 𝑉𝑉 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷

𝑔𝑔𝑚𝑚 = 𝑑𝑑𝑉𝑉 𝐷𝐷 = −2 𝑉𝑉𝑇𝑇
�1 − 𝑉𝑉𝐺𝐺𝐺𝐺 � = 2𝛽𝛽[𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 ] where 𝛽𝛽 = 𝑉𝑉𝑇𝑇2
𝐺𝐺𝐺𝐺 𝑇𝑇

Ohmic-region characteristics
For very small values of VDS, the curves of ID versus VDS were straight lines whose slopes were a function of VGS. In
1 1
this region the FET behaves like a voltage-controlled resistor. 𝑟𝑟𝐷𝐷𝐷𝐷 = =
𝑔𝑔𝑚𝑚 2𝛽𝛽[𝑉𝑉𝐺𝐺𝐺𝐺 −𝑉𝑉𝑇𝑇 ]

Simulator parameters
MULTISIM/SIMETRIX etc... use the JFET parameters in a slightly different form: VGS-OFF is represented as VT but IDSS is
not used as such. Instead the simulator uses the parameter “trans-conductance coefficient” k which is usually
associated with MOSFETs. This has the advantage of being able to use the same parameters for all FETs by using 𝛽𝛽 as
k.

JFET analysis example:

Consider the following common source JFET amplifier circuit, given that IDSS = 10mA and VT = -4V, determine 𝑉𝑉𝐺𝐺𝐺𝐺 , 𝑉𝑉𝐷𝐷
and 𝐼𝐼𝐷𝐷 of the circuit using calculation and load-line technique.

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JFET AC analysis
The small signal model of the JFET is similar to a BJT except 𝑟𝑟𝐺𝐺𝐺𝐺 is an open circuit due to the reverse bias voltage of
𝑉𝑉𝐺𝐺𝐺𝐺 which cause p-n junction to be reverse bias.

Using the small signal AC model we can determine the voltage gain of a JFET amplifier.

JFET amplifier design

Example: Design a common source (CS) JFET amplifier for 𝐴𝐴𝑉𝑉 = −10 if IDSS = 12mA, VT = -4V and 𝑅𝑅𝑖𝑖𝑖𝑖 = 100𝑘𝑘Ω.
1
Determine 𝑅𝑅𝐺𝐺 , 𝑅𝑅𝑆𝑆 , 𝑅𝑅𝐷𝐷 𝑎𝑎𝑎𝑎𝑎𝑎 𝑉𝑉𝐷𝐷𝐷𝐷 . Assume 𝑉𝑉𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷 .
2

JFET amplifier analysis

Example: for the following JFET amplifier circuit calculate the drain voltage, source voltage, 𝑉𝑉𝐺𝐺𝐺𝐺 and voltage gain for
𝐼𝐼𝐷𝐷 = 0.5𝑚𝑚𝑚𝑚.

For 𝐼𝐼𝐷𝐷 = 0.5𝑚𝑚𝑚𝑚

12

VDD

RD

Use KVL, 𝑉𝑉𝐷𝐷𝐷𝐷 = 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 + 𝑉𝑉𝐷𝐷𝐷𝐷 + 𝐼𝐼𝑆𝑆 𝑅𝑅𝑆𝑆 = 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 + 𝑉𝑉𝐷𝐷
10k

Therefore 𝑉𝑉𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 = 12𝑉𝑉 − 10𝑘𝑘Ω ∗ 0.5𝑚𝑚𝑚𝑚 = 7𝑉𝑉

100n

𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆 = 𝐼𝐼𝑆𝑆 𝑅𝑅𝑆𝑆 = 0.5𝑚𝑚𝑚𝑚 ∗ 4𝑘𝑘Ω = 2𝑉𝑉

C1 Q1
Vs

𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆 = 0 − 𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆 = −2𝑉𝑉

RG RS

1Meg 4k

Since 𝑉𝑉𝐺𝐺𝐺𝐺 < 0, therefore the JFET is operating in the linear region.

𝑅𝑅 10𝑘𝑘Ω
The voltage gain of the amplifier is 𝐴𝐴𝑉𝑉 = − 𝑅𝑅𝐷𝐷 = − = −2.5
𝑆𝑆 4𝑘𝑘Ω

METAL OXIDE SEMICONDUCTOR FET (MOSFET)

Introduction
The metal-oxide-semiconductor FET (MOSFET) is similar to its JFET counterpart, in that both are devices whose
channel conductivity is controlled by a gate-to-source voltage. The principal feature that distinguishes a MOSFET
from a JFET is that the gate terminal is insulated from its channel region. A MOSFET is often call an insulated-gate

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FET, or IGFET. There are two kinds of MOSFETs: the depletion type and the enhancement type, referred to as
depletion-mode and enhancement-mode MOSFETs.

Enchancement-type MOSFETs

Construction
The following diagram shows the structure of an N-channel D-MOSFET.

STRUCTURE SYMBOL

N-channel enhancement MOSFET by jjbeard,

Public domain

MOSFET Structure by Brews ohare, CC

BY-SA 3.0

P-channel enhancement MOSFET by jjbeard,

Public domain

A block of high resistance, P-type silicon forms a substrate, in which are embedded two heavily doped N-type wells,
or pockets, labelled n+. A thin layer of silicon dioxide (SiO2), which is an insulating material, is deposited along the
surface.

Metal contacts penetrate the silicon dioxide layer at the two N+ wells and become the drain and source terminals.

Between the two N+ wells is a more lightly doped region of N material that forms the channel. Metal (aluminium) is
deposited on the silicon dioxide opposite the channel and becomes the gate terminal. The substrate is usually
connected to the source.

When the gate is made negative with respect to the source by VGS, the electric field it produces in the channel drives
electrons away from a portion of the channel near the SiO2 layer.

The device behaves very much like an N-channel JFET, except that the channel width is controlled by the action of
the electric field rather than by the size of the depletion region of a PN junction.

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Since there is no PN junction, the voltage VGS can be made positive. Making VGS positive attracts more electrons into
the channel and increases, or enhances, its conductivity.

Transfer function & characteristics

Because of the similarity of a D-MOSFET to a JFET, it has similar parameters and operating characteristics and is
biased in the same way.

The square-law equation for the transfer characteristic of a D-MOSFET is identical to that for a JFET:

𝑉𝑉𝐺𝐺𝐺𝐺 2
𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 �1 − 𝑉𝑉𝑇𝑇
�

The gate voltage on a D-MOSFET can be varied through both positive and negative voltages and the device can
operate in both depletion and enhancement modes.

Construction
In the enhancement MOSFET, there is no N-type material between the drain and the source; the P-type substrate
extends all the way to the SiO2 layer adjacent to the gate. This structure is as for the depletion-type MOSFET except
that the channel is induced rather than actual. As in the depletion MOSFET, the substrate is usually connected to the
source. The positive gate voltage attracts electrons from the substrate to the region along the insulating layer
opposite the gate.

If the gate is made sufficiently positive, enough electrons will be drawn into that region to convert it to N-type
material. Thus, an N-type channel will be formed between drain and source. Making VGS more positive enhances the
conductivity of the channel and increases the flow of current from drain to source. The induced N channel does not
become sufficiently conductive to allow drain current to flow until VGS reaches a certain threshold voltage, VT.

In modern silicon MOSFETs, the value of VT is typically in the range from 1V to 4V. The drain characteristics are
similar to those of an N-channel JFET, except that all values of VGS are positive in the case of the enhancement
MOSFET. The enhancement MOSFET can be operated only in an enhancement mode.

The following diagram shows the schematic symbols used to represent N-channel and P-channel enhancement
MOSFETs.

E-MOSFET transfer characteristic

In the active region, the drain current and gate-to-source voltage are related by

𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 2 2
𝐼𝐼𝐷𝐷 = 2 [𝑉𝑉𝑇𝑇 − 𝑉𝑉𝐺𝐺𝐺𝐺 ] = 𝛽𝛽[𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 ]
𝑉𝑉𝑇𝑇
Where β is the trans-conductance coefficient expressed in A/V2 and for E-MOSFET we assume 𝑉𝑉𝐺𝐺𝐺𝐺 > 𝑉𝑉𝑇𝑇 .

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Enhancement MOSFET VI characteristic by CyrilB, CC BY-SA 3.0

𝐴𝐴
Example: if 𝑉𝑉𝑇𝑇 = 2.5𝑉𝑉 and 𝛽𝛽 = 0.1 , plot the 𝐼𝐼𝐷𝐷 vs 𝑉𝑉𝐺𝐺𝐺𝐺 transfer characteristic of the Enhancement-MOSFET.
𝑉𝑉 2

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Biasing methods of E-MOSFET
The E-MOSFET can be biased using the following method:

The voltage divider bias method is like the BJT amplifier where
DIVIDER BIAS the voltage at the source terminal is set by the difference
Vcc
between the gate voltage (𝑉𝑉𝐺𝐺 ) and threshold voltage (𝑉𝑉𝐺𝐺𝐺𝐺(𝑂𝑂𝑂𝑂) ), or
𝑉𝑉𝑆𝑆 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝐺𝐺𝐺𝐺(𝑂𝑂𝑂𝑂).

R1 RD From the source voltage (𝑉𝑉𝑆𝑆 ) we can determine the source

𝑉𝑉𝑆𝑆
current and drain current using ohm’s law, 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝑆𝑆 = .
𝑅𝑅𝑆𝑆

The DC bias voltage at the drain is like the JFET amplifier, i.e.
v_out

𝑉𝑉𝐷𝐷 = 𝑉𝑉𝐶𝐶𝐶𝐶 − 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 .

v_in

Q1

R2 RS

Enhancement-MOSFET amplifier analysis

Enhancement-MOSFET amplifier analysis is like JFET since they use similar equation for 𝐼𝐼𝐷𝐷 and 𝑔𝑔𝑚𝑚 . The only
difference being Enhancement-MOSFET will have positive 𝑉𝑉𝑇𝑇 .

Example: determine the DC bias voltage, voltage gain, Rin and Rout of the following common source Enhancement-
MOSFET amplifier. Assume 𝑉𝑉𝐺𝐺𝐺𝐺 = 2𝑉𝑉.
1𝑀𝑀Ω
𝑉𝑉𝐺𝐺 = ∗ 12𝑉𝑉 = 4𝑉𝑉
3𝑀𝑀Ω

𝑉𝑉𝑆𝑆 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝐺𝐺𝐺𝐺 = 4𝑉𝑉 − 2𝑉𝑉 = 2𝑉𝑉

𝑉𝑉
𝐼𝐼𝑆𝑆 = 𝑅𝑅𝑆𝑆 = 2𝑚𝑚𝑚𝑚 = 𝐼𝐼𝐷𝐷
𝑆𝑆

𝑉𝑉𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 = 12𝑉𝑉 − 2𝑚𝑚𝑚𝑚 ∗ 3.3𝑘𝑘Ω = 5.4𝑉𝑉

𝑅𝑅 3.3𝑘𝑘Ω
𝐴𝐴𝑉𝑉 = − 𝑅𝑅𝐷𝐷 = − = −3.3
𝑆𝑆 1𝑘𝑘Ω

𝑅𝑅𝑖𝑖𝑖𝑖 = 𝑅𝑅1 ∥ 𝑅𝑅2 ∥ 𝑅𝑅𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺 = 2𝑀𝑀Ω ∥ 1𝑀𝑀Ω ∥ Open circuit = 667𝑘𝑘Ω

𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑅𝑅𝐷𝐷 = 3.3𝑘𝑘Ω

Lecture 4 Page 12 of 13
EC Lecture 4 2020s2 - Field Effect Transistors.docx (Revised: 12/10/20)
TAFE SA Associate Degree in Biomedical Engineering
Associate Degree in Electronic Engineering
Associate Degree in Electrical Engineering
ELECTRONIC CIRCUITS
FETs transfer characteristics:

FETs output characteristic:

JFET

Lecture 4 Page 13 of 13
EC Lecture 4 2020s2 - Field Effect Transistors.docx (Revised: 12/10/20)