5 4 3 2 1

D
S32K148EVBQ144/Q176 D
C U S T O M E R E V B

Table of Contents Revisions

01 TITLE AND NOTES Rev Description Designer Date Approved
02 POWER SUPPLY / LIN / CAN X1 Schematic Enwei Hu
03 S32K148 MCU A Prototype
04 VOLTAGE TRANSLATORS B Production
05 RTC and Accelerator B1 Schematic update ONLY
06 ETHERNET
07 FLASH MEM
C 08 SAI AUDIO C

09 I/Os HEADERS
10 TOUCH
11 USER I/Os C A U T I O N :
12 CAN bus This schematic is provided for reference
purposes only. As such, NXP does not make any 3 Different test points
13 BLE GPS & 4G Modules warranty, implied or otherwise, as to the used in design:
14 ECU CONNECTOR suitability of circuit design or component
selection (type or value) used in these TPVx - Through Hole Pad
small
schematics for hardware design using the NXP
S32K family of Microprocessors. Customers using TPHx - Through Hile Pad
any part of these schematics as a basis for Large (for standard 0.1"
header). Also used on IO
hardware design, do so at their own risk and Matrix (IOMx)
Freescale does not assume any liability for such
a hardware design. TPX - Surface Mount Wire
Loop

B Notes: B

- All components and board processes are to be ROHS compliant

- All connectors and headers are denoted Jx/Px and are 2.54mm pitch unless otherwise stated
- All jumpers are denoted Jx. Jumpers are 2mm pitch
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always
posn 1-2.
2 Pin jumpers generally have the "source" on pin 1.
- All switches are denoted SWx
- All test points (SMT wire loop style) are denoted TPx
- Test point Vias (just through hole pads) are denoted TPVx

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
Signals (ports) have not been routed via busses as this makes it harder to determine
This document contains information proprietary to NXP and shall not be used for engineering design,
where each signal goes. procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
User notes are given throughtout the schematics. ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Specific PCB LAYOUT notes are detailed in ITALICS Enwei Hu
S32K148-T-BOX
Drawn by: Page Title:
Enwei Hu TITLE/NOTE
Approved: Size Document Number Rev
Enwei Hu B SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 1 of 14

5 4 3 2 1
 5 4 3 2 1

3.3V Switching Regulator

HDR TH 1X3 Input Voltage 5V, Output 3.3V at 1600mA
P5V0_V1SBC J29 PVEXT_SBC

TP1 Battery supply

L1 330 OHM
input for SMPS TPAD1
VBAT 1 2 R3

1
2
3
1.0K 1.69K 1% R5
1%
TP2 Buck/boost J2 VBAT P5V0 R6 1% 3.09K
D TP6 SMPS output HS-CAN/dual LIN HDR TH 1X3 TPAD3 U1 DNP D
D1 1
VSUP voltage system basis chip D2
A C 2 A C 1 3
3 VIN FB TPAD4 L2 TP8 P3V3_SW
C3 C4 C6 C7 TP10 TP11 TP12 TP13 PMEG6045ETP 4.7uH
PMEG3050EP + C2 0.1UF 0.1UF + C5 0.1UF 0.1UF R7 R8 C297 C298 L3 22uH 4 2 1 2 R9 0

VCAN_SBC

1
C10 4700 PF C11 4700 PF SD OUT

GND1
GND2
GND3
GND4
+ C1 47uF 47uF 0 0 22uF 22uF 1 2
220uF Low Low 0603 0603 16V 16V + C16 C15

C
ESR ESR C13 DNP C14 DNP
DNP 47uF 0.1UF
JP1 4700 PF 4700 PF AP1509-SG-13 D3 C23 C17 C18

5
6
7
8
DNP PMEG6045ETP 22uF 0.1UF 0.1UF
P5V0_V1SBC P5V0_V2SBC 16V

A
P5V0_V1SBC HDR 1X1

1
C19 C20

26

38

43

20

47
1
U2 R11 R12 0.1UF 10uF
Bbootstrap capacitor
R10 10K 10K Layout note: follow IC datasheet recommandations for

BAT
BATV2
BATHS1

VCAN
BATSMPS

VSMPS
10K
PCB layout and thermal dissipation
C21 C22 TP14 TP15 TP16
4700 PF DNP 42
4700 PF BOOTH1 44
41 L1 46
40 CAPA L2 48
CAPB BOOTH2
TP18
R13 1.0K 28 P5V0_V1SBC PVEXT_SBC
BATSENSE 6 TPAD8

1
C24 SBC_EN 5 V1 2 R14 0
10nF EN VEXT 3
V2 27
PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX_LS R15 0 7 ADCCAP TPAD9 TPAD10
PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN_LS R16 0 8 SDI
PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX_LS R17 0 9 SDO C25 C26 C27 C28 C29 C30 C31 VDD_MCU_PERH TP20 TP21 P5V0_V1SBC PVEXT_SBC
TX / RX PTA26/FTM5_CH1/LPSPI1_PCS0_LS R18 0 10 SCK 11 R19 0 10nF 10uF 10uF 0.1UF 10uF 10uF 0.1UF VCCA_LS_SBC
SCSN INTN1 13 PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25_LS {2} VCCA_LS_SBC
R20 0 R21 0 R22 0
POKA-YOKE: Place both jumpers with INTN2 PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26_LS {2}
R23 DNP
the same orientation and provide PTA3/LPUART0_TX_LS 17
same airgap between their terminals R25 0 C32 C33 C34 C35 C36 C37 C38 C39 0
PTA2/LPUART0_RX_LS R24 0 16 TXDL1 0.1UF 0.1UF 0.1UF 0.1UF R26 10K SBC_OE 0.1UF 0.1UF 0.1UF 0.1UF
in a square fashion. RXDL1 24 SBC_LIN_OUT1 R27 0 ECU_EXT_LIN1
LIN1 SBC_LIN_OUT2 ECU_EXT_LIN1 {14} U3
25 R28 0 ECU_EXT_LIN2 ECU_EXT_LIN2 {14}
PTA9/LPUART2_TX R29 0 15 LIN2
PTA8/LPUART2_RX R30 0 14 TXDL2 R31 0 LIN1_OUT LIN1and LIN2 Bus 1 8
RXDL2 21 SBC_CAN_H 1 FL4 4 SBC_CANH LIN2_OUT LIN1_OUT {9} routed to I/O VCCA VCCB
R32 0
CANH SBC_CAN_L SBC_CANL LIN2_OUT {9} Connectors PTA3/LPUART0_TX_LS
22 SBC_LIN1TX R33 0 2 7
PTE5/CAN0_TX_LS CANL CAN_H {3,8,9} PTA3/LPUART0_TX A1 B1 PTA2/LPUART0_RX_LS
R34 0 19 2 3 R35 0 SBC_LIN1RX R36 0 3 6
PTE4/CAN0_RX_LS TXDC CAN_L {3,8,9} PTA2/LPUART0_RX A2 B2
R37 0 18 ACT45B-110-2P-TL003 R38 0
RXDC VCCA_LS_SBC 4 5
39 SBC_LIMP R39 0 CANH_OUT CAN Bus GND OE R472 2.2K
C SBC_RESET LIMP CANL_OUT CANH_OUT {9} routed to I/O C
R40 0402 0 12 R41 0 R458 2.2K R471 2.2K
RSTN CANL_OUT {9} Connectors
TP24 TP25 R459 2.2K NTSX2102GU8H
29
NC_29 30 SBC_HVIO8 D4
P5V0_V2SBC VSUP VSUP
J3 SBC_HVIO1 37 NC_30 31 SBC_HVIO7 C A R43 1.8K U4
SBC_HVIO8 {2} SBC_HVIO1 SBC_HVIO2 HVIO1 NC_31 SBC_HVIO6
1 2 R42 10K R44 0 36 32
3 4 SBC_HVIO7 SBC_HVIO3 35 HVIO2 NC_32 33 SBC_HVIO5 1 8
LY L29K-H1K2-26-Z
SBC_LIMP 5 6 SBC_HVIO6 SBC_HVIO4 34 HVIO3 NC_33 VCCA VCCB

GNDSMPS
SBC_EN 7 8 SBC_HVIO5 SW1 HVIO4 R46 0 SBC_LIN2TX R45 0 2 7 PTA9/LPUART2_TX
SBC_HVIO1 SBC_HVIO4 {3,9} PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2 A1 B1 PTA8/LPUART2_RX
9 10 C40 SBC_LIN2RX R47 0 3 6
{3,9} PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3 A2 B2

GND1

GND2

EPAD
SBC_HVIO2 11 12 SBC_HVIO3 1 2 4700 PF HVIO1-8 VCCA_LS_SBC
3 4 Bidirectional 4 5
EVQ-P2402W R460 2.2K GND OE R474 2.2K
HDR 2X6 TH open-drain low-side
DNP driver with UJA1131HW/FD/5V/0 R461 2.2K R473 2.2K

23

45

49
integrated pull-up R446 0 NTSX2102GU8H
SBC Wake-Up
resistance SBC_HVIO5_EXT {14}
U5

1 8
VCCA VCCB
R48 0 2 7 PTE5/CAN0_TX_LS
SBC_HVIO3 {3} PTE5/TCLK2/FTM2_CH3/CAN0_TX/FXIO_D7 A1 B1 PTE4/CAN0_RX_LS
R49 0 DNP TRACE R50 0 3 6
{12} TJA1043_INH {3} PTE4/TRACE_D1/FTM2_CH2/CAN0_RX/FXIO_D6 A2 B2
VCCA_LS_SBC 4 5
R51 0 DNP SBC_HVIO4 GND OE R476 2.2K
{6} ENETSW_INH
R462 2.2K R475 2.2K
R463 2.2K NTSX2102GU8H

Test and reference points

Power LED Indicators
CAN /FD Interface TP28 TP29 TP30 TP31

1
TP40 TP41
{12} CAN0H U6
VBAT HDR 1X4 RA
R495 0 0603
CAN_H 1 1 8
2 VCCA VCCB
DNP R54 3 SBC_SPI_MOSI R53 0 2 7 PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN_LS
{3,9} PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN A1 B1 PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX_LS
R56 C41 C42 0 4 VSUP P5V0 SBC_SPI_MISO R57 0 3 6
{3,9} PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX A2 B2
60.4 Mouting holes VCCA_LS_SBC
100PF 100PF J5 4 5
SPLIT R464 2.2K GND OE R478 2.2K
DNP
BH1 BH2 BH3 BH4 R465 2.2K R477 2.2K
B R59 R60 R61 NTSX2102GU8H B
C43 R58 1.8K 560 560
60.4 ISO 11898-2:201x (upcoming merged ISO Mounting Hole Mounting Hole Mounting Hole Mounting Hole U7
4700 PF
11898-2/5/6) compliant 1 Mbit/s high-speed
R496 0 0603 1 8
CAN transceiver supporting CAN FD active

A
CAN_L VCCA VCCB
communication up to 2 Mbit/s in the CAN

LED_ORANGE
D10 D11 D12 SBC_SPI_CLK R62 0 2 7 PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX_LS
FD data field {3,9} PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX A1 B1 PTA26/FTM5_CH1/LPSPI1_PCS0_LS
RED RED SBC_SPI_CS R63 0 3 6
{12} CAN0L {3,9} PTA26/FTM5_CH1/LPSPI1_PCS0 A2 B2
VCCA_LS_SBC
4 5
C R466 2.2K GND OE R480 2.2K

C
{2} SBC_HVIO1 R64 0 R467 2.2K R479 2.2K
DNP NTSX2102GU8H

R65
0
0603
U8

1 8
VCCA VCCB
R66 0 2 7
Global Supply Jumpers and TPAD11
{3,9} PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25
R67 0 3 A1 B1 6
PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25_LS {2}
{3,9} PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26 PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26_LS {2}
3

Power Selection P3V3_SW VCCA_LS_SBC A2 B2

R68 10K 1 Q1 4 5
MMBT3904TT1G R468 2.2K GND OE R482 2.2K
R69 33K R469 2.2K R481 2.2K
2

P3V3_SW VDD P5V0 P5V0_V1SBC P5V0 NTSX2102GU8H

J9 TPAD13 J8 TPAD12
1 1 R70 R71
2 2 TPAD14 U9
10K 10K
3

3 3 VDD
R74 10K 1 Q2 1 8
HDR TH 1X3 HDR TH 1X3 MMBT3904TT1G DNP VCCA VCCB
R76 33K R75 0 2 7 SBC_RESET
{3,4,9,11,13} PTA5/TCLK1_2/RESET
2

VCCA_LS_SBC 3 A1 B1 6
A2 B2
J11 R470 2.2K 4 5
GND OE
R483 2.2K
VDD TPAD15 TPAD16 VDD_MCU VDD_MCU_PERH NTSX2102GU8H
2
1

HDR_1X2
R77 0 TPAD17

R78 0

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
S32K148-T-BOX
Page Title:
PWR SUPPLY
Size Document Number Rev
D SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 2 of 14

5 4 3 2 1
 5 4 3 2 1

{10} TOUCH_ADC0_A R79 0

{10} TOUCH_ADC1_A R80 0

{10} TOUCH_ADC0_B R83 0

S32K148 Microcontroller {3}
{3}
PTB6_XTAL
PTB7_EXTAL
R81
R82
0
0
PTB6_XTAL_1

144pins LQFP

PTB7_EXTAL_1
{10} TOUCH_ADC1_B R84 0
DNP
R85 0

Y1
U10A 1 2
R86 R87 TPAD18 VDD_MCU
TOUCH 0 PTA0 115
{9} PTA0/ACMP0_IN0/ADC0_SE0 PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN0 8MHZ
TOUCH 0 PTA1 113 C46 C47
{9} PTA1/ACMP0_IN1/ADC0_SE1 PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN1
XTAL

VC080505C150RP
AUDIO_I2C_SDA 105 12PF 12PF
{2,3,8,9} PTA2/LPUART0_RX

1
D AUDIO_I2C_SCL 104 PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT/FXIO_D4/LPUART0_RX/ADC1_SE0 D
{2,3,8,9} PTA3/LPUART0_TX PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1
JTAG 142 DNP
{3} PTA4/CMP0_OUT/JTAG_TMS/SWD_DIO PTA4/CMP0_OUT/EWM_OUT/JTAG_TMS/SWD_DIO
141 32 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 D7
{2,3,4,9,11,13} PTA5/TCLK1_2/RESET PTA5/TCLK1/RESET VDD1
RTC_CLK_EN 85 11 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 10uF 10uF 10uF
{3,9,14} PTA6/FTM0_FLT1 PTA6/FTM0_FLT1/LPSPI1_PCS1/FTM5_CH5/LPUART1_CTS/ADC0_SE2 VDD2
RTC_CLKIN 83 67 DNP DNP
{3,9,14} PTA7/FTM0_FLT2

2
SBC_LIN2RX 144 PTA7/FTM0_FLT2/FTM5_CH3/RTC_CLKIN/LPUART1_RTS/ADC0_SE3 VDD3 51
{2,3,9} PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3 PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3/FTM4_FLT1 VDD4
SBC_LIN2TX 143 91
{2,3,9} PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2 PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3/FTM4_FLT0 VDD5
JTAG 136 124
{3} PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO VDD6
SAI 135
{3,8,9} PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC
SAI 134 13 TPAD19
{3,8,9} PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/SAI0_BCLK PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/FTM2_QD_PHB/SAI0_BCLK VDDA
SAI 130 VDDA_MCU
{3,8,9} PTA13/FTM1_CH7/FTM2_QD_PHA/SAI0_D0 PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS/FTM2_QD_PHA/SAI0_D0 VREFH_MCU L4
SAI 127 14 R88 0
{3,9} PTA14/FTM0_FLT0/FTM3_FLT1/SAI0_D3 PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/SAI0_D3 VREFH
TOUCH R90 0 PTA15 120 30 OHMFER_BEAD
{9} PTA15/FTM1_CH2/ADC1_SE12

1
TOUCH R91 0 PTA16 119 PTA15/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3/FTM7_FLT0/ADC1_SE12 15 VDD_MCU_PERH
{9} PTA16/FTM1_CH3/ADC1_SE13 ENET QSPI 92 PTA16/FTM1_CH3/LPSPI1_PCS2/ADC1_SE13 VREFL R92 0 DNP
S32K148 Debugg Connector
{3,4,9} PTA17/FTM0_CH6/ENET_RESET PTA17/FTM0_CH6/FTM3_FLT0/EWM_OUT/FTM5_FLT0 VREFH {9}
{3,4,9} PTA25/FTM5_CH0
10
PTA25/FTM5_CH0 VSS1
66 C63 C64 C65 C66 C67 C68 C69 C70 D8 20-pin Cortex Debug D ETM connector
SBC_SPI_CS 19 31 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 10uF 10uF
{2,3,9} PTA26/FTM5_CH1/LPSPI1_PCS0 PTA26/FTM5_CH1/LPSPI1_PCS0/LPSPI0_PCS0 VSS2 VC080505C150RP
SBC_SPI_MISO 22 16 DNP
{2,3,9} PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX

2
SBC_SPI_CLK 24 PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX/CAN0_TX VSS3 12 C71
{2,3,9} PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX R93 R94 R95 R96 R97
SBC_SPI_MOSI 26 PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX/CAN0_RX VSS4 50 0.1UF DNP
{2,3,9} PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN 10K 10K 10K 10K
27 PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN VSS5 90 10K
{3,9} PTA30/FTM5_CH5 PTA30/FTM5_CH5/LPUART2_RX/LPSPI0_SOUT VSS6 J12
33 123
{3,9} PTA31/FTM5_CH6 PTA31/FTM5_CH6/LPSPI0_PCS1 VSS7 1 2 R98 0 JTAG
PTA4/CMP0_OUT/JTAG_TMS/SWD_DIO {3}
3 4 R99 0 JTAG
PTC4/FTM1_CH0/RTC_CLKOUT/JTAG_TCLK/SWD_CLK {3}
FS32K148UJT0VLQT 5 6 R100 0 JTAG
PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO {3}
7 8 R101 0 JTAG
TPAD20 PTC5/FTM2_CH0/RTC_CLKOUT/JTAG_TDI {3}
U10B 9 10 R102 0
TPAD21 PTA5/TCLK1_2/RESET {2,3,4,9,11,13}
R103 DNP 11 12 R104 0 TRACE
PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/TRACE_CLKOUT {3,9}
BLE_UART_RX 78 U10E R105 DNP 13 14 R106 0 TRACE
{3,9,13} PTB0/SBC_LPSPI0_PCS0 PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/FTM4_CH6/ADC0_SE4/ADC1_SE14 PTD0/FTM0_CH2/FTM2_CH0/TRACE_D0/FXIO_D0 {3,9}
BLE_UART_TX 77 138 SAI 15 16 R107 0 TRACE
{3,9,13} PTB1/LPSPI0_SOUT PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/FTM4_CH5/ADC0_SE5/ADC1_SE15 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/LPSPI1_SOUT/FTM1_FLT2/SAI0_D2 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/SAI0_D2 {3,9} PTE4/TRACE_D1/FTM2_CH2/CAN0_RX/FXIO_D6 {2,3}
ECU_EXT_ADC1 68 137 SAI 17 18 R108 0 TRACE
{3,9} PTB2/LPSPI0_SCK PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE6 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/LPSPI1_PCS0/FTM1_FLT1/SAI0_D1 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/SAI0_D1 {3,8,9} PTD11/MII_RMII_TX_CLK/QSPI_A_IO0 {3,4}
ECU_EXT_ADC2 63 122 19 20 R109 0 TRACE
{3,9} PTB3/LPSPI0_SIN PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE7 PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/SAI1_SYNC/ADC1_SE10 PTE2/LPSPI0_SOUT/FTM3_CH6/SAI1_SYNC/ADC1_SE10 {3,9} PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 {3,9}
ENET QSPI 41 21
{3,4} PTB4/MII_RMII_MDIO/QSPI_B_IO0 40 PTB4/FTM0_CH4/LPSPI0_SOUT/MII_RMII_MDIO/TRGMUX_IN1/QSPI_B_IO0 PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/CMP0_OUT 9 TRACE
PTE3/FTM0_FLT0/FTM2_FLT0/CMP0_OUT {3,9}
{3,4} PTB5/MII_RMII_MDC PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0/MII_RMII_MDC PTE4/TRACE_D1/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT PTE4/TRACE_D1/FTM2_CH2/CAN0_RX/FXIO_D6 {2,3} HDR_2X10
18 8 R110
{3} PTB6_XTAL PTB6/LPI2C0_SDA/XTAL PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN PTE5/TCLK2/FTM2_CH3/CAN0_TX/FXIO_D7 {2,3}
17 121 10K
{3} PTB7_EXTAL PTB7/LPI2C0_SCL/EXTAL PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 {3,9}
111 87
{3,9} PTB8/FTM3_CH0/SAI1_BCLK PTB8/FTM3_CH0/SAI1_BCLK PTE7/FTM0_CH7/FTM3_FLT0 PTE7/FTM0_CH7/FTM3_FLT0 {3,9}
109 39
{3,9} PTB9/FTM3_CH1/LPI2C0_SCLS PTB9/FTM3_CH1/LPI2C0_SCLS/SAI1_D0 PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 {3,9}
108 30
{3,9} PTB10/FTM3_CH2/LPI2C0_SDAS PTB10/FTM3_CH2/LPI2C0_SDAS/SAI1_MCLK PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 {3,9}
TJA1043_EN 107 6
{3,9,12} PTB11/FTM3_CH3/LPI2C0_HREQ PTB11/FTM3_CH3/LPI2C0_HREQ PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT4 PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4 {3,9}
CAN2_RX 98 5
{3,9,12} PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX/FTM6_FLT1/ADC1_SE7 PTE11/LPSPI2_PCS0/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5 PTE11/FTM2_CH5/FXIO_D5 {3,9}
CAN2_TX 97 23 4G_UART_TX
{3,9,12} PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/FTM6_FLT0/ADC1_SE8/ADC0_SE8 PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 {3,9,13}
TJA1043_ERR_N 96 7
{3,9,12} PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 {3,9}
TJA1043_STB_N 95 20
{3,9,12} PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 PTE14/FTM0_FLT1/FTM2_FLT1 PTE14/FTM0_FLT1/FTM2_FLT1 {3,9}
R111 0 PTB16 94 2
{9} PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15 PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15 PTE15/LPUART1_CTS/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2/TRGMUX_OUT6 PTE15/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2 {3,9}
93 1
{3,9} PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 PTE16/LPUART1_RTS/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3/TRGMUX_OUT7 PTE16/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3 {3,9}
36 125
{3,9} PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 PTE19/FTM7_CH7/ADC1_SE25 PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25 {2,3,9}
ECU_EXT_PWM_IN1 37 126
{3,4,9,14} PTB20/FTM6_CH0/ADC0_SE17 PTB20/FTM6_CH0/ADC0_SE17 PTE20/FTM4_CH0/ADC1_SE26 PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26 {2,3,9}
ECU_EXT_PWM_IN2 38 128 PTE21 R112 0
{3,9,14} PTB21/FTM6_CH1/ADC0_SE18 PTB21/FTM6_CH1/ADC0_SE18 PTE21/FTM4_CH1/ADC1_SE27 PTE21/FTM4_CH1/FTM4_CH1/ADC1_SE27 {9}
58 129 PTE22 R113 0
{3,9} PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTE22/FTM4_CH2/ADC1_SE28 PTE22/FTM4_CH2/FTM4_CH2/ADC1_SE28 {9}
60 131 PTE23 R114 0
{3,9} PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 PTE23/FTM4_CH3/ADC1_SE29 PTE23/FTM4_CH3/FTM4_CH3/ADC1_SE29 {9}
ENET_SPI_CS0 62 132
{3,9} PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 PTE24/FTM4_CH4/CAN2_TX/ADC1_SE30 PTE24/FTM4_CH4/CAN2_TX/FTM4_CH4/ADC1_SE30 {3,9}
ENET_SPI_MISO 64 133
{3,9} PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTE25/FTM4_CH5/CAN2_RX/ADC1_SE31 PTE25/FTM4_CH5/CAN2_RX/CAN2_RX/FTM4_CH5/ADC1_SE31 {3,9}
ENET_SPI_MOSI 65
{3,6,9} PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23
ENET_SPI_SCK 69 R115 0
{3,9} PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 LED_RED {11}
FS32K148UJT0VLQT R116 0
LED_GREEN {11}
R118 0
LED_BLUE {11}
{3,11} ADC_POT R117 0 DNP FS32K148UJT0VLQT
U10D
U10C
4
ENET QSPI 53 PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/TRACE_D0/FXIO_D0/TRGMUX_OUT1 3 SAI PTD0/FTM0_CH2/FTM2_CH0/TRACE_D0/FXIO_D0 {3,9}
{3,4} PTC0/MII_RMII_RXD1/QSPI_B_RWDS PTC0/FTM0_CH0/LPSPI2_SIN/MII_RMII_RXD1/MII_RMII_RXD0/FTM1_CH6/QSPI_B_RWDS/ADC0_SE8 PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK/FXIO_D1/TRGMUX_OUT2 PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK {3,8,9}
ENET QSPI 52 102 4G_RELOAD
{3,4} PTC1/MII_RMII_RXD0/QSPI_B_SCK PTC1/FTM0_CH1/LPSPI2_SOUT/MII_RMII_RXD1/MII_RMII_RXD0/FTM1_CH7/QSPI_B_SCK/ADC0_SE9 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/ADC1_SE2 {3,9,13}
ENET QSPI 43 101 4G_RESET
{3,4} PTC2/MII_RMII_TXD0/QSPI_A_IO3 PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/MII_RMII_TXD0/TRACE_CLKOUT/QSPI_A_IO3/ADC0_SE10/CMP0_IN5 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/NMI/ADC1_SE3 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/ADC1_SE3 {3,9,13}
ENET QSPI 42 100 4G_POWER_KEY
{3,4} PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3 JTAG 140 PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3/ADC0_SE11/CMP0_IN4 PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE6 46 ENET QSPI PTD4/FTM0_FLT3/ADC1_SE6 {3,9,13}
{3} PTC4/FTM1_CH0/RTC_CLKOUT/JTAG_TCLK/SWD_CLK PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2 PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/MII_TXD3/TRGMUX_IN7/QSPI_B_IO2 PTD5/MII_TXD3/QSPI_B_IO2 {3,4}
JTAG 139 45 ENET QSPI
{3} PTC5/FTM2_CH0/RTC_CLKOUT/JTAG_TDI PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI PTD6/LPUART2_RX/FTM2_FLT2/MII_TXD2/QSPI_B_IO1/CMP0_IN7 PTD6/MII_TXD2/QSPI_B_IO1 {3,4}
CAN1_RX 118 44 ENET QSPI
{3,9,12} PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2 PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4 PTD7/LPUART2_TX/FTM2_FLT3/MII_RMII_TXD1/TRACE_D0/QSPI_A_IO1/CMP0_IN6 PTD7/MII_RMII_TXD1//QSPI_A_IO1 {3,4}
CAN1_TX 117 55 ENET QSPI
{3,9,12} PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3 PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5 PTD8/LPI2C1_SDA/MII_RXD3/FTM2_FLT2/FXIO_D1/FTM1_CH4/QSPI_B_IO5 PTD8/MII_RXD3/QSPI_B_IO5 {3,4}
GPS_UART_TX 81 54 ENET QSPI
{3,9,13} PTC8/LPUART1_RX PTC8/LPUART1_RX/FTM1_FLT0/FTM5_CH1/LPUART0_CTS PTD9/LPI2C1_SCL/FXIO_D0/FTM2_FLT3/MII_RXD2/FTM1_CH5/QSPI_B_IO4 PTD9/MII_RXD2/QSPI_B_IO4 {3,4}
GPS_UART_RX 80 49
{3,9,13} PTC9/LPUART1_TX PTC9/LPUART1_TX/FTM1_FLT1/FTM5_CH0/LPUART0_RTS PTD10/FTM2_CH0/FTM2_QD_PHB/TRACE_D3/MII_RX_CLK/CLKOUT/QSPI_A_SCK PTD10/MII_RX_CLK/QSPI_A_SCK {3,4}
GPS_PPS 75 48 ENET QSPI TRACE
{3,9,13} PTC10/FTM3_CH4/TRGMUX_IN11 PTC10/FTM3_CH4/TRGMUX_IN11 PTD11/FTM2_CH1/FTM2_QD_PHA/TRACE_D2/MII_RMII_TX_CLK/LPUART2_CTS/QSPI_A_IO0 PTD11/MII_RMII_TX_CLK/QSPI_A_IO0 {3,4}
TJA1044_STB 74 47 ENET QSPI
{3,9,12} PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 PTD12/FTM2_CH2/LPI2C1_HREQ/TRACE_D1/MII_RMII_TX_EN/LPUART2_RTS/QSPI_A_IO2 PTD12/MII_RMII_TX_EN/QSPI_A_IO2 {3,4}
R119 0 PTC12 71 35
{9} PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT {3,9}
R120 0 PTC13 70 34
{9} PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT {3,9}
61 29 TRACE
{3,9} PTC14/FTM1_CH2/LPSPI2_PCS0/ADC0_SE12 ENET QSPI 59 PTC14/FTM1_CH2/LPSPI2_PCS0/MII_COL/TRGMUX_IN9/ADC0_SE12 PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 28 TRACE
PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 {3,9}
{3,9} PTC15/FTM1_CH3/LPSPI2_SCK/QSPI_B_CS PTC15/FTM1_CH3/LPSPI2_SCK/MII_CRS/TRGMUX_IN8/QSPI_B_CS/ADC0_SE13 PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/CMP0_RRT/TRACE_CLKOUT PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/TRACE_CLKOUT {3,9}
ENET QSPI 57 25 4G_UART_RX
{3,4} PTC16/MII_RMII_RX_ER/QSPI_B_IO7 PTC16/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS/MII_RMII_RX_ER/QSPI_B_IO7/ADC0_SE14 PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 {3,9,13}
ENET QSPI 56 88
{3,4} PTC17/MII_RMII_RX_DV/QSPI_B_IO6 72 PTC17/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS/MII_RMII_RX_DV/QSPI_B_IO6/ADC0_SE15 PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 89 RTC_ACC_I2C_SCL PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 {3,9}
{3,9} PTC19/FTM7_CH5/ADC0_SE25 PTC19/FTM7_CH5/LPSPI2_PCS1/ADC0_SE25 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 {3,5,9}
C 73 99 ACC_INT1 C
{3,9} PTC23/LPSPI0_SCK/ADC0_SE26 PTC23/LPSPI0_SCK/ADC0_SE26 PTD22/FTM6_CH3/ADC1_SE18 PTD22/FTM6_CH3/FTM6_CH3/ADC1_SE18 {3,5,9}
76 103 ACC_INT2
{3,9} PTC27/FTM4_CH4/FTM4_CH4/ADC0_SE27 PTC27/FTM4_CH4/ADC0_SE27 PTD23/FTM6_CH4/ADC1_SE19 PTD23/FTM6_CH4/FTM6_CH4/ADC1_SE19 {3,5,9}
R121 0 PTC28 79 106
{9} PTC28/FTM4_CH7/FTM4_CH7/ADC0_SE28 PTC28/FTM4_CH7/ADC0_SE28 PTD24/FTM6_CH5/ADC1_SE20 PTD24/FTM6_CH5/FTM6_CH5/ADC1_SE20 {3,9}
82 110 ECU_EXT_HS1_DIAG
{3,9} PTC29/FTM5_CH2/FTM5_CH2/ADC0_SE29 PTC29/FTM5_CH2/ADC0_SE29 PTD27/FTM7_CH0/ADC1_SE21 PTD27/FTM7_CH0/FTM7_CH0/ADC1_SE21 {3,9,14}
84 112 ECU_EXT_HS1
{3,9} PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/FXIO_D0/ADC0_SE30 PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/ADC0_SE30 PTD28/FTM7_CH1/ADC1_SE22 PTD28/FTM7_CH1/FTM7_CH1/ADC1_SE22 {3,9,14}
RTC_ACC_I2C_SDA 86 114 ECU_EXT_HS2_DIAG
{3,5,9} PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/FXIO_D1/ADC0_SE31 PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/ADC0_SE31 PTD29/FTM7_CH2/ADC1_SE23 PTD29/FTM7_CH2/FTM7_CH2/ADC1_SE23 {3,6,9,14}
116 ECU_EXT_HS2
PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 {3,9,14}
FS32K148UJT0VLQT
FS32K148UJT0VLQT
{11} PTC12/BTN0 R122 0
{11} PTC13/BTN1 R123 0
{3,11} ADC_POT R124 0

VDD_MCU VDDA_MCU
S32K148 Microcontroller
U11A 176pins LQFP
TOUCH PTA0 140
TOUCH PTA1 138 PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN0
126 PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN1
{2,3,8,9} PTA2/LPUART0_RX PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT/FXIO_D4/LPUART0_RX/ADC1_SE0
125
{2,3,8,9} PTA3/LPUART0_TX PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1
JTAG 173 18
{3} PTA4/CMP0_OUT/JTAG_TMS/SWD_DIO PTA4/CMP0_OUT/EWM_OUT/JTAG_TMS/SWD_DIO VDD1
170 39
{2,3,4,9,11,13} PTA5/TCLK1_2/RESET PTA5/TCLK1/RESET VDD2
104 59
{3,9,14} PTA6/FTM0_FLT1 PTA6/FTM0_FLT1/LPSPI1_PCS1/FTM5_CH5/LPUART1_CTS/ADC0_SE2 VDD3
102 77
{3,9,14} PTA7/FTM0_FLT2 PTA7/FTM0_FLT2/FTM5_CH3/RTC_CLKIN/LPUART1_RTS/ADC0_SE3 VDD4
SBC_LIN2RX 176 110
{2,3,9} PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3 PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3/FTM4_FLT1 VDD5
SBC_LIN2TX 175 129
{2,3,9} PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2 PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3/FTM4_FLT0 VDD6
JTAG 164 152
{3} PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO VDD7
SAI 163 172
{3,8,9} PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC VDD8
162 TPAD22
{3,8,9} PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/SAI0_BCLK PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/FTM2_QD_PHB/SAI0_BCLK
SAI 158 20
{3,8,9} PTA13/FTM1_CH7/FTM2_QD_PHA/SAI0_D0 PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS/FTM2_QD_PHA/SAI0_D0 VDDA
SAI 155
{3,9} PTA14/FTM0_FLT0/FTM3_FLT1/SAI0_D3 PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/SAI0_D3 VREFH_MCU
TOUCH PTA15 148 21
TOUCH PTA16 146 PTA15/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3/FTM7_FLT0/ADC1_SE12 VREFH
ENET QSPI 111 PTA16/FTM1_CH3/LPSPI1_PCS2/ADC1_SE13 22
{3,4,9} PTA17/FTM0_CH6/ENET_RESET PTA17/FTM0_CH6/FTM3_FLT0/EWM_OUT/FTM5_FLT0 VREFL
1
{9} PTA18/FTM4_CH0/LPUART1_TX/LPSPI1_SOUT/FTM6_CH0 2 PTA18/FTM4_CH0/LPUART1_TX/LPSPI1_SOUT/FTM6_CH0
{9} PTA19/FTM4_CH1/LPUART1_RX/LPSPI1_SCK PTA19/FTM4_CH1/LPUART1_RX/LPSPI1_SCK
3 19
{9} PTA20/FTM4_CH2/LPSPI1_SIN PTA20/FTM4_CH2/LPSPI1_SIN VSS1
6 23
{9} PTA21/FTM4_CH3/FXIO_D0/LPSPI1_PCS0 PTA21/FTM4_CH3/FXIO_D0/LPSPI1_PCS0 VSS2
9 38
{9} PTA22/FTM4_CH4/FXIO_D1/LPSPI1_PCS1 PTA22/FTM4_CH4/FXIO_D1/LPSPI1_PCS1 VSS3
13 58
{9} PTA23/FTM4_CH6/FXIO_D2 PTA23/FTM4_CH6/FXIO_D2 VSS4
16 76
{9} PTA24/FTM4_CH7/FXIO_D3 PTA24/FTM4_CH7/FXIO_D3 VSS5
17 109
{3,4,9} PTA25/FTM5_CH0 PTA25/FTM5_CH0 VSS6
SBC_SPI_CS 26 130
{2,3,9} PTA26/FTM5_CH1/LPSPI1_PCS0 PTA26/FTM5_CH1/LPSPI1_PCS0/LPSPI0_PCS0 VSS7
SBC_SPI_MISO 29 151
{2,3,9} PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX/CAN0_TX VSS8
SBC_SPI_CLK 31 171
{2,3,9} PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX/CAN0_RX VSS9
SBC_SPI_MOSI 33
{2,3,9} PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN
34
{3,9} PTA30/FTM5_CH5 PTA30/FTM5_CH5/LPUART2_RX/LPSPI0_SOUT
40
{3,9} PTA31/FTM5_CH6 PTA31/FTM5_CH6/LPSPI0_PCS1

FS32K148UJT0VLUT
DNP
U11B

BLE_UART_RX 97 U11E
{3,9,13} PTB0/SBC_LPSPI0_PCS0 PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/FTM4_CH6/ADC0_SE4/ADC1_SE14
B BLE_UART_TX 96 B
{3,9,13} PTB1/LPSPI0_SOUT PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/FTM4_CH5/ADC0_SE5/ADC1_SE15
78 166 SAI
{3,9} PTB2/LPSPI0_SCK PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE6 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/LPSPI1_SOUT/FTM1_FLT2/SAI0_D2 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/SAI0_D2 {3,9}
73 165 SAI
{3,9} PTB3/LPSPI0_SIN PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE7 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/LPSPI1_PCS0/FTM1_FLT1/SAI0_D1 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/SAI0_D1 {3,8,9}
ENET QSPI 49 150
{3,4} PTB4/MII_RMII_MDIO/QSPI_B_IO0 48 PTB4/FTM0_CH4/LPSPI0_SOUT/MII_RMII_MDIO/TRGMUX_IN1/QSPI_B_IO0 PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/SAI1_SYNC/ADC1_SE10 28 PTE2/LPSPI0_SOUT/FTM3_CH6/SAI1_SYNC/ADC1_SE10 {3,9}
{3,4} PTB5/MII_RMII_MDC PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0/MII_RMII_MDC PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/CMP0_OUT PTE3/FTM0_FLT0/FTM2_FLT0/CMP0_OUT {3,9}
25 15 TRACE
{3} PTB6_XTAL PTB6/LPI2C0_SDA/XTAL PTE4/TRACE_D1/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT PTE4/TRACE_D1/FTM2_CH2/CAN0_RX/FXIO_D6 {2,3}
24 14
{3} PTB7_EXTAL PTB7/LPI2C0_SCL/EXTAL PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN PTE5/TCLK2/FTM2_CH3/CAN0_TX/FXIO_D7 {2,3}
136 149
{3,9} PTB8/FTM3_CH0/SAI1_BCLK PTB8/FTM3_CH0/SAI1_BCLK PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 {3,9}
ENET_I2C_SCL 133 106
{3,9} PTB9/FTM3_CH1/LPI2C0_SCLS PTB9/FTM3_CH1/LPI2C0_SCLS/SAI1_D0 PTE7/FTM0_CH7/FTM3_FLT0 PTE7/FTM0_CH7/FTM3_FLT0 {3,9}
ENET_I2C_SDA 131 47
{3,9} PTB10/FTM3_CH2/LPI2C0_SDAS PTB10/FTM3_CH2/LPI2C0_SDAS/SAI1_MCLK PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 {3,9}
TJA1043_EN 128 37
{3,9,12} PTB11/FTM3_CH3/LPI2C0_HREQ PTB11/FTM3_CH3/LPI2C0_HREQ PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 {3,9}
CAN2_RX 119 11 ENET_SPI_CS1
{3,9,12} PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX/FTM6_FLT1/ADC1_SE7 PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT4 PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4 {3,9}
CAN2_TX 118 10
{3,9,12} PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/FTM6_FLT0/ADC1_SE8/ADC0_SE8 PTE11/LPSPI2_PCS0/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5 PTE11/FTM2_CH5/FXIO_D5 {3,9}
TJA1043_ERR_N 116 30
{3,9,12} PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 {3,9,13}
TJA1043_STB_N 115 12 ENET_SPI_CS2
{3,9,12} PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 {3,9}
PTB16 114 27
112 PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15 PTE14/FTM0_FLT1/FTM2_FLT1 5 PTE14/FTM0_FLT1/FTM2_FLT1 {3,9}
{3,9} PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 PTE15/LPUART1_CTS/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2/TRGMUX_OUT6 PTE15/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2 {3,9}
43 4
{3,9} PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 PTE16/LPUART1_RTS/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3/TRGMUX_OUT7 PTE16/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3 {3,9}
44 145
{9} PTB19/FTM5_CH7 PTB19/FTM5_CH7 PTE17/FTM7_CH5/FXIO_D5 PTE17/FTM7_CH5/FXIO_D5 {9}
45 147
{3,4,9,14} PTB20/FTM6_CH0/ADC0_SE17 PTB20/FTM6_CH0/ADC0_SE17 PTE18/FTM7_CH6/FXIO_D4 PTE18/FTM7_CH6/FXIO_D4 {9}
46 153
{3,9,14} PTB21/FTM6_CH1/ADC0_SE18 PTB21/FTM6_CH1/ADC0_SE18 PTE19/FTM7_CH7/ADC1_SE25 PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25 {2,3,9}
66 154
{3,9} PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTE20/FTM4_CH0/ADC1_SE26 PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26 {2,3,9}
68 156 PTE21
{3,9} PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 PTE21/FTM4_CH1/ADC1_SE27
69 157 PTE22
{9} PTB24/FTM6_CH4 PTB24/FTM6_CH4 PTE22/FTM4_CH2/ADC1_SE28
71 159 PTE23
{3,9} PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 PTE23/FTM4_CH3/ADC1_SE29
72 160
{9} PTB26/FTM6_CH6 PTB26/FTM6_CH6 PTE24/FTM4_CH4/CAN2_TX/ADC1_SE30 PTE24/FTM4_CH4/CAN2_TX/FTM4_CH4/ADC1_SE30 {3,9}
ENET_SPI_MISO 74 161
{3,9} PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTE25/FTM4_CH5/CAN2_RX/ADC1_SE31 PTE25/FTM4_CH5/CAN2_RX/CAN2_RX/FTM4_CH5/ADC1_SE31 {3,9}
ENET_SPI_MOSI 75 167
{3,6,9} PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 PTE26/FTM4_CH6 PTE26/FTM4_CH6 {9}
ENET_SPI_SCK 79 174
{3,9} PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 PTE27/FTM4_CH7 PTE27/FTM4_CH7 {9}
80
{9} PTB30/FTM7_CH2 PTB30/FTM7_CH2
82
{9} PTB31/FTM7_CH3 PTB31/FTM7_CH3 FS32K148UJT0VLUT
DNP
FS32K148UJT0VLUT
DNP
U11C
U11D
ENET QSPI 61
{3,4} PTC0/MII_RMII_RXD1/QSPI_B_RWDS PTC0/FTM0_CH0/LPSPI2_SIN/MII_RMII_RXD1/MII_RMII_RXD0/FTM1_CH6/QSPI_B_RWDS/ADC0_SE8
ENET QSPI 60 8
{3,4} PTC1/MII_RMII_RXD0/QSPI_B_SCK PTC1/FTM0_CH1/LPSPI2_SOUT/MII_RMII_RXD1/MII_RMII_RXD0/FTM1_CH7/QSPI_B_SCK/ADC0_SE9 PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/TRACE_D0/FXIO_D0/TRGMUX_OUT1 PTD0/FTM0_CH2/FTM2_CH0/TRACE_D0/FXIO_D0 {3,9}
ENET QSPI 51 7 SAI
{3,4} PTC2/MII_RMII_TXD0/QSPI_A_IO3 PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/MII_RMII_TXD0/TRACE_CLKOUT/QSPI_A_IO3/ADC0_SE10/CMP0_IN5 PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK/FXIO_D1/TRGMUX_OUT2 PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK {3,8,9}
ENET QSPI 50 123
{3,4} PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3 JTAG 169 PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3/ADC0_SE11/CMP0_IN4 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2 122 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/ADC1_SE2 {3,9,13}
{3} PTC4/FTM1_CH0/RTC_CLKOUT/JTAG_TCLK/SWD_CLK PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/NMI/ADC1_SE3 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/ADC1_SE3 {3,9,13}
JTAG 168 121
{3} PTC5/FTM2_CH0/RTC_CLKOUT/JTAG_TDI PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE6 PTD4/FTM0_FLT3/ADC1_SE6 {3,9,13}
CAN1_RX 144 54 ENET QSPI
{3,9,12} PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2 PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4 PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/MII_TXD3/TRGMUX_IN7/QSPI_B_IO2 PTD5/MII_TXD3/QSPI_B_IO2 {3,4}
CAN1_TX 143 53 ENET QSPI
{3,9,12} PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3 PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5 PTD6/LPUART2_RX/FTM2_FLT2/MII_TXD2/QSPI_B_IO1/CMP0_IN7 PTD6/MII_TXD2/QSPI_B_IO1 {3,4}
SBC GPS_UART_TX 100 52 ENET QSPI
{3,9,13} PTC8/LPUART1_RX PTC8/LPUART1_RX/FTM1_FLT0/FTM5_CH1/LPUART0_CTS PTD7/LPUART2_TX/FTM2_FLT3/MII_RMII_TXD1/TRACE_D0/QSPI_A_IO1/CMP0_IN6 PTD7/MII_RMII_TXD1//QSPI_A_IO1 {3,4}
SBC GPS_UART_RX 99 63 ENET QSPI
{3,9,13} PTC9/LPUART1_TX PTC9/LPUART1_TX/FTM1_FLT1/FTM5_CH0/LPUART0_RTS PTD8/LPI2C1_SDA/MII_RXD3/FTM2_FLT2/FXIO_D1/FTM1_CH4/QSPI_B_IO5 PTD8/MII_RXD3/QSPI_B_IO5 {3,4}
GPS_PPS 94 62 ENET QSPI
{3,9,13} PTC10/FTM3_CH4/TRGMUX_IN11 PTC10/FTM3_CH4/TRGMUX_IN11 PTD9/LPI2C1_SCL/FXIO_D0/FTM2_FLT3/MII_RXD2/FTM1_CH5/QSPI_B_IO4 PTD9/MII_RXD2/QSPI_B_IO4 {3,4}
TJA1044_STB 92 57
{3,9,12} PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 PTD10/FTM2_CH0/FTM2_QD_PHB/TRACE_D3/MII_RX_CLK/CLKOUT/QSPI_A_SCK PTD10/MII_RX_CLK/QSPI_A_SCK {3,4}
PTC12 84 56
ENET QSPI TRACE
PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS PTD11/FTM2_CH1/FTM2_QD_PHA/TRACE_D2/MII_RMII_TX_CLK/LPUART2_CTS/QSPI_A_IO0 PTD11/MII_RMII_TX_CLK/QSPI_A_IO0 {3,4}
PTC13 81 55 ENET QSPI
PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS PTD12/FTM2_CH2/LPI2C1_HREQ/TRACE_D1/MII_RMII_TX_EN/LPUART2_RTS/QSPI_A_IO2 PTD12/MII_RMII_TX_EN/QSPI_A_IO2 {3,4}
70 42
{3,9} PTC14/FTM1_CH2/LPSPI2_PCS0/ADC0_SE12 ENET QSPI 67 PTC14/FTM1_CH2/LPSPI2_PCS0/MII_COL/TRGMUX_IN9/ADC0_SE12 PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT 41 PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT {3,9}
{3,9} PTC15/FTM1_CH3/LPSPI2_SCK/QSPI_B_CS PTC15/FTM1_CH3/LPSPI2_SCK/MII_CRS/TRGMUX_IN8/QSPI_B_CS/ADC0_SE13 PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT {3,9}
ENET QSPI 65 36 TRACE
{3,4} PTC16/MII_RMII_RX_ER/QSPI_B_IO7 PTC16/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS/MII_RMII_RX_ER/QSPI_B_IO7/ADC0_SE14 PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 {3,9}
ENET QSPI 64 35 TRACE
{3,4} PTC17/MII_RMII_RX_DV/QSPI_B_IO6 83 PTC17/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS/MII_RMII_RX_DV/QSPI_B_IO6/ADC0_SE15 PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/CMP0_RRT/TRACE_CLKOUT 32 PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/TRACE_CLKOUT {3,9}
{9} PTC18/FTM7_CH4 PTC18/FTM7_CH4 PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 {3,9,13}
85 107
{3,9} PTC19/FTM7_CH5/ADC0_SE25 PTC19/FTM7_CH5/LPSPI2_PCS1/ADC0_SE25 PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 {3,9}
86 108
{9} PTC20/FTM7_CH6 PTC20/FTM7_CH6 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 {3,5,9}
87 113
{9} PTC21/FTM7_CH7/FTM7_FLT0 PTC21/FTM7_CH7/FTM7_FLT0 PTD20/FTM6_CH1 PTD20/FTM6_CH1 {9}
88 117
{9} PTC22/FTM7_FLT1 PTC22/FTM7_FLT1 PTD21/FTM6_CH2 PTD21/FTM6_CH2 {9}
89 120
{3,9} PTC23/LPSPI0_SCK/ADC0_SE26 PTC23/LPSPI0_SCK/ADC0_SE26 PTD22/FTM6_CH3/ADC1_SE18 PTD22/FTM6_CH3/FTM6_CH3/ADC1_SE18 {3,5,9}
90 124
{9} PTC24/FTM4_CH0 PTC24/FTM4_CH0 PTD23/FTM6_CH4/ADC1_SE19 PTD23/FTM6_CH4/FTM6_CH4/ADC1_SE19 {3,5,9}
91 127
{9} PTC25/FTM4_CH1 PTC25/FTM4_CH1 PTD24/FTM6_CH5/ADC1_SE20 PTD24/FTM6_CH5/FTM6_CH5/ADC1_SE20 {3,9}
93 132
{9} PTC26/FTM4_CH3 PTC26/FTM4_CH3 PTD25/FTM6_CH6 PTD25/FTM6_CH6 {9}
95 134
{3,9} PTC27/FTM4_CH4/FTM4_CH4/ADC0_SE27 PTC27/FTM4_CH4/ADC0_SE27 PTD26/FTM6_CH7/FXIO_D7 PTD26/FTM6_CH7/FXIO_D7 {9}
PTC28 98 135
101 PTC28/FTM4_CH7/ADC0_SE28 PTD27/FTM7_CH0/ADC1_SE21 137 PTD27/FTM7_CH0/FTM7_CH0/ADC1_SE21 {3,9,14}
{3,9} PTC29/FTM5_CH2/FTM5_CH2/ADC0_SE29 PTC29/FTM5_CH2/ADC0_SE29 PTD28/FTM7_CH1/ADC1_SE22 PTD28/FTM7_CH1/FTM7_CH1/ADC1_SE22 {3,9,14}
103 139
{3,9} PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/FXIO_D0/ADC0_SE30 PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/ADC0_SE30 PTD29/FTM7_CH2/ADC1_SE23 PTD29/FTM7_CH2/FTM7_CH2/ADC1_SE23 {3,6,9,14}
105 141
{3,5,9} PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/FXIO_D1/ADC0_SE31 PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/ADC0_SE31 PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 {3,9,14}
142
PTD31/FTM7_CH4/FXIO_D6/FTM6_FLT0 PTD31/FTM7_CH4/FXIO_D6/FTM6_FLT0 {9}
FS32K148UJT0VLUT
DNP FS32K148UJT0VLUT
DNP

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
S32K148-T-BOX
Page Title:
S32K148 MCUs
Size Document Number Rev
E SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 3 of 14

5 4 3 2 1
 5 4 3 2 1

D D

VDD_MCU_PERH FER_BEAD TPAD23 VCCA_VTRANSL

L5 30 OHM
3.3 V / 5.0V TPAD24 P3V3_SW
MCU Reference VCCB_VTRANSL
C72 C73 C74 C75 C76 C77 C78 C79 R125 0603 0
10uF 1000PF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C80 C81 C82 C83 C84 C85 C86 C87
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1000PF 10uF
TPAD25

R128 0
{3,9} PTA25/FTM5_CH0 R129 0
DNP

ENTHERNET Lines
ENABLED by
R130 R131 R132 R133 R134 R135 R136 R138 Default

14

1
51K 51K 51K 51K U40 51K 51K 51K 51K
DNP DNP DNP DNP DNP DNP DNP DNP

VCCB

VCCA
ENET QSPI R137 0 PTD9/MII_RXD2/QSPI_B_IO4__A 13 2 PTD9/MII_RXD2/QSPI_B_IO4__B R139 0 ENET
{3} PTD9/MII_RXD2/QSPI_B_IO4 ENET QSPI PTD8/MII_RXD3/QSPI_B_IO5__A 12 B1 A1 3 PTD8/MII_RXD3/QSPI_B_IO5__B PTD9/MII_RXD2 {6}
R140 0 R141 0 ENET
{3} PTD8/MII_RXD3/QSPI_B_IO5 ENET QSPI PTC17/MII_RMII_RX_DV/QSPI_B_IO6__A 11 B2 A2 4 PTC17/MII_RMII_RX_DV/QSPI_B_IO6__B PTD8/MII_RXD3 {6}
R142 0 R143 0 ENET
{3} PTC17/MII_RMII_RX_DV/QSPI_B_IO6 PTC16/MII_RMII_RX_ER/QSPI_B_IO7__A B3 A3 PTC16/MII_RMII_RX_ER/QSPI_B_IO7__B PTC17/MII_RMII_RX_DV {6}
ENET QSPI R144 0 10 5 R145 0 ENET
{3} PTC16/MII_RMII_RX_ER/QSPI_B_IO7 B4 A4 PTC16/MII_RMII_RX_ER {6}

GND2
GND1
6 8
9 NC1 OE
NC2
C C

15
7
NTB0104BQ

R146 R147 R148 R149 R150 R154 R151 R152

14

1
4.70K 4.70K 4.70K 4.70K U41 4.70K 4.70K 4.70K 4.70K

HyperFLASH &

VCCB

VCCA
ENET QSPI R153 0 PTB4/MII_RMII_MDIO/QSPI_B_IO0__A 13 2 PTB4/MII_RMII_MDIO/QSPI_B_IO0__B R155 0 ENET
{3} PTB4/MII_RMII_MDIO/QSPI_B_IO0 ENET QSPI R156 0 PTD6/MII_TXD2/QSPI_B_IO1__A 12 B1 A1 3 PTD6/MII_TXD2/QSPI_B_IO1__B R157 0 ENET PTB4/MII_RMII_MDIO {6} Ethernet Connector
S32K148 {3} PTD6/MII_TXD2/QSPI_B_IO1
{3} PTD5/MII_TXD3/QSPI_B_IO2
ENET QSPI R158 0 PTD5/MII_TXD3/QSPI_B_IO2__A 11 B2
B3
A2
A3
4 PTD5/MII_TXD3/QSPI_B_IO2__B R159 0 ENET PTD6/MII_TXD2 {6}
PTD5/MII_TXD3 {6}
ENET QSPI R160 0 PTD7/MII_RMII_TXD1//QSPI_A_IO1__A 10 5 PTD7/MII_RMII_TXD1//QSPI_A_IO1__B
MCU SIGNALS {3} PTD7/MII_RMII_TXD1//QSPI_A_IO1 B4 A4 R161 0 DNP HYPFLASH
PTD7/QSPI_A_IO1 {7}
6 8 R162 0 ENET
NC1 OE PTD7/MII_RMII_TXD1 {6}

EPAD
9

GND
NC2

NTS0104BQ

15
7
R163 R164 R165 R166 R167 R168 R169 R170

14

1
51K 51K 51K 51K U42 51K 51K 51K 51K
DNP DNP DNP DNP DNP DNP DNP DNP

VCCB

VCCA
ENET QSPI R171 0 PTC0/MII_RMII_RXD1/QSPI_B_RWDS__A 13 2 PTC0/MII_RMII_RXD1/QSPI_B_RWDS__B R172 0 ENET
{3} PTC0/MII_RMII_RXD1/QSPI_B_RWDS PTC1/MII_RMII_RXD0/QSPI_B_SCK__A B1 A1 PTC1/MII_RMII_RXD0/QSPI_B_SCK__B PTC0/MII_RMII_RXD1 {6}
ENET QSPI R173 0 12 3 R174 0 ENET
{3} PTC1/MII_RMII_RXD0/QSPI_B_SCK PTC2/MII_RMII_TXD0/QSPI_A_IO3__A B2 A2 PTC2/MII_RMII_TXD0/QSPI_A_IO3__B PTC1/MII_RMII_RXD0 {6}
ENET QSPI R175 0 11 4
{3} PTC2/MII_RMII_TXD0/QSPI_A_IO3 PTD10/MII_RX_CLK/QSPI_A_SCK__A B3 A3 PTD10/MII_RX_CLK/QSPI_A_SCK__B
ENET QSPI R176 0 10 5 R177 0 ENET
{3} PTD10/MII_RX_CLK/QSPI_A_SCK B4 A4 PTC2/MII_RMII_TXD0 {6}
R178 0 DNP HYPFLASH
PTC2/QSPI_A_IO3 {7}

GND2
GND1
6 8
9 NC1 OE R179 0 ENET
NC2 PTD10/MII_RX_CLK {6}
R188 0 DNP HYPFLASH
PTD10/QSPI_A_SCK {7}

15
7
NTB0104BQ

R180 R181 R182 R183 R184 R185 R186 R187

14

1
51K 51K 51K 51K U43 51K 51K 51K 51K
DNP DNP DNP DNP DNP DNP

VCCB

VCCA
ENET QSPI R189 0 PTD12/MII_RMII_TX_EN/QSPI_A_IO2__A 13 2 PTD12/MII_RMII_TX_EN/QSPI_A_IO2__B R190 0 ENET
{3} PTD12/MII_RMII_TX_EN/QSPI_A_IO2 PTD11/MII_RMII_TX_CLK/QSPI_A_IO0__A B1 A1 PTD11/MII_RMII_TX_CLK/QSPI_A_IO0__B PTD12/MII_RMII_TX_EN {6}
ENET QSPI TRACE R191 0 12 3 R192 0 DNP HYPFLASH
B
{3} PTD11/MII_RMII_TX_CLK/QSPI_A_IO0 PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3__A B2 A2 PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3__B PTD12/QSPI_A_IO2 {7} B
ENET QSPI R193 0 11 4
{3} PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3 10 B3 A3 5 R194 0 ENET
PTD11/MII_RMII_TX_CLK {6}
B4 A4 R195 0 DNP HYPFLASH
PTD11/QSPI_A_IO0 {7}

GND2
GND1
6 8
9 NC1 OE R196 0 ENET
NC2 PTC3/MII_TX_ER {6}
R201 0 DNP HYPFLASH
PTC3/QSPI_A_CS {7}

15
7
NTB0104BQ

R197 R198 R199 R200 R202 R203 R204 R205

14

1
4.70K 4.70K 4.70K 4.70K U44 4.70K 4.70K 4.70K 4.70K

VCCB

VCCA
R206 0 PTB5/MII_RMII_MDC__A 13 2
{3} PTB5/MII_RMII_MDC PTB20/FTM6_CH0/ADC0_SE17__A B1 A1 PTB5/ENET_MII_RMII_MDC {6}
ENET QSPI R207 0 DNP 12 3
{3,9,14} PTB20/FTM6_CH0/ADC0_SE17 ENETSW_RESET_A B2 A2 PTB20/FTM6_CH0/ENET_INT {6}
ENET QSPI R208 0 11 4
{3,9} PTA17/FTM0_CH6/ENET_RESET B3 A3 ENETSW_RESET {6}
R209 0 DNP 10 5
{2,3,9,11,13} PTA5/TCLK1_2/RESET B4 A4
6 8
NC1 OE

EPAD
9

GND
NC2

NTS0104BQ

15
7
R210 C88
51K DNP
10uF

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
S32K148-T-BOX
Page Title:
MUXDMUX
Size Document Number Rev
D SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 4 of 14

5 4 3 2 1
 5 4 3 2 1

D
RTC and Accelerator circuit D

P3V3_SW P3V3_SW

C89
P3V3_SW 0.1UF C90
4.7uF
R211 R212 U18

14
1
4.70K 4.70K
C91 VDD_MCU_PERH VDD_MCU

VDD
VDDIO
J34

8
U17 0.1UF
2

1 R213 I2C_SCL_3V 4 11 ACC_INT1_3V HDR TH 1X3

VDD
QZ1 OSCI 7 4.70K I2C_SDA_3V 6 SCL INT1 9 ACC_INT2_3V
2 CLKOUT SDA INT2
32.768KHZ
1

OSCO P3V3_SW 3

3
2
1
I2C_SDA_3V 5 R214 7 NC3 8 Y4
SDA 3 RTC_INT_3V SA0 NC8 13 R486 0 3 4
{3,9,14} PTA6/FTM0_FLT1

VSS
I2C_SCL_3V 6 INT 4.70K NC13 15 CLKOE VDD
SCL 2 NC15 16
BYP NC16

GND1
GND3
GND4
PCA85063ATT 2 1 R487 0
4
GND CLKOUT PTA7/FTM0_FLT2 {3,9,14}

32.7680KHZ
C92

5
10
12
0.1UF MMA8452Q

This active 32.768KHz oscillator

is provided for S32K148 internal
RTC module low-power performance
C PCA85063A Device Address = 0x51 MMA8452AQ Device Address = 0x1C with SA0=1 assess. C

level shifter
VDD_MCU_PERH P3V3_SW
B B

R215 R216 R217 R218

U19
10K 10K 10K 10K

1 8
VCCA VCCB
R219 0 RTC_ACC_I2C_SCL 2 7 I2C_SCL_3V
{3,9} PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 RTC_ACC_I2C_SDA 3 A1 B1 6 I2C_SDA_3V
{3,9} PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/FXIO_D1/ADC0_SE31 R220 0
A2 B2
C93 4 5
0.1UF GND OE C94
0.1UF
NTSX2102GU8H

VDD_MCU_PERH P3V3_SW

R221 R222 R223 R224

U20
10K 10K 10K 10K

1 8
VCCA VCCB
R225 0 ACC_INT1 2 7 ACC_INT1_3V
{3,9} PTD22/FTM6_CH3/FTM6_CH3/ADC1_SE18 ACC_INT2 A1 B1 ACC_INT2_3V
R226 0 3 6 R227 DNP 0
{3,9} PTD23/FTM6_CH4/FTM6_CH4/ADC1_SE19 A2 B2
C95 4 5 R228 0 RTC_INT_3V
0.1UF GND OE C96
0.1UF
A NTSX2102GU8H A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
S32K148-T-BOX
Page Title:
RTC AND ACCELERATOR
Size Document Number Rev
C SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 5 of 14

5 4 3 2 1
 5 4 3 2 1

P3V3_SW
L6
Place 0.47uF near pin 7 1 2

C97
120OHM
Ethernet (PHY Address is 00101) P3V3_SW
L7
0.47UF
L8
1 2 1 2
Place 0.1uF near VDDIO Pins
120OHM C299 C99 C100 C101 120OHM
C102
0.1UF 0.1UF
D D
22uF 0.1UF 0.1UF
16V (0603 (0603 (0603
50V) 50V) 50V)
L9 TPH1
VSUP
1 2 Place 0.1uF near pins 11 and 14

C103

1
120OHM
0.1UF
P3V3_SW ENETSW_INH {2,6}
R494 C104 C105
GND R493
0.47UF 0.47UF
10K 100K

PHY Address 00101

19
27

15

16

11
14
9

4
U21 GND GND
GND

VDDIO_1
VDDIO_2

VDDD_3V3

VDDA_3V3

VDDD_1V8

SEL_1V8

VDDA_TX1
VDDA_TX2
VBAT
{4} PTB20/FTM6_CH0/ENET_INT R229 0 2
R231 R232 R233 0 1 INT
{4} PTB5/ENET_MII_RMII_MDC MDC
4.70K R230 0 36
{4} PTB4/MII_RMII_MDIO MDIO
4.70K
R234 0 8
{6} ENETSW_WAKE WAKE_IN_OUT 10
R237 51 3 INH
{4} ENETSW_RESET RST ENET_TX_P FL1 ENET_TRX_P
P3V3_SW R238 10K 35 12 2 3 C107 ENET_TRX_P {14}
EN TRX_P 0.1UF
24 13 ENET_TX_N 1 4 C108 ENET_TRX_N
{4} PTC1/MII_RMII_RXD0 RXD0/PHYAD0 TRX_M ENET_TRX_N {14}
{4} PTC0/MII_RMII_RXD1 23 0.1UF
22 RXD1/PHYAD1 200uH @ 100KHz
{4} PTD9/MII_RXD2 RXD2/CONFIG0
21
{4} PTD8/MII_RXD3 RXD3/CONFIG1 R242 R243
R241 0 34
{4} PTC3/MII_TX_ER TXER 1.0K 1.0K
{4} PTD12/MII_RMII_TX_EN 29
33 TXEN 6 R244 0 C110 15PF
{4} PTC2/MII_RMII_TXD0 TXD0 XI
{4} PTD7/MII_RMII_TXD1 32
31 TXD1 1 4
{4} PTD6/MII_TXD2 TXD2
{4} PTD5/MII_TXD3 30
TXD3 R248
C PULL UP as Master, {4} PTD11/MII_RMII_TX_CLK 28 C
PULL DOWN as Slave R245 R246 R247 TXC 5
18 XO 2 3 C111
{4} PTC17/MII_RMII_RX_DV RXDV/CRSDV/CONFIG2 4700 PF
R249 0 17 20 C112 15PF
{4} PTC16/MII_RMII_RX_ER RXER/CONFIG3/TXCLK CLK_IN_OUT
Autonomous operation 25 R250 0 100K
{4} PTD10/MII_RX_CLK RXC/REF_CLK 25MHz
4.70K 4.70K 4.70K Y2

GND
TSX-3225 25.0000MF10P-C

EP
DNP
P3V3_SW TJA1101

26
37
P3V3_SW P3V3_SW 4.70K R251
GND DNP

GND 4.70K R252

00 = Normal MII mode
01 = RMII mode(external 50MHz oscillator)
10 = RMII mode (external 25MHz crystal) P3V3_SW
11 = Reverse MII mode 4.70K R253
DNP

GND 4.70K R254

VDD_MCU_PERH TPAD26 VDD_MCU_ENETSW P3V3_ENETSW TPAD27 P3V3_SW P5V0

3.3 V / 5.0V
MCU Reference L12 0603
R255 0
R256 0603 DNP
FER_BEAD 30 OHM
C115 C113 C114 C116
1000PF 0.1UF 0.1UF 1000PF 3.3 Volts
by Default
U23
R408 R409 R406 R407
B B
10K 10K 10K 10K TPAD28
1 8
VCCA VCCB
R263 0 2 7
{3,9} PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 A1 B1 ENETSW_WAKE {6}
3 6
A2 B2
4 5
GND OE

NTSX2102GU8H

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
S32K148-T-BOX
Page Title:
ETHERNET
Size Document Number Rev
C SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 6 of 14

5 4 3 2 1
 5 4 3 2 1

D D

CMOS FLASH Memory 64M-BIT

TPAD30
L13 P3V3_SW
VCC_HYPRFLASH
FER_BEAD 30 OHM

R266 C120
10K 10uF C118 C119

8
U24 0.1UF 1000PF

VCC
C C
ENET HYPFLASH R268 33 OHM HYPFLASH/QSPI_A_IO0 5
{4} PTD11/QSPI_A_IO0 SI/SIO0

MX25L6433FM2R-08G
ENET HYPFLASH R270 33 OHM HYPFLASH/QSPI_A_IO1 2
{4} PTD7/QSPI_A_IO1 SO/SIO1
ENET HYPFLASH R269 33 OHM HYPFLASH/QSPI_A_IO2 3
{4} PTD12/QSPI_A_IO2 WP/SIO2
ENET HYPFLASH R271 33 OHM HYPFLASH/QSPI_A_IO3 7
{4} PTC2/QSPI_A_IO3 HOLD/SIO3
ENET HYPFLASH R272 33 OHM HYPFLASH/QSPI_A_CS 1
{4} PTC3/QSPI_A_CS CS
ENET HYPFLASH R273 33 OHM HYPFLASH/QSPI_A_SCK 6

GND
{4} PTD10/QSPI_A_SCK SCLK

4
B B

A A
ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
S32K148-T-BOX
Page Title:
HYPERFLASH
Size Document Number Rev
B SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 7 of 14

5 4 3 2 1
 5 4 3 2 1

SAI I2S Audio

P3V3_SW
L14
D C121 R274 1 2 D
P3V3_SW 1.0K
0.1UF
R275 120OHM

C122 C123 Place jack connectors

1.0K
0.1UF 0.1UF
beside each other

20

30

5
U25

VDDIO

VDDD

VDDA
LINE IN GND GND LINE OUT
AUD 4 J15
1 C124 1
GND GND
3 14 12 C125 1uF 3
R LINEIN_L LINEOUT_L R
4 4
2 1uF C126 2
L L
13 11 C127 1uF
J14 LINEIN_R LINEOUT_R
AUD 4
1uF External amplifier connection
External amplifier connection

Note: R1 only needed if

internal BIAS_RESISTOR
settings are not suitable.
P1 C128 0.1UF C319 220UF
1 15 6 AUDIO OUT

+
+ MIC HP_L

R276 J16
2 C320 220UF 1
- 16 2 3

+
MIC_BIAS HP_R R
EM6022P
P3V3_SW C129 4
2.2K 2
1uF L
4
R277 4.70K DNP HP_VGND
AUD 4
Headphone connection
R278 4.70K DNP R488
0
27
AUDIO_I2C_SDA CTRL_DATA 0603
29 10
C AUDIO_I2C_SCL CTRL_CLK VAG C
C130

P3V3_SW AUDIO_I2S_DOUT 25 0.1UF

I2S_DOUT 18
AUDIO_I2S_DIN 26 CPFILT
I2S_DIN
AUDIO_I2S_LRCLK 23 GND
C300 I2S_LRCLK 28
0.1UF AUDIO_I2S_SCLK 24 NC6 22
I2S_SCLK NC5
1

Y3 U49 19
1 4 NC4

CTRL_ADR0_CS
17
VDD1

VDD2

OE VDD R457 0 NC3 9

CTRL_MODE
R455 0 6 AUDIO_SYS_MCLK 21 NC2 8

GND3-PAD
2 3 3 Q0 SYS_MCLK NC1
GND OUT ICLK 7 R456 0 AUDIO_MCLK

AGND
Q1

GND2

GND1
12.288MHz
GND1

GND2

GND3

Layout Notes AGND (pin 7) should be "star"

31

32

33

7
SGTL5000 32QFN
74FCT38072S connected to the jack grounds for LINEIN and
4

LINEOUT, and to the VAG capacitor ground.

This node should via to the ground plane (or
GND GND GND GND GND GND
connected to ground) at a single point.
Add the reference clock circuit by NXA07657,
for S32K148 SAI module cannot generate MCLK
clock for common used audio sample in
SGTL5000, 2018.5.21
VDD_MCU_PERH TP62 P3V3_SW
L15
3.3 V / 5.0V
MCU Reference
FER_BEAD 30 OHM
C131 C132 C133 C134 C135 C136
10uF 0.1UF 0.1UF 0.1UF 0.1UF 10uF

B B

R280 R281 R282 R283 R285 R286 R287 R288

14

51K 51K 51K 51K U39 51K 51K 51K 51K

DNP DNP DNP DNP DNP DNP DNP DNP
VCCB

VCCA

R284 0 13 2 AUDIO_I2S_DOUT
{3,9} PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/SAI0_D1 12 B1 A1 3 AUDIO_I2S_DIN
{3,9} PTA13/FTM1_CH7/FTM2_QD_PHA/SAI0_D0 R289 0
R290 0 11 B2 A2 4 AUDIO_I2S_LRCLK
{3,9} PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC B3 A3 AUDIO_I2S_SCLK
R291 0 10 5
{3,9} PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/SAI0_BCLK B4 A4
GND2
GND1

6 8
9 NC1 OE P3V3_SW
NC2 R301 0
15
7

NTB0104BQ
R302 C137
51K DNP
10uF

VDD_MCU_PERH P3V3_SW

R399 R398 R396 R397

U37
10K 10K 10K 10K

1 8
VCCA VCCB
R299 0 2 7 AUDIO_I2C_SDA
{2,3,9} PTA2/LPUART0_RX A1 B1 AUDIO_I2C_SCL
R300 0 3 6
{2,3,9} PTA3/LPUART0_TX A2 B2
4 5
C180 GND OE C179
0.1UF 0.1UF
NTSX2102GU8H

VDD_MCU_PERH P3V3_SW

A R405 R404 R402 R403 A

U38
10K 10K 10K 10K

1 8
VCCA VCCB
R400 0 2 7 AUDIO_MCLK
{3,9} PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK A1 B1
3 6
A2 B2
4 5
C182 GND OE C181
0.1UF 0.1UF
NTSX2102GU8H

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
S32K148-T-BOX
Page Title:
SAI AUDIO
Size Document Number Rev
D SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 8 of 14

5 4 3 2 1
 5 4 3 2 1

PTD20/FTM6_CH1 {3}
PTD21/FTM6_CH2 {3}
PTB24/FTM6_CH4 {3}
PTB26/FTM6_CH6 {3}
PTB30/FTM7_CH2 {3}
R303 0 PTB31/FTM7_CH3 {3,9}
R304 0 DNP
D PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 {3,9,13} D

SAI
PTA13/FTM1_CH7/FTM2_QD_PHA/SAI0_D0 {3,8}
SAI
PTA14/FTM0_FLT0/FTM3_FLT1/SAI0_D3 {3}
PTE2/LPSPI0_SOUT/FTM3_CH6/SAI1_SYNC/ADC1_SE10 {3}
PTE3/FTM0_FLT0/FTM2_FLT0/CMP0_OUT {3}
PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 {3}
R305 0
PTE7/FTM0_CH7/FTM3_FLT0 {3,9}
PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 {3}
PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 {3}
R306 0 DNP
PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 {3,9,13}

PTE17/FTM7_CH5/FXIO_D5 {3}
PTE18/FTM7_CH6/FXIO_D4 {3}
PTB19/FTM5_CH7 {3}
PTE27/FTM4_CH7 {3}
PTE26/FTM4_CH6 {3}
PTA20/FTM4_CH2/LPSPI1_SIN {3}
PTA21/FTM4_CH3/FXIO_D0/LPSPI1_PCS0 {3}
{3} PTC18/FTM7_CH4 PTA22/FTM4_CH4/FXIO_D1/LPSPI1_PCS1 {3}
{3} PTC20/FTM7_CH6 PTA23/FTM4_CH6/FXIO_D2 {3}
{3}PTC21/FTM7_CH7/FTM7_FLT0 PTA24/FTM4_CH7/FXIO_D3 {3}
{3} PTC22/FTM7_FLT1
{3} PTC24/FTM4_CH0
{3} PTC25/FTM4_CH1
{3} PTC26/FTM4_CH3
{3} PTD25/FTM6_CH6 TRACE
{3} PTD26/FTM6_CH7/FXIO_D7 PTD0/FTM0_CH2/FTM2_CH0/TRACE_D0/FXIO_D0 {3}
{3} PTD31/FTM7_CH4/FXIO_D6/FTM6_FLT0 PTE14/FTM0_FLT1/FTM2_FLT1 {3}
PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 {3}
PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 {3,13}
PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2 {3,12}
{3,4} PTA25/FTM5_CH0 PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3 {3,12}
{3,14} PTA7/FTM0_FLT2 PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS {3}
{3,9,14} PTA6/FTM0_FLT1 PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS {3}
{3} PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 VDD_MCU_PERH
{3,9} PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1
{3,12} PTB11/FTM3_CH3/LPI2C0_HREQ
ENET_SPI_CS1
{3} PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4
C138
{3} PTE11/FTM2_CH5/FXIO_D5
{3,12} PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX 0.1UF
{3,12} PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX

C C

VDD_MCU_PERH

30
29
27
26
24
23
21
20
18
17
15
14
12
11

24
23
21
20
18
17
15
14
12
11

30
29
27
26
24
23
21
20
18
17
15
14
12
11
9
8
6
5
3
2

9
8
6
5
3
2

9
8
6
5
3
2
J17 J18 J19
ESQ-110-33-T-T ESQ-108-33-T-T ESQ-110-33-T-T
R307 R308 DNP
10K 10K DNP DNP
DNP DNP

28

25

22

19

16

13

10

22

19

16

13

10

28

25

22

19

16

13

10

1
TPAD31 {3} PTE15/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2
{3} PTE16/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3
VREFH
{3} VREFH
GPIO/SCK
{3} PTB2/LPSPI0_SCK
C139 {3} PTB3/LPSPI0_SIN
GPIO/MISO
PTB20/FTM6_CH0/ADC0_SE17 {3,4,14}
0.1UF {3,13} PTB1/LPSPI0_SOUT
GPIO/MOSI
PTB21/FTM6_CH1/ADC0_SE18 {3,14}
GPIO/SS
{3,13} PTB0/SBC_LPSPI0_PCS0 PTB10/FTM3_CH2/LPI2C0_SDAS {3}
PWM
{3} PTA30/FTM5_CH5 PTB9/FTM3_CH1/LPI2C0_SCLS {3}
PWM RX
{3} PTA31/FTM5_CH6 PTA19/FTM4_CH1/LPUART1_RX/LPSPI1_SCK {3}
PWM R309 0 DNP TX
{3,9} PTB31/FTM7_CH3 PTA18/FTM4_CH0/LPUART1_TX/LPSPI1_SOUT/FTM6_CH0 {3}
GND PWM R310 0 DNP SPI2_MISO RX4
{3,9} PTE7/FTM0_CH7/FTM3_FLT0 PWM SPI2_MOSI TX4 PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 {3}
{3} PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT PWM TRACE SPI2_SCK RXD5 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 {3,5}
{3} PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 PWM TRACE SPI2_SS TXD5 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/ADC1_SE2 {3,13}
{3} PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/TRACE_CLKOUT PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/ADC1_SE3 {3,13}
R311 0
{3,9,13} PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 PWM
{3,13} PTC10/FTM3_CH4/TRGMUX_IN11
PWM
{3,12} PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10
TX R312 0
{2,3,8} PTA3/LPUART0_TX
RX R313 0
{2,3,8} PTA2/LPUART0_RX
{3,13} PTC9/LPUART1_TX R314 0 DNP
{3,13} PTC8/LPUART1_RX R315 0 DNP

ADC
{2,3} PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26
ADC
{2,3} PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25
ADC
{3,5} PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/FXIO_D1/ADC0_SE31
ADC
{3} PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/FXIO_D0/ADC0_SE30
ADC
{3} PTC29/FTM5_CH2/FTM5_CH2/ADC0_SE29
ADC ADC
{3} PTC28/FTM4_CH7/FTM4_CH7/ADC0_SE28 PTE21/FTM4_CH1/FTM4_CH1/ADC1_SE27 {3}
ADC ADC
{3} PTC27/FTM4_CH4/FTM4_CH4/ADC0_SE27 PTE22/FTM4_CH2/FTM4_CH2/ADC1_SE28 {3}
ADC ADC
{3} PTC23/LPSPI0_SCK/ADC0_SE26 PTE23/FTM4_CH3/FTM4_CH3/ADC1_SE29 {3}
ADC
PTE24/FTM4_CH4/CAN2_TX/FTM4_CH4/ADC1_SE30 {3}
VBAT ADC
PTE25/FTM4_CH5/CAN2_RX/CAN2_RX/FTM4_CH5/ADC1_SE31 {3}
P5V0 P3V3_SW VDD_MCU_PERH ADC
PTC19/FTM7_CH5/ADC0_SE25 {3}
ADC
ADC PTC14/FTM1_CH2/LPSPI2_PCS0/ADC0_SE12 {3}
PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 {3,12}
ADC
0603
PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 {3,12}
{2,3,4,11,13} PTA5/TCLK1_2/RESET R316 0 ADC
PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15 {3}
R317 0603 DNP
B
{3,4} PTA17/FTM0_CH6/ENET_RESET B
VBAT VBAT
C140 C141 C142
0.1UF 0.1UF 0.1UF C143 C144
0.1UF 0.1UF

10

13

16

19

22

10

13

16

19

22

11
13
15
17
19
1

1
3
5
7
9
J22
J20 J21 CON 2X10
ESQ-108-33-T-T ESQ-108-33-T-T DNP
DNP DNP

2
4
6
8
10
12
14
16
18
20
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24

2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT {3}
SAI
PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK {3,8}
SAI
SAI PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/SAI0_D2 {3}
VDD_MCU_PERH
PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/SAI0_D1 {3,8}

{3} PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20
SAI
{3} PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/SAI0_BCLK {3,8}
ENET_SPI_SCK SAI C145
{3} PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC {3,8}
ENET_SPI_MISO 0.1UF
{3} PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTB8/FTM3_CH0/SAI1_BCLK {3}
ENET_SPI_MOSI
{3,6} PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 PTC15/FTM1_CH3/LPSPI2_SCK/QSPI_B_CS {3}
ENET_SPI_CS0
{3} PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21
SBC_LIN2RX
{2,3} PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3
SBC_LIN2TX
{2,3} PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2

{2} LIN1_OUT
{2} LIN2_OUT

{2} CANH_OUT
{2} CANL_OUT

ADC
{3,13} PTD4/FTM0_FLT3/ADC1_SE6 ADC
{3,5} PTD22/FTM6_CH3/FTM6_CH3/ADC1_SE18 ADC
{3,5} PTD23/FTM6_CH4/FTM6_CH4/ADC1_SE19 ADC
{3} PTD24/FTM6_CH5/FTM6_CH5/ADC1_SE20 ADC
{3,14} PTD27/FTM7_CH0/FTM7_CH0/ADC1_SE21 ADC
{3,14} PTD28/FTM7_CH1/FTM7_CH1/ADC1_SE22 ADC
{3,6,14} PTD29/FTM7_CH2/FTM7_CH2/ADC1_SE23 ADC
{3,14} PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24
A A

{3,9,14} PTA6/FTM0_FLT1 R318 DNP 0

{3,9} PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 R319 0
{2,3} PTA26/FTM5_CH1/LPSPI1_PCS0 R320 DNP 0 SBC_SPI_CS
SBC_SPI_MISO
{2,3} PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX
SBC_SPI_CLK
{2,3} PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX
SBC_SPI_MOSI
{2,3} PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN
{3} PTA0/ACMP0_IN0/ADC0_SE0
{3} PTA1/ACMP0_IN1/ADC0_SE1
{3} PTA15/FTM1_CH2/ADC1_SE12
{3} PTA16/FTM1_CH3/ADC1_SE13
ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
S32K148-T-BOX
Page Title:
I/O HEADERS
Size Document Number Rev
D SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 9 of 14

5 4 3 2 1
 5 4 3 2 1

D D

TPAD32

TOUCH
{3} TOUCH_ADC0_A
C146
4.7pF
Touch PADs
R321
4.7K

TPAD33
SW2
R322 0 1
{3} TOUCH_ADC1_A
C C
Electrode

TPAD34

{3} TOUCH_ADC0_B
C147
4.7pF
R323
4.7K

TPAD35
SW3
TOUCH R324 0 1
{3} TOUCH_ADC1_B

Electrode

B B

A A
ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
S32K148-T-BOX
Page Title:
TOUCHPAD
Size Document Number Rev
B SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 10 of 14

5 4 3 2 1
 5 4 3 2 1

D D

VDD_MCU_PERH
User buttons
P5V0 RGB LED SW4 EVQ-P2402W TP70

TP74 TP75 TP76 1 2 R325 PTC12/BTN0 {3}

D9 3 4 220

A1 C1 LEDRGB_RED R326 560

SW5 EVQ-P2402W TP78

A2 C2 LEDRGB_GREEN R327 560 1 2 R328 PTC13/BTN1 {3}

3 4 220

A3 C3 LEDRGB_BLUE R329 560 C148 C149 R330 R331 C150 C151

0.1UF 0.1UF 10K 10K 0.1UF 0.1UF

LED RED/GRN/BL

C C
TPAD36

3
R332 10K 1 Q3
{3} LED_BLUE
MMBT3904TT1G
R333 33K

2
VDD_MCU_PERH 3.3 V / 5.0V
TPAD37 MCU Reference
Potentiometer
3
R334 10K 1 Q4 R335 0603 0
{3} LED_GREEN
MMBT3904TT1G

1
R336 33K 2 TP79 TP80

TPAD38 R337 2 R338 ADC_POT {3}

3

5K 220
R339 10K 1 Q5
{3} LED_RED
MMBT3904TT1G C152 C153

3
R340 33K 0.1UF 0.1UF
2

B B

MCU reset bottom

VDD_MCU_PERH
D27
A C R410 330 R411 0 PTA5/TCLK1_2/RESET {2,3,4,9,13}

RED SW6

1 2 C183
3 4 0.1UF
A EVQ-P2402W A
ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
S32K148-T-BOX
Page Title:
USER PHERP
Size Document Number Rev
B SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 11 of 14

5 4 3 2 1
 5 4 3 2 1

CAN1 Physical Interface TJA1044T(SO-8 package) to compatiable with Stinger

P5V0

D D
C154 C155
10V 0.1UF VDD_MCU_PERH
2.2UF

5
U45 C156
R489 0603 DNP 100PF

VCC

VIO
R341 0 CAN1_TX 1 7 CAN1_H CAN1H
{3,9} PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3 TXD CANH CAN1H {14}
1 FL2 4
R343 0 CAN1_RX 4 R342
{3,9} PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2 RXD 2 3 120
R344 0 TJA1044_STB 8 6 CAN1_L ACT45B-110-2P-TL003 DNP
{3,9} PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 STB CANL CAN1L

GND
0603
CAN1L {14}
R490 DNP

2
TJA1044GT/3

2
C157
100PF
PESD2CAN
U29

3
C C

CAN2 Physical Interface with TJA1043TKY(HVSON-14 package) to compatiable with Stinger

VDD_MCU_PERH P5V0 VSUP

C159
C158 2.2UF R345
10nF 10V 1.0K
C162
C161 GND
C160 2.2UF
10nF 10V
10nF

10
5

3
GND U30
VCC
VIO

VBAT
R491 0603 DNP
C163 R346
R347 0 CAN2_TX 1 13 CAN2_H 100PF 60.4 CAN2H
{3,9} PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX TXD CANH CAN2H {14}
2 FL3 3
R348 0 TJA1043_EN 6 11 GND
B {3,9} PTB11/FTM3_CH3/LPI2C0_HREQ EN SPLIT B
1 4
12 CAN2_L ACT45B-110-2P-TL003 C164 R349 CAN2L
TJA1043_STB_N CANL CAN2L {14}
R350 0 14 4700 PF 60.4
{3,9} PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 STB TPH2 0603
R492 DNP

2
R351 100K R352 2.7K 8 GND
9 ERR
VSUP WAKE 7 C165
1

INH TJA1043_INH {2} 100PF

PESD2CAN
EPAD

4
GND

RXD GND U31

{3,9} PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX R353

3
TJA1043TKY
2
15

0 GND

{3,9} PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 R354 0

GND
CAN2_RX

TJA1043_ERR_N

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
S32K148-T-BOX
Page Title:
CAN BUS
Size Document Number Rev
C SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 12 of 14

5 4 3 2 1
 5 4 3 2 1

D D

Header two 1x12 for 4G module connection

Header 1x4 for BLE module connection VDD_MCU_PERH P3V3_SW P3V3_SW

J25
R355 R356 R357 R358 LINKA_LED 1
U32 LINKB_LED 2 1
10K 10K 10K 10K
3 PIN3 USB_D- not use
1 8 4 PIN4 USB_D+ not use
VDD_MCU_PERH P3V3_SW VCCA VCCB 5 PIN5 VCC_IO connect to 3.3V
R359 0 4G_UART_RX 2 7 UTXD3 6
{3,9} PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 4G_UART_TX 3 A1 B1 6 7
R362 0 URXD2
{3,9} PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 A2 B2 8
R360 R361 R363 R364
U33 4 5 C168 WORK_LED 9
10K 10K 10K 10K
C166 GND OE C167 0.1UF POWER_KEY_N 10
1 8 0.1UF 0.1UF 11
VCCA VCCB J26 NTSX2102GU8H 12
R365 0 BLE_UART_RX 2 7 BLE_UART_RX_3V 1 12
{3,9} PTB0/SBC_LPSPI0_PCS0 BLE_UART_TX A1 B1 BLE_UART_TX_3V
R366 0 3 6 2
{3,9} PTB1/LPSPI0_SOUT A2 B2 SKT_1x12
3
C170 4 5 4
GND OE P3V3_SW
0.1UF C169
0.1UF
CON_1X4
NTSX2102GU8H

VDD_MCU_PERH P3V3_SW
VSUP
J27
R367 R368 R369 R370 1 13
U34 C172 2 PIN13/14 VIN(12V power supply) use for module
10K 10K 10K 10K
+ C171 0.1UF NET_LED 3
1 8 220UF 4
VCCA VCCB 5 PIN16 VCAP(3.8V power supply) not use
R371 0 4G_RELOAD 2 7 M_RELOAD_N 6
{3,9} PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/ADC1_SE2 4G_RESET A1 B1 M_RESET_N
R372 0 3 6 7
{3,9} PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/ADC1_SE3 A2 B2 8
4 5 9
C R373 0402 DNP C173 GND OE C174 10 PIN20~23 are SIM card related not use C
{2,3,4,9,11} PTA5/TCLK1_2/RESET
0.1UF 0.1UF 11
NTSX2102GU8H 12 23

SKT_1x12

P5V0

Header 1x5 for GPS module connection

R374 R375 R376 R377
Power LED Indicators 560 560 560 560

A
LED_ORANGE

LED_ORANGE
D13 D14 D16
GREEN LED_YELLOW
VDD_MCU_PERH P3V3_SW
D15

C
R378 R379 R380 R381
U35
10K 10K 10K 10K
J28
1 8 TPAD39
VCCA VCCB

3
GPS_PPS_3V 1
R382 0 GPS_UART_TX 2 7 GPS_UART_TX_3V 2 LINKA_LED R383 10K 1 Q6
{3,9} PTC9/LPUART1_TX GPS_UART_RX A1 B1 GPS_UART_RX_3V
R384 0 3 6 3 MMBT3904TT1G
{3,9} PTC8/LPUART1_RX A2 B2 4 R385 33K

2
4 5 5
GND OE P3V3_SW
C175 C176
0.1UF 0.1UF
NTSX2102GU8H CON 1X5 TPAD40

3
LINKB_LED R386 10K 1 Q7
MMBT3904TT1G
R387 33K

2
VDD_MCU_PERH P3V3_SW
TPAD41

3
B R388 R389 WORK_LED R390 10K 1 Q8 B
U36 MMBT3904TT1G
10K 10K
R391 33K

2
1 8
VCCA VCCB
R392 0 GPS_PPS 2 7
{3,9} PTC10/FTM3_CH4/TRGMUX_IN11 4G_POWER_KEY A1 B1 POWER_KEY_N
R393 0 3 6 TPAD42
{3,9} PTD4/FTM0_FLT3/ADC1_SE6 A2 B2

3
4 5 NET_LED R394 10K 1 Q9
C177 GND OE C178 MMBT3904TT1G
0.1UF 0.1UF R395 33K

2
NTSX2102GU8H

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
S32K148-T-BOX
Page Title:
BLE GPS & 4G Modules
Size Document Number Rev
D SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 13 of 14

5 4 3 2 1
 5 4 3 2 1

VDD_MCU_PERH

HS1 VDD_MCU_PERH
PWM_IN_1
VSUP R484
R427 10.0K

1
10.0K Q12
R428
(HS1_DIAG) R439
{3,9} PTD27/FTM7_CH0/FTM7_CH0/ADC1_SE21 ECU_EXT_PWM_IN1
C274 {3,4,9} PTB20/FTM6_CH0/ADC0_SE17 R443 2 3 R436
D
1000PF U47 R426
D

5
6
7
8
1.0K AUIPS7091G 10.0K 0 0

C
DNP 1.0K C286

VCC1
VCC2
VCC3
VCC4
3 C283 2N7002BKW R438 10nF D24
GND DG 10nF
R429 10.0K BZX384-C30
DNP DNP
(HS1_ENABLE) 2 4 ECU_EXT_HS1

C
{3,9} PTD28/FTM7_CH1/FTM7_CH1/ADC1_SE22

A
IN OUT

GND
C276 D19
1.0K 1000PF BZX384-C30

A
GND

GND

VDD_MCU_PERH VDD_MCU_PERH
HS2
VSUP
R424
10.0K
PWM_IN_2
R430
R485
(HS2_DIAG) 10.0K
{3,6,9} PTD29/FTM7_CH2/FTM7_CH2/ADC1_SE23
C275

1
1000PF U48 R425 Q13

5
6
7
8
1.0K AUIPS7091G 10.0K
DNP

VCC1
VCC2
VCC3
VCC4
3
GND DG R444 0 R440 1.0K 2 3 R433 0 ECU_EXT_PWM_IN2
R431 {3,9} PTB21/FTM6_CH1/ADC0_SE18
2 4 ECU_EXT_HS2

C
{3,9} PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 (HS2_ENABLE) IN OUT
C C

GND
C277 D18 C284 2N7002BKW R434 C285 D17
1.0K 1000PF 10nF 10nF
BZX384-C30 10.0K BZX384-C30
DNP DNP

A
GND

GND

VDD_MCU_PERH C294
Analog IN 0.1UF
LIN1 Master option
GND

J32
8

HDR1X2
R419
VDD 2 VSUP
- R417 R451 TP82
R422 1
{3,9} PTB2/LPSPI0_SCK
3 D25

1
2
VSS
+
0 U46A A C 2K R447
C

1.0K R421 R454 2K R448

MCP6022-I/SN
4

C279 10.0K 100K D22 150.0K 470K PMEG3050EP VBAT J31

10nF C281 BZT52C3V3 1 16
GND
10nF 9
C322 CAN1H 2 17 CAN1L
{12} CAN1H CAN1L {12}
A

GND C296 2.2uF {2} ECU_EXT_LIN1 10

ECU_EXT_LIN1
GND GND 220PF DNP CAN2H 3 18 CAN2L
{12} CAN2H ECU_EXT_LIN2 CAN2L {12}
11
{2} ECU_EXT_LIN2 ECU_EXT_HS1 ECU_EXT_HS2
4 19
SBC_HVIO5_EXT 12
{2} SBC_HVIO5_EXT
{12} CAN0H CAN0H 5 20 CAN0L CAN0L {12}
B ECU_EXT_PWM_IN2 B
U46B 13
R420 6 ECU_EXT_ADC1 6 21
- R418 R452 ECU_EXT_PWM_IN1
{3,9} PTB3/LPSPI0_SIN R423 0 7 14
5 ECU_EXT_ADC2 7 22 ENET_TRX_P
+ ECU_EXT_5V ENET_TRX_P {6}
PVEXT_SBC 15
C

1.0K MCP6022-I/SN R412 R453 8 23 ENET_TRX_N

10.0K 470K ENET_TRX_N {6}
C280 100K D23 150.0K 0 R432
10nF C282 BZT52C3V3 PLUG 23 RA
10nF
LIN2 Master option
A

GND
GND GND
J33
VSUP HDR1X2

TP83
D26

1
2
A C 2K R449
2K R450
PMEG3050EP

C295 C321
220PF 2.2uF
DNP
ECU_EXT_PWM_IN1

ECU_EXT_PWM_IN2

SBC_HVIO5_EXT
ECU_EXT_ADC1

ECU_EXT_ADC2
ECU_EXT_LIN1

ECU_EXT_LIN2

ECU_EXT_HS1

ECU_EXT_HS2

CAN1L

CAN2L

ENET_TRX_N
ENET_TRX_P

ECU_EXT_5V
CAN1H

CAN2H

CAN0H

CAN0L

A C301 C302 C303 C304 C305 C306 C307 C308 C309 C310 C311 C313 C312 C314 C315 C316 C317 C318 A
DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP
100PF 100PF 100PF 100PF 100PF 100PF 100PF 100PF 100PF 100PF 10PF 10PF 100PF 100PF 100PF 100PF 100PF 100PF

Add the connector filter capcitor circuit for ESD protection by NXA07657, ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
and please place capcitor C301 to C318 near the connector J31 as much as
S32K148-T-BOX
possible, 2018.5.21 Page Title:
ECU CONNECTOR
Size Document Number Rev
C SCH-32232 PDF: SPF-32232 B1

Date: Monday, December 10, 2018 Sheet 14 of 14

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