MICROPROCESSORS

8086

MICROPROCESSORS
Lec.7
Dr. Abdallah Ramadan Fawzy
E-Mail: Abdallah.gad@must.edu.eg

The figures and text included in slides are borrowed from various books, websites, and
other sources for academic purposes only. The author do not claim any originality.
ORG 0000H ; Set the origin of the program to memory address 0000H
START: ; Label for the start of the program
MVI A, 0AH ; Load the value 0AH into register A
CPI 05H ; Compare the value in register A with 05H
JZ EQUAL ; Jump to the EQUAL label if the values are equal
JC LESS ; Jump to the LESS label if A is less than 05H
JMP GREATER ; Jump to the GREATER label if A is greater than 05H
EQUAL: ; Label for when the values are equal
MVI B, 01H ; Load the value 01H into register B
HLT ; Halt the program
LESS: ; Label for when A is less than 05H
MVI B, 02H ; Load the value 02H into register B
HLT ; Halt the program
GREATER: ; Label for when A is greater than 05H
MVI B, 03H ; Load the value 03H into register B
HLT ; Halt the program
END START ; End of the program
In this code, we start by loading the value 0AH into register A. We
then use the `CPI` instruction to compare the value in A with 05H.
If the values are equal, we jump to the `EQUAL` label. If A is less
than 05H, we jump to the `LESS` label. If A is greater than 05H, we
jump to the `GREATER` label.

At each of these labels, we perform a different action based on the

value of A. For example, if the values are equal, we load the value
01H into register B and halt the program. If A is less than 05H, we
load the value 02H into register B and halt the program. And if A is
greater than 05H, we load the value 03H into register B and halt
the program.

Note: This is just an example of how conditional instructions can

be used in 8085 assembly code. The specific actions performed at
each label will depend on the requirements of your program.
Sure! Conditional instructions in 8085 assembly language allow you
to execute different sets of instructions based on the condition of a
particular flag. Here's a brief overview of the most commonly used
conditional instructions in 8085:
- Jump if zero (JZ): This instruction jumps to a specified memory
address if the zero flag (Z) is set. The zero flag is set when the result
of an operation is zero.
- Jump if not zero (JNZ): This instruction jumps to a specified
memory address if the zero flag (Z) is not set.
- Jump if carry (JC): This instruction jumps to a specified memory
address if the carry flag (CY) is set. The carry flag is set when an
operation results in a carry-out or borrow.
- Jump if not carry (JNC): This instruction jumps to a specified
memory address if the carry flag (CY) is not set.
- Jump if positive (JP): This instruction jumps to a specified memory
address if the sign flag (S) is not set. The sign flag is set when the
result of an operation is negative.
- Jump if not positive (JM): This instruction jumps to a specified
memory address if the sign flag (S) is set.
- Jump if parity even (JPE): This instruction jumps to a specified
memory address if the parity flag (P) is set. The parity flag is set when
the result of an operation has an even number of 1s in its binary
representation.
- Jump if parity odd (JPO): This instruction jumps to a specified
memory address if the parity flag (P) is not set.
To use these instructions, you typically compare the result of an
operation with a particular value or check the state of a flag using a
CMP, CMA, or ANA instruction, and then use a conditional instruction
to jump to a particular memory address based on the state of the flag.
For example, in the code I provided earlier, we use the `CPI`
instruction to compare the value in register A with 05H, and then use
conditional instructions (`JZ`, `JC`, and `JMP`) to jump to different
labels based on the result of that comparison. This allows us to
execute different sets of instructions based on the value of A.
ORG 0000H ; Set the origin of the program to memory address
0000H
START: ; Label for the start of the program
MVI A, 0AH ; Load the value 0AH into register A
ANI 0FH ; Perform a bitwise AND operation with the value 0FH
JPE EVEN ; Jump to the EVEN label if the result has an even
number of 1s
JMP ODD ; Jump to the ODD label if the result has an odd
number of 1s
EVEN: ; Label for when the result has an even number of 1s
MVI B, 01H ; Load the value 01H into register B
HLT ; Halt the program
ODD: ; Label for when the result has an odd number of 1s
MVI B, 02H ; Load the value 02H into register B
HLT ; Halt the program
END START ; End of the program
In this code, we start by loading the value 0AH into register A. We then perform a
bitwise AND operation with the value 0FH using the `ANI` instruction. This
operation sets the high-order bits of A to zero, effectively limiting the range of
values that A can hold to between 0 and 0FH.

We then use the `JPE` instruction to check the parity flag (P), which is set when the
result of an operation has an even number of 1s in its binary representation. If the P
flag is set, we jump to the `EVEN` label. If the P flag is not set (i.e., the result has an
odd number of 1s), we jump to the `ODD` label.

At each of these labels, we perform a different action based on the parity of the
result. For example, if the result has an even number of 1s, we load the value 01H
into register B and halt the program. If the result has an odd number of 1s, we load
the value 02H into register B and halt the program.

Note that the `JPE` instruction is typically used to check the parity of the result of an
operation, rather than the value of a register. In this example, we use the `ANI`
instruction to limit the range of values that A can hold so that we can use the `JPE`
instruction to check the parity of the result.
Interrupt is a process where an external device can
get the attention of the microprocessor.
The process starts from the I/O device

Interrupts can be classified into two types:

Maskable(can be delayed)
Non-Maskable(can not be delayed)
• Interrupts can also be classified into:
Vectored(the address of the service routine is
hard-wired)
Non-vectored(the address of the service routine
needs to be supplied externally)
•An interrupt is considered to be an emergency signal.
–The Microprocessor should respond to it as soon as
possible.
– When the Microprocessor receives an interrupt signal,
it suspends the currently executing program and jumps
to an Interrupt Service Routine(ISR) to respond to the
incoming Interrupt.
–Each interrupt will most probably have its own ISR.
 Responding to interrupt
•Responding to an interrupt may be immediate or delayed
depending on whether the interrupt is maskable or non-
maskable and whether interrupts are being masked or not.
• There are two ways of redirecting the execution to the ISR
depending on whether the interrupt is vectored or non-
vectored.
–The vector is already known to the Microprocessor
–The device will have to supply the vector to
Microprocessor
 8085 Interrupt

The maskable interrupt process in the 8085 is controlled by

a single flip flop inside the microprocessor.
This Interrupt Enable flip flop is controlled using the two
instructions “EI” and “DI”.
• The 8085 has a single Non-Maskable interrupt.
The non-maskable interrupt is not affected by the value
of the Interrupt Enable flip flop.
8085 Interrupt

•The 8085 has 5 interrupt inputs.

–The INTR input.
–The INTR input is the only non-vectored interrupt.
–INTR is maskable using the EI/DI instruction pair.
–RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
– RST 5.5, RST 6.5, and RST 7.5 are all maskable.
–TRAP is the only non-maskableinterrupt in the 8085
–TRAP is also automatically vectored
8085 Interrupt
Interrupt Vector

An interrupt vector is a pointer to where the ISR is

stored in memory.
All interrupts (vectored or otherwise) are mapped onto
a memory area called the Interrupt Vector Table(IVT).
The IVT is usually located in memory page 00(0000H -
00FFH).
The purpose of the IVT is to hold the vectors that redirect the
microprocessor to the right place when an interrupt arrives.
The IVT is divided into several blocks. Each block is used by
one of the interrupts to hold its “vector”
 Non-Vectored Interrupt
1. The interrupt process should be enabled using the EI
instruction.
2. The 8085 checks for an interrupt during the execution of every
instruction.
3. If there is an interrupt, the microprocessor will complete the
executing instruction, and start a RESTART sequence.
4. The RESTART sequence resets the interrupt flip flopand
activates the interrupt acknowledge signal (INTA).
5. Upon receiving the INTA signal, the interrupting device is
expected to return the op-code of one of the 8 RST
instructions.
 Non-Vectored Interrupt

6. When the microprocessor executes the RST instruction

received from the device, it saves the address of the next
instruction on the stack and jumps to the appropriate
entry in the IVT.
7. The IVT entry must redirect the microprocessor to the
actual service routine.
8. The service routine must include the instruction EI to re-
enable the interrupt process.
9. At the end of the service routine, the RET instruction
returns the execution to where the program was
interrupted.
Masking

These three interrupts are masked at two levels:

Through the Interrupt Enable flip flop and the EI/DI
instructions.
The Interrupt Enable flip flop controls the whole
maskable interrupt process.
Through individual mask flip flops that control the
availability of the individual interrupts.
These flip flops control the interrupts individually.
Hardware of EI
 Manipulating the Mask

The Interrupt Enable flip flop is manipulated using the EI/DI

instructions.
The individual masks for RST 5.5, RST 6.5 and RST 7.5
are manipulated using the SIM instruction.
This instruction takes the bit pattern in the Accumulator
and applies it to the interrupt mask enabling and
disabling the specific interrupts.
SIM
 SIM and Interrupt Mask

Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is
the mask for RST 7.5.
If the mask bit is 0, the interrupt is available.
If the mask bit is 1, the interrupt is masked.
Bit 3 (Mask Set Enable -MSE) is an enable for setting the mask.
If it is set to 0 the mask is ignored and the old settings remain.
If it is set to 1, the new setting are applied.
The SIM instruction is used for multiple purposes and not only for
setting interrupt masks.
It is also used to control functionality such as Serial Data
Transmission.
Therefore, bit 3 is necessary to tell the microprocessor whether or
not the interrupt masks should be modified
Triggering Level

RST 7.5 is positive edge sensitive.

When a positive edge appears on the RST7.5 line, a logic 1 is stored
in the flip-flop as a “pending” interrupt.
Since the value has been stored in the flip flop, the line does not
have to be high when the microprocessor checks for the interrupt to
be recognized.
The line must go to zero and back to one before a new interrupt is
recognized.
RST 6.5 and RST 5.5 are level sensitive.
The interrupting signal must remain present until the microprocessor
checks for interrupts.
 Trap

TRAP is the only non-maskable interrupt.

It does not need to be enabled because it cannot be
disabled.
It has the highest priority amongst interrupts.
It is edge and level sensitive.
It needs to be high and stay high to be recognized. Once
it is recognized, it won’t be recognized again until it goes
low, then high again.
TRAP is usually used for power failure and emergency
shutoff.
Summary – Data transfer

MOV Move
MVI Move Immediate
LDA Load Accumulator Directly from Memory
STA Store Accumulator Directly in Memory
LHLD Load H & L Registers Directly from Memory
SHLD Store H & L Registers Directly in Memory
Summary Data transfer

An 'X' in the name of a data transfer instruction implies that it deals with
register pair (16-bits);

LXI Load Register Pair with Immediate data

LDAX Load Accumulator from Address in Register Pair
STAX Store Accumulator in Address in Register Pair
XCHG Exchange H & L with D & E
XTHL Exchange Top of Stack with H & L
Summary - Arithmetic Group
Add, Subtract, Increment / Decrement data in registers or memory.
ADD Add to Accumulator
ADI Add Immediate Data to Accumulator
ADC Add to Accumulator Using Carry Flag
ACI Add Immediate data to Accumulator Using Carry
SUB Subtract from Accumulator
SUI Subtract Immediate Data from Accumulator
SBB Subtract from Accumulator Using Borrow (Carry) Flag
SBI Subtract Immediate from Accumulator
Using Borrow (Carry) Flag
INR Increment Specified Byte by One
DCR Decrement Specified Byte by One
INX Increment Register Pair by One
DCX Decrement Register Pair by One
DAD Double Register Add; Add Content of Register Pair to H & L
Register Pair
Summary Logical Group

This group performs logical (Boolean) operations on data in registers

and memory and on condition flags.
These instructions enable you to set specific bits in the accumulator
ON or OFF.
ANA Logical AND with Accumulator
ANI Logical AND with Accumulator Using Immediate
Data
ORA Logical OR with Accumulator
OR Logical OR with Accumulator Using Immediate
Data
XRA Exclusive Logical OR with Accumulator
XRI Exclusive OR Using Immediate Data
The Compare instructions compare the content of an 8-bit value with the
contents of the accumulator;
CMP Compare
CPI Compare Using Immediate Data
The rotate instructions shift the contents of the accumulator one bit position to
the left or right:
RLC Rotate Accumulator Left
RRC Rotate Accumulator Right
RAL Rotate Left Through Carry
RAR Rotate Right Through Carry
Complement and carry flag instructions:
CMA Complement Accumulator
CMC Complement Carry Flag
STC Set Carry Flag
Summary - Branch Group

Unconditional branching
JMP Jump
CALL Call
RET Return
Conditions
NZ Not Zero (Z = 0)
Z Zero (Z = 1)
NC No Carry (C = 0)
C Carry (C = 1)
PO Parity Odd (P = 0)
PE Parity Even (P = 1)
P Plus (S = 0)
M Minus (S = 1)
Conditional branching
 Summary - Stack

PUSH Push Two bytes of Data onto the Stack

POP Pop Two Bytes of Data off the Stack
XTHL Exchange Top of Stack with H & L
SPHL Move content of H & L to Stack Pointer
I/0 instructions

IN Initiate Input Operation

OUT Initiate Output Operation
Summary -Machine Control instructions

EI Enable Interrupt System

DI Disable Interrupt System
HLT Halt
NOP No Operation