Microprocessor and Microcontroller Systems 4 Ree TOPIC 3 INSTRUCTION SET ARCHITECTURE Learning Objectives: At the end of this topic, students should be able to: 1. Analyze and interpret the instruction set architecture of a given microprocessor. 2. Explain the architecture of a microprocessor, including the fetch-decode- execute cycle. 3. Understand the different types of instructions, addressing modes, and their implications in programming. 4. \rite simple programs in assembly language for a specific microprocessor. Learning Discussions ‘A microprocessor instruction set architecture (ISA) is a set of rules and conventions that define the programming interface and the functionalities available to software developers and programmers. It serves as the interface between the hardware (microprocessor) and the software (programs written by developers) The ISA specifies the machine language instructions that the microprocessor can execute, along with addressing modes, data formats, and the organization of registers. It defines how instructions are encoded in binary and how they are executed by the microprocessor’s hardware. The ISA provides a standardized way for programmers to write software that can run on different microprocessor implementations with the same architecture. Instruction Set 7 It is the complete set of instructions that allows the microprocessor to manipulate data by moving it or processing it and to perform housekeeping functions. 7 The microprocessors instruction word is the same length as its data word EEE NOONMicroprocessor and Microcontroller Systems 1s Example: — 8-bit microprocessor is 8 bits long 16-bit microprocessor is 16 bits long @ Any microprocessor may use a number of instruction words to make up 2 complete instruction. ‘® The microprocessor’s instructions are decoded and carried out when an instruction is loaded into the microprocessors instruction register by the fetch cycle. During the execute cycle, the instruction decodes, and the control logic are used to make the microprocessor perform the function indicated by the instruction. [deh eel Get instruction from memory Decode instruction Seo Execute instruction ere) The Microprocessor's Fetch/Execute Cycle ‘/ A microprocessor instruction contains two pieces of information. First, it tells ‘the microprocessor what to do. Second, it tells the microprocessor the address of the data or target with the instruction. It must tell the microprocessor the location of the data to work on. 7+ An instruction can be broken into two parts called the op cade (operation code) and the address. 77 The op code tells the microprocessor what to do while the address tells the microprocessor where to take the action. Machine Code 7 The actual binary instruction. ENO,Mi icroprocessor and Microcontroller Systems 16 a Mnemonics @ Is an abbreviation that reminds us of what it stands for Example: MOV - copy LD - — oad JMP = jump Assembly Language 7 Assembly language is a low-level programming language that is specific to a particular computer architecture or microprocessor. It serves as an intermediary representation between machine code (bi 9 unit) and high-level inary code understood by the computer's central processin programming languages. Assembly language is a human-readable and writable representation of the machine code instructions that a particular processor understands. Assembler 7 Assembly language code needs to be translated into machine code for execution by the computer's CPU. This translation is done by a program called an assembler, The assembler converts the symbolic assembly language instructions into the binary code that the processor understands. Microprocessor's Basic Instruction types 4, Data Transfer Instructions allows the programmer to copy data from register to register and between registers and memory locations. The source data is copied into the destination. MOV instruction + Copies the second operand (source) to the first operand (destination). = The source operand can be an immediate value, general-purpose register or memory location. «| The destination register can be @ general-purpose register, or memory location. * Both operands must be the same size, which can be a byte or a word. These types of operands are supported: eeMicroprocessor and Microcontroller Systems 7 MOV REG, memory MOV memory, REG MOV REG, REG MOV memory, immediate MOV REG, immediate REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, Dl, SI, BP, SP. memory: [BX], [BX+Si+7], variable, etc... immediate: 5, -24, 3Fh, 100011016, etc. For segment registers only these types of MOV are supported: MOV SREG, memory MOV memory, SREG MOV REG, SREG MOV SREG, REG SREG: DS, ES, SS, and only as second operand: CS REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP. memory: [BX], [BX+SI+7], variable, etc... ‘The MOV instruction cannot be used to set the value of the CS and IP registers. 2. The Exchange Instructions are used to swap data between sets of registers. Example: XCHG DE, HL 3. The arithmetic and logical instructions allow the programmer to modify the data in a register or sometimes the data in the memory using the arithmetic ‘or logical operators: add, subtract, add with carry, subtract with cary, AND, OR, and Exclusive-OR (XOR). The Arithmetic and Logical Instruction Group also includes instructions, which let you increment or decrement the current value contained in a register cor memory location. They also include instructions, which allow the programmer to compare the value of a register or a memory location to the value in another register or memory location. The compare instruction only affects the microprocessor status register. Most Arithmetic and Logic Instructions affect the processor status register (or Flags) NicoMicroprocessor and Microcontroller Systems 8 15 OOOOssaee overlon Direction Interupt Trace Sign Zero As you may see there are 16 bits in this register, each bit is called a flag and can take a value of 1 or 0. Carry Flag (CF) - this fiag is set to 1 when there is an unsigned overflow. For example, when you add bytes 255 + 1 (result is not in range 0...255). When there is no overflow, this flag is set to 0. Zero Flag (ZF) - set to 1 when result is zero. For none zero result this flag is set to 0. set Sign Flag (SF) - set to 1 when result is negative. When result is positive to 0. Actually, this flag take the value of the most significant bit. Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when you add bytes 100 + 50 (result is not in range -128...127). Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in result, and to 0 when there is odd number of one bits. Even if result is a word only 8 low bits are analyzed. Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4 bits). Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from external devices. Direction Flag (DF) - this flag is used by some instructions to process data chains, when this flag is set to 0 - the processing is done forward, when this flag is set to 1 the processing is done backward. There are 3 groups of instructions. * First group: ADD, SUB, CMP, AND, TEST, OR, XOR These types of operands are supported: REG, memory memory, REG REG, REG eeMicroprocessor and Microcontroller Systems 9 Memory, immediate REG, immediate REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP. memory: [BX], [BX+SI+7], variable, etc. immediate: 5, -24, 3Fh, 10001101b, etc. ‘After operation between operands, result is always stored in first operand CMP and TEST instructions affect flags only and do not store a result (these instructions are used to make decisions during program execution). These instructions affect these flags only: CF, ZF, SF, OF, PF, AF. ADD - add second operand to first. SUB - Subtract second operand to first. CMP - Subtract second operand from first for flags only. AND - Logical AND between all bits of two operands. These rules apply: 1 AND 1 1 ANDO OAND1=0 QANDO TEST - The same as AND but for flags only. OR - Logical OR between all bits of two operands. These rules apply: 10R 10R OOR ORO=0 XOR - Logical XOR (exclusive OR) between all bits of two operands. These rules apply: 1XOR1=0 1XORO OXOR1 OXORO = Second group: MUL, IMUL, DIV, IDIV These types of operands are supported: REG memory, REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP. memory: [8X], [BX+S|*7], variable, etc. MUL and IMUL instructions affect these flags only: CF, OF noMicroprocessor and Microcontroller Systems 20 When result is over the operand size, these flags are set to 1, when result fits in operand size these flags are set to 0. For DIV and IDIV flags are undefined. MUL - Unsigned multiply: when operand is a byte: AX = AL * operand when operand is a word: (DX AX) = AX * operand IMUL - Signed multiply when operand is a byte: AX = AL * operand. when operand is a word: (DX AX) = AX * operand. DIV - Unsigned divide: ‘when operand is a byte: ‘AL= AX //operand AH = remainder (modulus) when operand is a word: ‘AX = (DX AX) / operand DX = remainder (modulus) IDIV - Signed divide: when operand is a byte: AL= AX/ operand AH = remainder (modulus) when operand is a word: AX = (DX AX) / operand DX = remainder (modulus) Third group: INC, DEC, NOT, NEG These types of operands are supported: REG memory REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP. memory: [BX], [BX+SI+7], variable, etc... INC, DEC instructions affect these flags only: ZF, SF, OF, PF, AF. NOT instruction does not affect any flags! NEG instruction affects these flags only: CF, ZF, SF, OF, PF, AF. NOT - Reverse each bit of operand NEG - Make operand negative (two's complement). Actually it reverses each bit of operand and then adds 1 to it. For example 5 will become -5, and -2 will become 2. iMicroprocessor and Microcontroller Systems a Program Flow Control Controlling the program flow is a very important thing, this is where your Program can make decisions according to certain conditions. The Jump Instructions are used to permanently change the program counter’s value. When you change the program counter’s value, you start executing a different part of the program. The new starting address is given as part of the jump instruction Two Kinds of Jump Instructions - Unconditional - simply changes the program counter's value. The basic instruction that transfers control to another point in the program is JMP. The basic syntax of JMP instruction JMP label To declare a label in your program, just type its name and add ":" to the fend, label can be any character combination, but it cannot start with a number, for example here are 3 legal label definitions: labelt: label2 a Label can be declared on a separate line or before any other instruction, for ‘example’ x1: MOV AX, 1 x2: MOV AX, 2 Here is an example of JMP instruction: ORG 100h MOV AX,5 — ; set AXto5. MOV BX,2 —; set BX to2. JMP calc; goto'‘calc’. back: JMP stop; go to'stop’. calc: ADD AX,BX — ; add BX to AX. JMP back —— ; go'back’. stop: RET ; return to operating system END ; directive to stop the compiler. ee oyMicroprocessor and Microcontroller Systems 2 a : Conditional ~ changes the program counters value ifthe conditional testis Example: JZ nn Note: PC = nn if zero bit is 1 The Microprocessor’s Addressing Modes Addressing Modes 7 Are different ways that the microprocessor uses fo access memory locations, 1. Inherent or Implied The address is contained in the instruction itself. The source of the data and the destination of the data are built into the instruction. It only requires one word. Example: NOP HLT RET 2. Immediate / Uses two-word instructions, The first word is instructions (op code), the second word is the immediate data to be acted on. Example: MOV CX, 4929 H ADD AX, 2387 H MOV AL, FFH 3. Direct Addressing 7 May use 2 or 3 bytes. The first is the op code, the second or third byte are memory address. Some manufacturers call 2-byte direct addressing as direct or page addressing while the 3-byte direct addressing as extended direct addressing. Ne TCPENTOONMicro, "Processor and Microcontroller Systems 2B Example: MOV AX, [1592H] MOV AL, [03004] 4. Register Indirect Addressing @ Another single word instruction. #¥ The instruction indicates which register contains the address of the needed data, Example: MOV AX, [BX] ; Suppose the register BX contains 4895H, then the contents 4895H are moved to AX ADD CX, [BX] 5. Indexed Addressing 7 Uses a special register called the index register. fit is done by adding the contents of the indexed addressing instructions’ second byte to the index register’s current contents. The resulting sum is used as a pointer to the address ‘of a memory location. ‘This is where the data to be operated on the instruction is stored. / Indexed addressing only works in microprocessors, which have an index register. > B-bit number added to the index register has a range of 60H to FFh is called an offset. This means indexed addressing permits pointing to 256 memory locations without changing the index register value. Example: MOV BX, [SI+16] ADD AL, [DI+16] 6. Based Register addressing mode 7e The effective address of an operand is determined by adding a fixed offset or displacement to the content of a base register. re aMicroprocessor and Microcontroller Systems 24 Example: MOV Dx, [8x+04) ADD CL, [Bx+08] 7. Register addressing mode 7 Operand is in a register Example: MOV CX, AX ADD BX, AX 8. Based index addressing mode Example: ADD CX, [AX+SI] MOV AX, [AX+DI] 9. Based indexed with displacement mode Example MOV AX, [BX+DI+08] ADD CX, [BX+SI+16]