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MP - Unit 4

Microprocessor notes on chapters

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Prathamesh Narale
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26 views

MP - Unit 4

Microprocessor notes on chapters

Uploaded by

Prathamesh Narale
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Basic Logic Instruction

 The basic logic instructions include AND, OR, Exclusive-OR, and NOT.
 Another logic instruction is TEST.
 NEG instruction which is somewhat similar to the NOT instruction.
 Logic operations provide binary bit control in low-level software.
 The logic instructions allow bits to be set, reset, or complemented.
 All logic instructions affect the flag bits.

AND
 Instruction performs Logic AND operation between Destination & Source
 PF, SF & ZF are updated
 Destination can be register or memory location.
 Source can be register or memory location.
 When both inputs are 1 output is 1 else 0
 Ex. AND AL, CL ; AL = AL AND CL
If AL = 47H = 0100 0111
& CL = 36H = 0011 0110
Then AL = 0000 0110 = 06 H

OR
 This instruction performs Logic OR operation between destination and source.
 Destination can be register or memory location.
 Source can be register or memory location.
 When either input is 1 output is 1 else 0
 Ex. OR AL, CL ; AL = AL OR CL
If AL = 47H = 0100 0111
& CL = 36H = 0011 0110
Then AL = 0111 0111 = 77H

NOT
 Performs the 1’s complement operation on the destination.
 The result is stored in destination
 Ex. NOT AX
If AL = 0100 0111
Then NOT AL = 1011 1000
EX - OR
 This instruction performs Logic XOR operation between Destination and source.
 Destination can be register or memory location.
 When both inputs are same output is 0 else 1
 Source can be register or memory location.
 Ex. XOR AL,CL ; AL = AL XOR CL
If AL = 47H = 0100 0111
& CL = 36H = 0011 0110
Then AL = 0111 0001

Test Instructions
 The TEST instruction performs the AND operation between destination and
source.
 Destination can be register or memory location.
 Source can be register or memory location.
 Result is not stored in register or memory location.
 A TEST only affects the condition of the flag register, which indicates the result
of the test.
 Uses the same addressing modes as that of AND instruction.
 ZF = 1(indicating a zero result) if the bit under test is a zero.
 ZF = 0(indicating a nonzero result) if the bit under test is not zero.

Shift & Rotate Instructions


 The shift & rotate instructions shift the bits in the destination operand by one or
more positions either to the left or right
 For a shift instruction, the bits shifted out are lost.
 These instructions can be used to multiply or divide by power of 2.
 Multiply – Shift Left
 Divide – Shift Right
 For a rotate instruction, bits shifted out from one end of the operand are put back
into the other end.
 SHL - Shift Logical Left
 SHR - Shift Logical Right
 SAL - Shift Arithmetic Left
 SAR - Shift Arithmetic Right
 ROL - Rotate Left
 ROR - Rotate Right
 RCL - Rotate Left Through Carry
 RCR - Rotate Right Through Carry
Shift Instructions
Rotate Instructions
1. RCL Instruction (Rotate Through Carry Left)
 RCL shifts each bit to the left
 Copies the carry flag to the least significant bit
 Copies the most significant bit to the carry flag.
 Ex.: CLC ; CF = 0
MOV BL, 88H ; CF, BL = 0 1000 1000
RCL BL, 1 ; CF, BL = 1 0001 0000
RCL BL, 1 ; CF, BL = 0 0010 0001

2. RCR Instruction (Rotate Through Carry Right)


 RCR shifts each bit to the right
 Copies the carry flag to the most significant bit
 Copies the least significant bit to the carry flag.
 Ex.: STC ; CF = 1
MOV AL, 10H ; CF, AL = 0001 0000 1
RCR AL, 1 ; CF, BL = 1000 1000 0

3. ROR Instruction (Rotate Right)


 ROR shifts each bit to the right
 No bits are lost
 Copies the least significant bit to both the carry flag and most significant bit.
 Ex.: MOV AL,F0H ; AL = 1111 0000
RCL AL, 3 ; AL = 0001 1110
4. ROL Instruction (Rotate Left)
 ROL shifts each bit to the left
 No bits are lost
 Copies the most significant bit to both the carry flag and least significant bit.
 Ex.: MOV AL,F0H ; AL = 1111 0000
RCL AL, 3 ; AL = 1000 0111

Unconditional Jump (JMP)


1. Short Jump
 2 byte instruction
 Allows jump to locations within +127 and -128 bytes

2. Near Jump
 3 byte instruction
 Allows jump to locations within +32kb and -32kb bytes

3. Far Jump
 5 byte instruction
 Allows jump to any locations within real memory system

Conditional Jump (Jump IF)


 Above & Below refer to comparison of two unsigned values.
 Greater & Less refer to comparison of two signed values.

MNEMONIC Jump IF

JA/JNBE Above/ not below or equal

JG/JNLE Greater/ not less or equal

JNC CF = 0

JE/JZ Equal/ Zero


Machine Control & Miscellaneous Instructions
1. HLT
 Stop fetching and execution of the instruction.
 Enters into HALT state
 Processor gets out of halt state when an interrupt or reset signal has occurred.

2. WAIT
 Pause fetching and execution of the instruction.
 Enters into IDLE state
 Comes out of this state when a high (1) signal is received from TEST pin or a
valid interrupt signal is received.
 Used to synchronize 8086 with peripheral devices.

3. ESC
 Used to pass instruction to a co-processor like 8087
 6 bit instruction is embedded ESC instruction.
 8086 treats ESC as NOP

4. LOCK
 In multiprocessor configuration.
 Different microprocessor share a system bus
 When a microprocessor needs exclusive use of the system bus for a particular
instruction.

5. NOP
 No operation is done
 3 clock cycles
 Time delay can be provided
 Does not affect any flag.

Basic Interrupt Processing


 An Interrupt is a special condition that arises during the working of
microprocessor.
 The microprocessor services it by executing a subroutine called Interrupt
Service Routine (ISR).
 There are 3 sources of Interrupt in 8086.

1. Hardware Interrupt
 These interrupts occurred by externally connected peripheral devices (Ex.
Keyboard).
 8086 has 2 pins to accept hardware interrupt NMI and INTR
2. Software Interrupt
 These interrupts are caused by writing the software interrupt instruction INTn
where ‘n’ can be any value from 0 to 255 (00H to FFH).

3. Internally Generated Interrupts


 8086 is interrupted when some special condition occurs while executing certain
instruction in the program.

INTERRUPT VECTOR TABLE

1. INT 0 (Divide Error)


 When the result of a division is large to be stored.

2. INT 1 (Single Stepping)


 Puts microprocessor in single stepping mode.

3. INT 2 (Non Maskable Interrupt)


 Non Maskable Interrupt.
4. INT 3 (Breakpoint Interrupt)
 Used to cause breakpoints in the program.

5. INT 4 (Overflow Interrupt)


 When Overflow Flag is set.

6. INT 5 to INT 31
 Reserved by INTEL for higher microprocessors like 80386, Pentium, etc.

7. INT 32 to INT 255


 User defined interrupts and software interrupts

Hardware Interrupt
1. NMI (Non Maskable Interrupt)
 High priority interrupt
 On receiving an interrupt on NMI line microprocessor executes INT 2.

2. INTR
 Low priority interrupt
 Maskable interrupt
 On receiving an interrupt on INTR line microprocessor executes 2 INTA pulse.
 1st INTA pulse- the interrupting device calculates the vector number
 2nd INTA pulse -the interrupting device sends the vector number ‘N’ to the
microprocessor.

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