OF eedadlts Page Normal = IDNo:--B LDR G9-Bane j= FAMILIARIZ ATION WITH XILINX [4.5 Tool! y FAN cl Procedure the proceclure te be -follocoect cfow c] Softcore and haveluave programs ave as sfellowos- al stepO— To staxt -the ZSE soptuave cfouble-click HP a] TsE project Navigatey Econ on your desktop. or sefect et Start > all programs > xlin TSE ojesign surte > TSE 4 elesign tools > project Navigator: aw SaPO— cveating a new project: = ~ = ie ip =~ = To cveak a neo profect uring a new progect wrfad do -the followéog ‘ : @ From project Navigator, select pile new project” .the new praect wrtavd oppeays. ® zn -the LocaGon Hitld- brows to the effvectory th exhich ou Save the praject . ® rn the name biel. enbr the project vertfy that HDL os Cyeatid as -the top level type om click next. Same ject ° The new Pred witoare = olevice peg paye ee the UL oe! following values Eo the New Project > product category : All > family : Spay tons + Device: X66 SLXUD5, RGUKT Basar Department of Electronice and Communication Engineering) @ a Experiment Name:- — package © ¢Sq324 > speed 2-3 —> Synthesis tool + xST Cvr pe | vert log) —> simulater > £sie (VHDL) Ver?log) > predewed banquege : VHDL or verilog depending en. Se this ewtll detmine the | cleft” fev all process that qenevats the HDL Language files. othe proper Ges can be left at -thety Anpoutt] values. © cl&ck next, then Yintsh conmplee the profect creatjoo A SGPO- To cveati the souvee file, ojo followtng : @ select progect > New source. Ahe neu Source cottava opens En ebich qou specify ry a | 4 | 4 the type Of source You cant to create. @® zn the Select source type page select vertlog enatule © Tn-the $%le name Held. entev pile mame. @® click next © Fo the define eodule POF, entey tio oput ports nemet a and b and an output port’ named por tk be debounc? component as fotos. > Fn the $IVSE three Port name bield. enty a bec -l_, set the clévectjon field +0 pur pov a,b ona , ev ouput & RGUKT Basar Department of Electronice and Communication Engineering,@© clich next to view a discr€ption of -the module. < @ ct&ch finish to open -the empty HIDL file cn the 7 Zs€ text eotitov. i stepOr lalstte -the vertley cafe &n the coosk space that opens and Save the pile afb completion of etibing stepD'-. 0 to the process view winfow and, clouble click on -the sy nunesi xst. | covvect the evrovs iy any supOr To create -the Test bench. eo -tne bellowing. © select project > New source the New souvee witavel opens En whfth qou speciby Behe type of Source cou want to create. © Fn the select - source, type, select vert log test fT ate. I@ click Neat _ | © Assoctate vertlog gfle gou dust Cveatid . [© cliché Heat. [@ cles bintsh. stepO- Mate the alliraons tn -the tast bench, Give % conf yon as vequfved for You Cesiqn ds the al stepOr fo te qesigr view click ow Mulatjon ood under process View Xitlox Fse€ simulator Pah t cle of the Simulat: behovioura/ moole} Selene and click on Run RGUKT Basar Department of Electronice and Communication EnginceringDate: Page No. IN BIDZGAD one q Experiment Name:-......Q. for the g@ven input comt?Gons. ry sapOr The new Trim esurfow open that res the O/P 4 sap@O- Abt cerplatyon of Sirmulation, we have to roplement the cocte Erte FPA heard, sap@- Abby syothst¥e XST of the design ‘ DI 0 check the output oD FP4A beara given Enputs. avd according + -the| AX RGUKT Basar Department of Electronice and Communication EnginceringPage NO! emer 1No:--GLI2Z426._ 2. SIMULATE Ano SYNTHSIS OF AI) BASIC GATES '— oe behaviour of Several of -the baste Logic a cepa you ewPll connect several Logie qates toqsthey Tr +o Create stenple dq@tal enodel. wR Soptuzare Teel Requtvernent :— mie computer with xlinx 15 Sortaave vertleq ; H) Sstyuctuval flow :— @ pnd module oR—qate Cénputa, trputh. outpute), assign c- a/b. endmodite. : t structuyal -- . . _f module o@ Cénput a, input b, output)? ov ar Co, a, bd) Sopukb, output vege)» always @ Carb) beqeo Y Ca==1bo%Y b=- jbod calbot : ese - er enealrmoaale Test bench :— module oR- TF weqa, weg by wire cy oR wut Gata), b0by . (9); witial RGUKT Basar Departme: eclroni Partment of Electronice and Communication EngineeringPage Nor QZ 1ONor LIF 24 Ab. 5 bzo', Hor, bel + 4PIOe, bro dHl00% bel 2 A400” ene] module | T © not Gate rm TY D Data flor rpodule NoT ( érputa, outputh) — assign be nal n—pe—F enel module — BP sirtctivat module noTCénput a, ourput 6): }1 fo not n) (bad~ end nodule yb Bebaviows © nodule NoT (énputa, output veg b> always @ Carb) bege> | 4 (ae 0) | berbs else bz! bo is ent — ena module. RGUKT Busar Department of Electronice and Communication EngineeringPage Nona aa: ono BI 24-10. ad Test bench ae module NOT_TF * * a nega: weve b» “4 not uut Gala). blb)> tntGal i beqin asl ene} end module @ kx-or Gatee 2 pata Figo sSb- module xoRCEnputa, énputb, output c): assign C= arb; ert module G) structural module x0@ (Esputa, Enputb, output c)~ XR a, (6,0,6)5 end module genaviours” reodule xoR Cénput a, toput b, output 229 ¢) always @ (C-arb)* a cae Cac) ‘ | cabo. RGUKT Basar Department of Electronic and Communication Engincering | T ee —4 Experiment Name: ww no:--B.192.44b.— cerbl® end mee Test bench ~ Tesh ben’ reodule xoR- TF mega: vegbs wtrec: foe oUk Cal). bleh cc)\ énitfal beg ed azo 5 bz0% #lor! Bo: bel 2 #1005 ee) Qe; bop 5 #lOP2 az) > bel ene eng module © Nenp Cele » Data dem - module sand (tppat a, Eoputb, output cd: assign ¢- agb: end module. af Pan ef hae Pic if cL ch PIV oN VA PJ Sf Me Sn Nie FE A op structural module rand (énputa, trputb, output); wand » (¢,a,b); ered) module, | RGUKT Busar Department of Electronice and Communication EngineeringBehavioval :- rrodule sand Cénput a. enput b, output vey o) allways @ (a,b) begin yy Ca-='b 33 beibi) cabo. Bee ibis, end end module Test bench:— module NAND- TF. weg as weg > wire cs MOND uut Cala). bbb). «Ces éni Hal begin azo: bro, Hod, aso+ bel #100) * gee bon alte asl 4 end end module © nok Gab ) Data Flow module nox Cépput a, Enputb. outpute); |= 3 a assign c= wlalb)s end module. RGUKT Basar Department of Electronice and Communicat tion EngineeringPage No: 1D No:~..ARLD.2.44 Stwuc tural i Stouc tura module van (input a, Enput b, output end module S strectawel ' module XNOR (input, Enput b» output); XNOR a Cora), enacmodule i) Behaviour 1 module NOR (épput a, Eput b» Output veg c): atuoays @ Ca+bd alsa lilly begéo 5 ig Ca>>b) : c=rbls | : | else ) 1 . cell bo: Ty fo fo . end | a _ a end mo dele est bench module XNOK_7F- mega: reg by wive KNOR uut (.ala). ble). cley) éni Gal beg eo Qa: § b=0, Hod, RGUKT Busar Department of Electronice and Communication Engineering‘ Q-o > bel: lov, - ' arl + b20; FH/or) . soe : ' ae bale om , ene end Module 1 Result Success pully cwortttin vertloq tHe and trst~ bench codes ter all. baste gakS Gm data plow , Structural and behavioural moelél. Department of Electronice and Communication EngineeringO nwalf adder lal ade cireuir diagen sum> a@b carry ab. efrewte cLiagrard sums aQDbOc carry < ab+be+rca,I Experiment Name... _ HIM To. writte verTlog cole and Test bench code. na rfor Full adder, Hatt adder ang «pple cavvy addey nd 20 data flew model. struc tieral and behaviouvel model, 4 Rey Tels A computer system with. xilinx Iy.c yy Theory e+ ~ ts Half adeler- A Halt adder t a aqital logic creeuile wl that Performs binary ada? tons of 80 single bE a binary numbers. fk has -rwo @npub A ana 8, pets sum and carvy. the Sun output Least sign? ficant bit output & the most Sign? Sndieating etatever eve addition eoh@le the carry bicant bie o6 -the cas a result, carrg Ovey brory -thal half adder can be using haste getes such as xoRk Goolean Expressions: ef the two tnpab. the em plementad Y AND Sum -AOB covry e AR Fall adder Fun adder t the acide 44, Enputs and procluce two Cutpull athe ave Aand B -he th?vd at add three tisst -ty0 ap enput & Gan cag. The eourput cavry bs dessqrakd as c¢_ weal oa a, output & designatid as which & suns norm] sum = AOB®De cavig = AR+ Be +cR. Department of Blectronice and Communication EnginceringSe addey »-wt can fox qeneva on ee y -boe pavalte) épstantiale the full adder.» bee wepple caury adder Ripple cavvg adder fs a | structure of roaluple Sell addev & cascade 9% mannev to qive 4the result of the add? Gorn of an “fbi binary Sepuente. The adder Encludes cascade fan adders & it structure. so. the caved wen be qenevatd at every fall aceev stage ine xtpple carry addev Cirecutt. - codes — PO Haly addev- D> Data Flow module Halg Cioput a, eepuk 5, oatput sum. output cary)} assign sums a%B) assgqr carrga ab, end module B® seceeberele motule Half Cfoput a, tnpat b, cutput sum, output carry); xor a, (sum, a, bd : and ar Cearry sas bd” end module ) Behaviour poodele Halt Cénputa, Empat b. output req Sum, output vq cay bexin always @ Ca,b, sum, carry) ‘begin & Cal =b) ty Cos-0 %Rb-+0) Department of Electronice und Communication Engineering,LiAA—-> (FAA TAA LIA ALA. Experiment Name:-... beqin Sum-O > cavvys Ol end eise Yo (ar=0 & % bead beg sumer, cavry=o™ end else ty Casal %% b= =0d begin Sums) covey e0% ese Y Cart] BS bent) beqe Sumo} caxsyet, en end end module . Test bench Code module Hal{- TF; weqas veq b', _ ete Sum, Carty), H-AD uae (. cot Gal beg for Cfeos, Tegrity begin fa,bye ft ee end ead moatule RGUKT Basar IN AlD24.9.b..n B64). BOb~ Cours (sum). carry cearry))?Date:- Experiment Name: 2) Full addey = Fell adde: % Data flow'— module FA (Zopata, Eput b, trpute, output sum, cul pat cary) assign sum Carbac)! assign coy = Ca%b)/( bcd] (c ga)’. end module, b Stvucturall— structural moclule FA CUput a, toput b, Enpute, output sum, output camy):, wre 5), Cy, Crs Head bh; C41b, 5,0€)4 HAD bs (ers, Sumied) OR 430 C1, Ca, carry): ert module. J Bebaviouyt— Ne basal mimi omlslim—oontimt module #90 Céerputa, tnputb. 2oputc, output rey sum, cutpat 197 always @ Ca, bye, sum, carry) cavrg beqd> ur at bt c<-3) carry. bt. end eise te Carbted=r) beqeo il We sum ctibos cavrge bIS end RGUKT Basar Department of Electronice and Communication Engincering| Experiment Name: else lr Catrbre yet) begin sume Nhl + cartys bot enel else beqer sum = tbo + carry = bo! end end endeqecdtule. Test bench'- ce roodule F-AD- FF: weqa: veg by veges cvtre SUM, cofve caxyy 4 Frad aut Calad. bCb). cCed. Sum CSum). carry Ccarry))* tniteal: , beqtn : tor Cis0: fats teitt) beqcn Parbicg Hos #50, |éopat co, oatputpa.c] sum, output cavry)? ative cy, Cr, C3) FAD 1 (alel, bo], co. Sum Lod ci+, FAD or Cat), br gy, sumfiy jc2)3 J FAD a3 (ab), bIeT, G, sumfby os); J fap 24 Cals), bis], cx, Sum[s], 3)! 4 eng module : Test bench :— -fov a@=Noo, b=lolo ~ (o20 module R¢- AD- TF; weg [s:olas veg [3iol bs req Col weve [8:0] Sums cwotve carry 5 Ree AD are Cala). blb)- ent tial bequ> az02 be0% 60 Hb 10D > a=y! bilo + b-y! Iolo» end end module. 1 66D + Sum(sum). Cavey Ccarry))5} i 1 RGUKT Basar Department of Eleetronice and Communication Engineering| Date:-, | experiment Name:-.... Result ait CBuce e sspetly written Ver? log Code and! “Test bench fov Half--addev , full - adder and pe bit vepple, Carry addley im data Flow, Stsuctarval ana Behaviontal models, ee ee | | F ication Engineeri: RGUKT Basar Department of Electronice and Communication ng a aaSo. y oy axl y o | x —] mov el 3 veut eprgin- DT Do = | 20 O 4x) reuxr Zo a 4x) Y a mone 43 St SD Yo HE To +5 ST) +S, 5 ap + 5) 507g > 2e ‘pppppPpPN PP PP PPPPPPPPH yp pp 9PARC NO ares Caiknenemene WN BLD AYA baa g 2 Zz 3 z 5 Kx periment —b Aim TO write a vert leg Code FY and fst bench 5 is d gxr, ey. 1x8 Codes for 2X1, GxI, Bx) maltiplererS and 9x>, i demultiplexers tn cata flow, stvactuval and behavioural. Theowy:— Multiplerer & @ combinational cfrcutt , whech have many data trpats ana single output cepending OD contro; Ov Select Enputs. for ny Empuk lines have the 2? input Lines. 1 selection Lines ave bequPred ave also Known as data 1 selector, Sevial converter. [sel ja Sal ab LI b/s) As Ls s/s Povatiel +o mang to one cfacutt santversa) logic Civeuits : ’ 5 2x1 mmultipleaey - ~ j TM 9x1 multiplexers, theve ave only two Enpubbasb and Sejectfon Line Sj and single output y. on -the basis Of -the combina ton ef the pub. whitch ave Present at the Selee oo Line S. one op the 2 inpur wen to the outpar ‘ be connected Redean expression es) yr Sa+Sby © pata Flow module mvox (tnput a, enputb, tpacs Assan p> (ms) Sa) 105 36) +, seat pat y)+ evel module, RGUKT Basar Deparment of Electronice and Comm® TATE ata raasy’ Sy by Soty od So SiSeds -+ Se (Se Fo Ty nes rererrern pp pp Pn yr PPpPPeAnRhPARRPRAP HPP AA»| Date:-.. Page NOi a= Zaheer WN ALTA. Experiment Namo: © structural '— module eoxCenput a enput b, imput Ss, output we whe Yr Sra? NoT 11(5.51) 5 AND mm (5, 664) ANd ms (sed) 7 on oy CU yo Do end module ® Behaviouy model module roux (input a, grputb, puts, output ae gy), always @ Carbs s, gd" begen te (<= -0? yet else qebs module Test bench =| module mut -7F > wreyas vey bs veges etre 45 mux unl Cala)-blb). 6(s).yly), enitia] beg fabic} ary HO; a RGUKT Basar Department of Electronice and CommunicationSPP rms ease eee SSevO ETE eees Men tree Steen PUPS rere SaaE eMRESaE SEE ESR - | 9 — 60 \w & & 4 “Mlo-o ‘ : Glo o == 2 4 so g, : a a ee x & : s 4 J = g Rg Ve i x» 8 at t ” 5 » ee 4 it ‘OF 7 i s % = SsDates. Experiment Name: Qs em eof ena modate © yx mulliplerey — i 1 In the yx) multiplexev, theve ave total of four énputs | a, bic. d ov fo, %, ,l3 and 9 selection Lines So.S)- | and a Single Output Yy. of the basis OF the Combs | Loy the enpub that are present at a sejectjon Une So, S$; ave OF Y inputs ave connects to the oat pal. | Boolean expression &: ys SoS fo + SoS, 2%, +5052 +505,52) BY Data Flew'- module mux input So. Eoput s,, input zo, Gopat hs input iz, input (3, output yy; assiqo Yr + (cose) § (51) 875) | Cems) ¥ 5, 3 41D] bs sound 83] | S951 $2; \ end module. : BD structural - module mus Cénput So, Zoputs), aoputte, Eoput hy , ioputie, apat & output yd; weve YY? eux ™, Cf, 21, $0,415 mux. m2 (fr, > Seo DIS mur ms C41, 429 51-9)%, end module. RGUKT Bayar Department of ElectrDixy dere [> ve x Ixy FY bo ne ¥3 qemu, SY so efveutt atiagearni— ra ry aes Sr 5 So Y= Sse, ne S50 b= S\S0 . ya 5iSo naannvnnannannas® Yor S25 So. Y= KEs0_ 4y = $0515 > Ys Si 51S0 Yo = 525151 Yg-Ss1S0 Yo = S2Si50 . yy osesisoPage to 2S < Exporiment Name: AP itis 10 Ho. sb a We Benavioey medel “| modele mur Ceapat se, input Sr, goput te. dapat by fopuatley = ape &, oulput sey wy Sy lungs @ Cs. 1 Co, €,, ta, ba) bee ty Csee = 0) beget tp Csiro) qs fo eee wet eod else beqeh tsp Csi) getos ese qeiss end end end moda le test beh module run TF: ae"g $0; wegs,! req fol 9 giv vegta, veg la, eotve Ys ren Ace CS CS0D- SCS). tC Pe de Ot) Cia) THC) « yyy} intial . cs fou Cf-0% Ceby 2 tay, RGUKT Basar Department of Elcctonice and Communication Engineeringbegin 450, 51, Hy, te oF} end #10’, ert enclenocu le © 8x1 multiplexer’ Tn -the «8X1 mux, -theve ave 8 fopue & to fy and three Selection Lines so. Si, $2 and a Single output. on the basis Of 2 combination of énpab that are present at tbe Selection Lines So, 5, and Sz ave these Enpa& ar€ connected fe the output: ye Bo5alo + S65 S28) + 5051Sa8 + $5515 5 45475 Cy > So S7S21S + So S/Br 76 +SeS)S227 4% D Date Flee medel cnodule nun (tnput So, Epub. put s2, Coput to, Copubt epuein énput %, Enpukty , Coputts, Zoput &, cnput Pr, outputy); assiq7n Y= (Corse) BCS) BCweeD $Fe)] (Cmte) Blwnr) & So K / Crs) 381 3(52) 372) wend module. ) ebrexekvel angdlel- module mux (60 $115 2 bo F, ty 83, Bie, ie, 7, yD! eppat Se, $1, Sr, fo, &, 2,13, fy, iS, 76, 17° Oukpat 45 wetve tus Gry RGURT Basar Department of Electronice and Communication EnginceringNo B19.2.49.8.0 mux 71 (So. 515%. &, 2,03, 995 mux ma (Se, So ty, Ps, 16.77 YDS moun m3 C4. 4e- $2,905 ~ end modalé = i) Behavicuval — ee oe eee | module mux (50.51, €, &%, tr, ts, S45, 6, £7, Dp) a Eopat se, Sry to, G1, tar is, Ty, ts, fe, ‘a Outpet veg ys ~3 alurays @ Cio, &, i, %, ty, te, 16,97) beg tp (sr = 209 beqa> i§-(s)-=0) bead AL Coen od qr ios ase get enel e1se bega> if Cs2202 yore seas yetst end end beg cn Up Csie +0) beg? ¢s-=0) RGUKT Basar Department of Electronice and Communication Engineering,Page NO: mnnn 2. WD Nor nlRL924.9. ge tas ese ye enel else begin up (s-"0) 5) gribs end end enemodale. Test bench = = modale mux —TF; meq ty, veqias 12g we qse 5 req fe. aoqty, regis, 29 te, veg FT) rey Sr, TEYS? wtre Tr pour uUet (be Ctod.t1 Chi) told. 23 07 Chtde SoCs0) +51 6519+ st). 4l4))) 13). 2y Cla). Ps (42). Polio) enitial_ bege® a oc (4705 ber048 + patti) beqeo & § 50, $1) 8% For G, testo, by, Movie, PIy eT end 410% end end module. 4 Department of Eleetronice and Communication Engineering RGUKT BasarPage Nox 2 __ 1oNo 8/9204 6 : i a 2 j 2) Demultipleaes— A qe muttipleser & 0 combimbona] Civeult that has only linpat and 2? output Unes. thedtmuttiptexer fs a single Yp end rmutuple cutpes athe tate:matjon 2s vecjeved From the single eyp lies atrected t the cutput Une the caemultipexers [Pl pation Dod, and ts opposile OF multiplexers. pL © 1x? demure I -7, it consish of Ci/p Line. one Selection Une and 9 Lt output lines ab. ae Te, eege & Date peo modale demua(opuk f, doputs, outpata, oatput b) assiqn az (ws) Kit assign be (s3D2 end module D styactyrel model — . ee ee eS catpat a, out pat b)> unre Si, noT 9, (5,51 AND 4 ($17.0); AND 9 C5, e+ b)y end mo dule Department of Electronice and Communication Engineering RGUKT BasarPage No: 3: Experiment Name: = WD Noon fAL92.44.98...0 WO Behavioural model !— module demux (énput &. input 5, output veg 0, out put ang bi Always @ Ci.5,a,b) begéd tr (s-+0) beqco : ast bz/ be, end eise | ‘ beqr aci'bo, be ibis end en end modale Test bench!— module denuz— TF: weqt* veqi $5 weveat were bi demux unt (.fc7). scs> «Cade - bee), Ri tial begin (205 S02 Aloe 4 SEIS Ar IOD) Pep, S205 thle gels end end module . RGUKT Basar Department of Electronice and Communication EngineeringDate: Page NotmaB.bneananmee ~B1I24.98._. ( Experiment Nam ID No: )_a_». Dor. © 1x4 demar'— consis of single Copal &, two se}ection| Utmes and four output Lines a,b, 63d Boolean Lapressions: ee i ee a pp yy, LEEPLLLAL LD ae He d= S05) 2, D Data plow’ modele clenua Cfoputt. Eoput se, copuls, outpuba output b eutputc, output dds assign a Crise) Sls) ¥F2 assign b= Crsed GOS ST ve assiqn C= gy Cvs ark assign 42 a eee ere} module wb structural rnodle] denne (épput &, tnput so, inputs, » output a, out pub > output c> outpued a5 module wotve Seb, Siby, —~ SS demu ai (8% 50, SobsSib) = emus d> Cseb>S1,0.6), —~S —— dernua da (sb Sirs AD) end module i) Behaviouval epdel— mociule demux C&, 50,51, a,b, 65, 4)5 input 2.50, 6,5 out pat_ req a be. lb Department of Electronice and Communication Engineering S| RGUKT Basar i 7always @ Ce, so. 51,0, b, cra) begin ip css+0? beqer else de ere enel end module Test bench’ te deeos ee weg t veg Se, eq 5) wotre a; wtvebs wtvec > wired’ Aeroux ut GICT)~ 50650)- 5,05,) -rcad. bl) «(Cede ))) enetial beqir gov (jeortess S-j+) e505 04-3 Heo ene} en: end module. ee RGUKT Basar Department of Electronice and Communication EngineeringPage NO: meme B Bimimn anne 1D Nor—— BID. » Experiment Name ® 1x8 demux tt consis of engle Copur &, and three Sefection Lines $0, 5,, $2 and & out pult foo Gib ca eo foes bo: 2 Data slew — module demux (&. $0, $1, S2,a,b, 6,0. 054. q bd» _ coput 2, Se, S15 output a,b, Cs ds es F592 bs Assign A= Cvs) ¥ Crs) ¥ rs) BT > assign b= Crs) & C05) & 52 BF > assign Co Crs) § 51 & vse) 8t7 assign cle Cs) 4S) HS BPS assiqn @ = SoS Crs) Bw) B > assign f= $0 & Cos) ¥ Cw & a assgn 72 S05) & Cas BPS assign h= So BS) 3 $1 BP, LEAPED i enadmo dale @ Bebaviow" moog] a revdale elemua CE. $0 $11 $24 a,b, Cr dies $59,695 Enput &, So. 8% ourpul e427 % bcs de.fsqsh: always @ C2 £0.81, S45 1b, 6, 4, er F49,h) a beg én ig Cs1= 20d begco ip (52770? RGUKT Basar Department of Electronice und Communication EngineeringDate: Experiment Name aol else bet ¢ else beqen eb Cs2 220) coe: elses. teary ene else peg tp (ss -0) gets else bet) end 4 Kesutt' CSuccesspully written VYertlog Code and Tet bene fer 2x) 5 Gxl, 8X) munes and [x>, Ixy, &x¥ demultiplerers . ‘ RGUKT Basar Department of Eleetronice and Communication Engineering}© YX» Encoder hore Yo 8x3 encoder a Ye to > a y RQ erxofev] 4 Boolean Kxpresssons'— pars eas Fo 4 Ye THT3 + 15 +57 Jo+ Fy + Ie 477 ty t+ TS +t +I5 cfveult diagram? wa od YP PP Y Np Pp gp gg gga gegenAim to write « veviloy cole and Test bench for encedev and qecoley & data flow model, structura)] and reofels behaviouval Encocfeys athe combinational circurts “that change -the binary” Cngerragon into WN ofp Lines ave Known as encoers.| The binary enpormation és passed & ~the for Of oY enpub& neds. the ap Uines depined oS N-GLE code pov the binary @npormagon. The produced N bit ofp code fov eqatvalnt to -the bnar?. a Vo yxr encoder! : FO yx> encodevs tt had total four “spat Unes ana | Ca.bic.d) arc two output lines Gu). tm y typ Lines one énput Use es set te select at tree at a tiae cto qet the respective binary code in ..the ep. m=Yb Yo ale: % Data Flow modele enceder (a. bic, x, Grads tnpul ia ae ourpel % 4) assign %- Yb > assign 42 ¥e5 end modal. RGUKT Basar Department of Elcetronice and Communication Engineering— D Stvactyeral emodel module encoder Ca,bsc.d. x. os Pnpat a.bresds output a. y% or a) (a>a,b>', or a C4 0d™ ‘ ene module. Gi) Behaviowval enedel— gib> Sehaviou oe module encodev Carbs ¢- dams yt Enput A be. dy output wey % TF) alevasys @ Ca» bred) begin ip Carb==) aslby else Up Care ==1> ge tel: e1se beqh , ' as mepbol Yetbor end end end module crest bench i modale encoder -TF 5 wegat veg by weges veya) weve &) wtre gq? entodev aut Cala). blbd+ ens ene module: oer '— ® 8x3 erse The 8%3 enceder & also Known as octal to binary encoder. In 8X3 Line encoder, there 2s a total Of 92h) and total OF chee O/P Enput Une ®& set oF binasy codes. efgbt topats Casbre,cde, ca 422). rn 8 Yp Lines, one 4yue at a time to get the respective DB Data flow model — module encoderCasbiGdreng$igsh, 239s tS Enput a, beds AaFghs outpat © gy Fs assign 22 a[bleld> assign Ge alblelf, assign > eel 4s end module. BD structural model module encoder Carb.c,d,OF,9,6,%- 4s EY) inpat a b,c.d.e,t.g.h? Ourpuk 2+ Yo F5 Department of Electronice and Communication Engineering RGUKT Basar~~ 7 & Os i Coe a bce orm Cyra,b 2, $9", or a3 C%,a,¢0,0599. end mnodule Behavioural rode! ee module encoder (x,y), input [7:0] zs output veg [gio] yo Always @ C1) begén sino : y= 3'booo: sib) 1 Ye bool? dm: Y= 3 bolo. sibs! shy ! ye sb)00; ye sblel; yeogboll> ahs! ang 2 Yes bilo SBI 2 gba. ye3 . end end module. crest bench cose - module encodev- TF? mega: vegbs vege, sega? vege : veq dt: veqq: veghy were x4 wlre yt wre 1 encoder aut (ala). b(b). cede ald eC) £4). 9C0)- HEA) 5 éial RGUKT Basar Department of Electronice and Communication Engineering24 ? LLEL Dopp Experiment Nami begin ov Cizot Peace, beqe > farbeo-ady ets A560, end end end module = DescederS'— The combinational circuth that changes the binary Seqrnentatyes Ento 2” enpuk Lines & Knoewn ac clecocky she binary tnformoater & passed a “the ores of N -én pub Lines. : » RxY decoder — en “the 2x4 Une decoder, there & —totalop three ch pult | a yo and enable signal €, and -four ourpae abc, d- Foul each conmbinaton of p's, ewhen —the enable '€’ & set to J 2 pate flee moaule cecodev (6% Ysarbscsd): tngut 25-95 output tbr coay assign A= €% Cra) &CNYy)L, assign b= EX (was BYS . assign ce EZRA COYD, asssqo 4 =e &xSG) ere} module. Department of Electronice and Communication EngineeringPage NOI nen. INO? al BLAS ERA WD Stree teral angetel'— module aecolev Cl. Yra,bicra)s enput Es, Yh output arb, c-dlt wtve Xo, Jo's not 0, Cro, a* not ts Cyo. Y's ai(a, x0, ge.€) ~ and arb, a0, y4,6)"> and ay (dsx. gq, 65 and and 43 (6125 Yo, E> 3 er) module. UW Behavioural engdel'— module decoder (€, 2.4 a besa) 5 Enpuk €.% Y) oukpue weq a, 8.40 always @ Ca, bs crcl, € 54-4) begin tp Ce 20> beqeh_ tp Ca-70D begeh tpl y= 20> ~ aci'bts else b= tbr end ene} efse , begin te Cyto) ce bls efse- _ RGUKT Basar Department of Electronice and Communication EngineeringPage No:nrnm Experiment Name:-.. a WD Nomen BLAEY I Boe deiibis end module Testbench code! eoodule decodev—TF weg €, weg, M45 etrear wrreb* awPrecs wired’, Clecodey aut (.ala)-blb).cle). der). Eve). xCad. GLY) Eniteal beqin gorCicos tees t+) beg eis Zea bhets fp 50) end end end module 3x8 decadeviK e ste B decoder cones of Y Emput Lines Ce ary z) ‘€ & the Enable fiqgral. and it has 8 outpab ave Carbseidse, $:9-h>. the output which B produce, by giving “the Enpobs ty -the Ceystem, Department of Electronice und Communication EngineeringExperiment Nam 08... » Data flow: module clecodey CE,x.g,4.4 input €. 4, 4, €5 output a,b, 6) des $.9+h5 pbrer ds e,f.9sbds assign a = (wa) &lry) 3 (wt) SE" assign b= (w®) &iwy) ¥ERES Osg390 Ce Cw BG SOWDBED aseiqn de (wa) SY ITHEL assigr e= 2&CPYDZWDSES assgn F223 (rq) ZSTSED assign 9 = a Hg FOND BED assign he HGS tSED end module Wh stractutal model module decoder CEs, 4 E54, b, 0,43 Cr $59,b)> Enput €,2. y t- : output a,b, od. es F.9sb5 were Xo. Yo. toD pot ) (ao. a)” not m2 ($e-9s not 03 Ct. and a1 (a1%0,4o, to, ana ar Cb, ao, Yo, %,ED3 and 43 (% 1 20, 4 >t, &)', and ay (d,x0, y, =D", and a5 Ler xs Yo, tor ED, and 2 (F1%3 40,285 RGUKT Basar Department of Electronice and Communication EnginceringDate:- ~ Experiment Namen. @Siesestoe and 87 C9. 24> to, G5 and ag Cb, a. Gs E- 0) end module i) Behavioural made!” module cecojer C1219) tra, b, 654,04 ,9 sb), Input Eom. Yr te out pat req a. bp ¢.d,@. fsahe . alway s@ Carbie, des $19 shy Esxiyr td beqér case C{EY) al booo : a= Shor dboo! + be dh’ dboro i Be 8b>s doo : A=-shs, dbloo : e= sx hy) gblot : $= shss gbilo : ge she: Sagi be ebay end case end end module Test bench module decoclev— TF: eq vem MYT, MOY E eotrea, atve bs wire cs wived + wive gs wivehs qecoter aut Cece). nlad- YC) + FAD- ala). bLED- CCD vetCetD. ele). $4). 90)- bt); wiree » wrre f 5 RGUKT BasarPABE NOtamemalf fonnemnmeee WD NO: aneLLI2YG faven 7% Date: : J Experiment Name: eni tia! begid Sox (t20, 216% f+ +) beqin (EG, 24-8 H20 ena end ena + ene modale . ‘ Result CCuccesspully written Vertlog code anid testbench codes forall pes of entodevS and clecoders & cata flow, Structural and behavioural! models / RGUKT Basar Department of Electronice and Communication EngineetExperiment Name: ALL desiqn'— -prtthmeie and Lozteal untt (Oro) TE comtatns -the set of opevations bv clo “the performance webich ave —prethenetic ancl boyteal Ct. .-. Bo%, 7, 1,0 ete--) © g bit ALY The 2 bit ALU Bs wthe 2 -the Logical and -Asttnar Ge operations aes ON Q bb, eahech contains 2 Epa @.b> and -these Zopub contatns (g-+g 4) bl. one secon Une contnins 9 bets and Single out put contelns | also 2 bib Only. module alu Cab, op. yg) im pat a,b. ops outpak 269 4% oleate © (a or b er op) op se) - ete beqen he adboo + 4+ ath) dept. a< 2%) s gbw . yo t5b3 gon: ge ohh encase ene end module. RGUKT Basar Department of Eleetronice and Communication Engineering,Experiment Name: Test bench Cocle- module alu— TFs reg ar seq bs reqoP) wire Ys ale aut (-90).b6b). op top). yy) 5 erittcal begen aro: bso: 4202 ast) bet op-Sboo', aso: bro: op= z'bob> 120% aso% bls ope atbol #705 acl; beO) Ope bel 5 4hoy asi, bel) ope o'bo); 420: 2 b205 ops gblo) 420, > berg op: J blo at 20% 1 bos ope glblo; 420, bel > op oped bi; 420) + beO 5 ope a!biy dao, asl; bel 2 eng end module, WW Norn BLA Bam RGUKT Basar Department of Electro and Communication Engineering> z z 4 bit ALLY The Yy- bit ALL Contains 9 cnputs, that © e inputs contain y-bité as well single output and t& contains y— bts and Selecion contains 3-biB. Cosje!- module alu CAB, op, out)’, tnpat- dD, Bop) topat [3:01 A> 8-7" Enpat [gio] oP™ output veg [S:0oT out) v alas @ Ct) begén : a case Cop) Jbooo : out 20% dbool : out. ATB, out = A-82 out = A*BS dbroo + out = 0/8> dbtol out - A.B) : 3b1o0 aolll : dlefautt * out =0> er case end end moclu le . dbolo : iboll : out = VAL out = 8, RGUKT Basar Department of Electronice and Communication EngineeringD TK oP lop \ ) 3 Q ok é bay ®@ Ss aQ IK. QbaY Todetivroinale RPARE NOt amen lL Sievmnnere Experiment Namez+.....Q8.o0 WN: LI92496_ Sequential Cirveuib t- Experiment 6 - Aim! To rile a Vertlog code and Test bench codes poy Sepuenter! civeutts of flip flops. © Th FLip bLeP module FE (T.K, éldgl Q, Qbear)’, i énpat Tis 5 Cle output Q, Qbar, cwwotre , wy), Wr’, nand Ca,, 7. cik, Qbax) mand (wr, K,cIK, Qa), rand CQ, w> Qbax)! rand (Qbar, wr, QD, erg module © Th blip Yep “eq cae statement module TKFF (FT. Kk. cIb. Q)! foput 5. Ky input clk * Output Q's weg BO) always @ Cpeseage clk) begin case C. £ 5-k}) gboo: Q-8; gbol : Q-0, RGUKT Basar Department of Electronice and Communication Engineering Ne ee eewa e Date: Experiment Nam ; » Qs ablo. Q i “ abn 2 QV, en case end erdrnoda le ny ® sv bleep qtop- module 52 (5,R,C1K, Q, Qhav)> empat Sok, ciks Output Q, Qbar> wtre wy, wrt mand Ca), 5. c1K>*, mand Cor) R, CIKDS mand (Q + ©), @baxy, rand (Qbear, woz Q);, end module @ D- Flip Flop - module DFF (CD. ck, Rst, ae Empat Do clk. Rst : out pat oe bt eq Vb’, always @ Ces ectge. ok) + Up CesetH) beges y= Ibo! Ab =ny ) RGUKT Basar ee Department of Electronice and. Communication EngincerinExperiment Name:-... end : beqro 4-0 Yb -nv % ena enq module