Lab_6_Traffic Controller in HDL

Objective: In this lab, we will implement a Finite State Machine (FSM) in Verilog to control a traffic light controller in
Verilog (or VHDL) sample project code is provided for either HDL.
The traffic light controller manages two traffic lights, LA and LB, based on the input from two traffic sensors, TA and TB.

Specifications:
1.Traffic Sensors:
• Two traffic sensors, TA and TB, provide inputs to the traffic light controller.
• Each sensor becomes TRUE when there is traffic detected at its respective intersection.
2.Traffic Lights:
• The traffic light controller manages two traffic lights, LA and LB.
• LA controls traffic flow in one direction, and LB controls traffic flow in another direction.
3.Finite State Machine (FSM):
• Design an FSM that controls the behavior of the traffic lights based on the input from the traffic sensors.
• Define states and transitions to represent the behavior of the traffic light controller.
• Ensure that the FSM follows the traffic light control rules (e.g., green light for one direction, red light for the
other).
4.HDL Implementation:
• Write Verilog/VHDL code to implement the FSM based on the designed state diagram.
• Ensure proper signal assignments, state transitions, and timing considerations.
5.Simulation and Testing:
• Test various scenarios, including different combinations of traffic sensor inputs, to ensure correct behavior.
6.Documentation:
• Provide clear documentation explaining the design of the FSM, state transitions, and signal assignments.
• Include comments in the Verilog code to explain the functionality of each module and signal.
Deliverables:
•HDL code files implementing the FSM for the traffic light controller.
•Submission of the assignment report including results from simulation and testing.
 FSM Example
• Traffic light controller
– Traffic sensors: TA, TB (TRUE when there’s traffic)

Bravado
– Lights: LA, LB Dining
Hall
LB

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms
Blvd.

Fields
 FSM Black Box
• Inputs: CLK, Reset, TA, TB
• Outputs: LA, LB →
CLK

Multiple Bits: R, Y, G
2
TA Traffic LA
(TRUE when
there’s traffic Light 2
TB Controller LB
Multiple Bits: R, Y, G

Reset
 FSM State Transition Diagram
• Moore FSM: outputs labeled in each state
• States: Circles
T
• Transitions: Arcs Reset
T
A

S0 A S1
S2 LA: green LA: yellow
LB: red LB: red
Bravado

Dining
Hall
Yellow light:
LB Yellow light: auto transition
auto transition

LA TB
LA
S3 S2
S0 Academic TA TA Ave. LA: red LA: red
LB: yellow LB: green
Labs TB LB Dorms TB
TB
Blvd.

Fields
FSM State Transition Table (Next State Table)
Current Next Reset
TA
Inputs TA
State State S0 S1
LA: green LA: yellow
S TA TB S' LB: red LB: red

S0 0 X S1

S0 1 X S0 S3 S2
LA: red LA: red
LB: yellow LB: green
S1 X X S2 TB
TB

S2 X 0 S3
State Encoding
S2 X 1 S2 S0 00
S3 X X S0 S1 01
S2 10
Assume clock cycle = 15 s (for illustration) S3 11
FSM Encoded State Transition Table

S0 S1

S0 S0
S1 S2

S2 S3
S2 S2
S3 S0

State Encoding
S0 00
S1 01
S2 10
S3 11
 FSM Encoded State Transition Table
Current Next State Encoding
State Inputs State
S1 S0 TA TB S'1 S'0 S0 00
0 S0 0 0 X 0 S1 1 S1 01
0 S0 0 1 X 0 S0 0 S2 10
0 S1 1 X X 1 S2 0
S3 11
1 S2 0 X 0 1 S3 1

Bravado
Dining
1 S2 0 X 1 1 S2 0 Hall
LB
1 S3 1 X X 0 S0 0
LA TB
LA

Academic TA TA Ave.
S'1 = S1  S0 TB LB Dorms
Labs
S'0 = S1S0TA + S1S0TB

Blvd.
Fields
 FSM Output Table
Current Output Encoding
State Outputs
S1 S0 LA1 LA0 LB1 LB0 green 00
0 S0 0 0 G 0 1 R 0 yellow 01
0 S1 1 0 Y 1 1 R 0 red 10
1 S2 0 1 R 0 0 G 0
1 S3 1 1 R 0 0 Y 1

Bravado
Dining
TA Hall
Reset
TA LB
S0 S1
LA: green LA: yellow
LB: red LB: red LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms
S3 S2

Blvd.
LA: red LA: red
LB: yellow LB: green
TB Fields
TB
Output Equations (based on states only)

S0 G R
S1 Y R
S2 R G
S3 R Y
 FSM Schematic: State Register
Current Next CLK
State Inputs State
S1 S0 TA TB S'1 S'0
S'1 S1
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
S'0 S0
1 0 X 0 1 1
r
1 0 X 1 1 0
1 1 X X 0 0 Reset
state register
 FSM Schematic: Next State Logic
CLK
S'1 S1

TA S'0 S0
r
TB Reset
S1 S0

inputs next state logic state register

 FSM Schematic: Output Logic
CLK LA1
S'1 S1
LA0

TA S'0 S0
LB1
r
TB Reset
S1 S0 LB0

inputs next state logic state register output logic outputs

 FSM Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
Current Next TA
Reset

Bravado
State Inputs State TA Dining
S0 S1
Hall
S1 S0 TA TB S'1 S'0 LA: green LA: yellow
LB: red LB: red LB
0 0 0 X 0 1
LA TB
LA
0 0 1 X 0 0
Academic TA TA Ave.
0 1 X X 1 0
Labs TB LB Dorms
1 0 X 0 1 1 S3 S2
LA: red LA: red

Blvd.
1 0 X 1 1 0 LB: yellow LB: green
TB Fields
1 1 X X 0 0 TB
 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)