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Sheet (4) 1

Circuit ac domain problems superposition

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43 views4 pages

Sheet (4) 1

Circuit ac domain problems superposition

Uploaded by

anas.hilton2004
Copyright
© © All Rights Reserved
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Misr University for Science and Technology

Faculty of Engineering
Electronics and communications Department
Electronics II (ECE 202) Sheet (4)
Q1- For each circuit in Figure (1), determine VDS and VGS

Figure (1)
Q2- Using the curve in Figure (2), determine the value of RS required for a 9.5 mA drain current.

Figure (2)
Q3- IDSS 20 mA and VGS (off) = -6 V for a particular JFET.
(a) What is ID when VGS = 0 V?
(b) What is ID when VGS = VGS (off)?
(c) If VGS is increased from -4V to -1 V does ID increase or decrease?
Q4- Graphically determine the Q-point for the circuit in Figure (3-a) using the transfer
characteristic curve in Figure (3-b).

Figure (3)
Q5- Find the Q-point for the p-channel JFET circuit in Figure (4)

Figure (4)

Q6- Given that the drain-to-ground voltage in Figure (5) is 5 V, determine the Q-point of the
circuit.
Figure (5)
Q7- Set up a midpoint bias for a JFET with IDSS 14 mA and VGS (off) = -10V. Use a 24 V dc source
as the supply voltage. Show the circuit and resistor values. Indicate the values of ID, VGS, and VDS.
Q8- The Q-point of a JFET is varied from VDS = 0.4 V and ID = 0.15 mA to VDS = 0.6 V and ID =
0.45 mA. Determine the range of RDS values.
Q9- The datasheet for an E-MOSFET reveals that ID (on) = 10 mA at VGS = -12 V and
V GS (th) = -3 V Find ID when VGS = -6 V.
Q10- The datasheet for a certain D-MOSFET gives VGS (off) = -5 V and IDSS = 8 mA.
(a) Is this device p channel or n channel?
(b) Determine ID for values of VGS ranging from -5 V to +5 V in increments of 1 V.
(c) Plot the transfer characteristic curve using the data from part (b).
Q11- Determine VDS for each circuit in Figure (6). IDSS = 8 mA.
Q12- Find VGS and VDS for the E-MOSFETs in Figure (7). Datasheet information is listed with
each circuit.
Q13- Based on the VGS measurements, determine the drain current and drain-to-source voltage for
each circuit in Figure (8).
Figure (6)

Figure (7)

Figure (8)

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