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Electronics (2) : Chapter (7) : Lecture

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Abdullah Zaid Ali El Şarki
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28 views22 pages

Electronics (2) : Chapter (7) : Lecture

Uploaded by

Abdullah Zaid Ali El Şarki
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Electronics (2):

Chapter (7): Lecture (4)

__________________________________________________
FET Biasing:

 Common Gate Configuration:


 The next configuration is one in which the gate terminal is grounded.
 The input signal applied to the source terminal.
 The output signal obtained at the drain terminal.

Two versions of the common-gate configuration.

For the dc analysis:


Mathematical Approach:

Gate – Source circuitry

Applying Kirchhoff’s at gate source circuitry

-VGS – IS.RS +VSS = 0

VGS = VSS – IS.RS

IS = ID

VGS = VSS – ID.RS

Drain – Source circuitry

Applying Kirchhoff’s voltage law around the loop

+VDD - IDRD - VDS - ISRS + VSS = 0

Substituting IS = ID we have

+VDD + VSS - VDS - ID (RD + RS) = 0

VDS = VDD + VSS - ID (RD + RS)

VD = VDD – ID. RD

VS = -VSS + ID.RS

Graphical Approach:
Q – point → [ VGSQ & IDQ]

VGS = VSS – ID.RS


Applying the condition ID = 0 from equation

VGS = VSS – (0) RS

Applying the condition VGS = 0 from equation

0 = VSS – ID.RS
Example (1): Determine the following for the common-gate configuration of
Fig:

Solution:

a) VGSQ
b) IDQ

For the transfer characteristics:


if ID = IDSS/4 = 12 mA/4 = 3 mA,
then VGS =Vp/2 = - 6 V/2 = -3 V.
The resulting curve representing Shockley’s equation appears in Fig.
VGS = 0 – ID RS
and VGS = -ID Rs
When ID = 0m A
VGS = 0 V
Point1 (0,0)
When ID = IDSS / 2 = 12 /2 = 6 mA.
VGS = - (6 mA) (680) = - 4.08 V
Point 2 (6, -4.08)
The resulting bias line appears on Fig.
IDQ = 3.8 mA and VGSQ = - 2.6 V
 SPECIAL CASE: VGSQ = 0 V
 Note that direct connection of the gate and source terminals to
ground resulting in VGS = 0 V.

 Since the transfer curve of a JFET will cross the vertical axis at
IDSS the drain current for the network is set at that level.

Applying Kirchhoff’s voltage law:

Example (2): Determine VDS for the network of Fig.


Solution:

The direct connection between the gate and source terminals V GS = 0 V

When VGS = 0

ID = IDSS

VGSQ = 0 V and IDQ = 10 mA

VD = VDD - IDRD = 20 V - (10 mA) (1.5 k Ω)

= 20 V - 15 V

=5V

 DEPLETION-TYPE MOSFETs:
 There are similarities between the transfer curves of JFETs and
depletion-type MOSFETs in analysis DC.
 The primary difference between the two is the depletion-type
MOSFETs allow operating points with positive VGS values and ID
levels beyond IDSS.

Example (3): For the n-channel depletion-type MOSFET of Fig,


determine:
a. IDQ and VGSQ.
b. VDS.

Solution:
a) For the transfer characteristics
ID = IDSS / 4, 6/4 =1.5 mA.
VGS = Vp/2, -3/2 = -1.5 mA.
We will be defined point at VGS = +1V.
The resulting curve representing Shockley’s equation appears in
Fig.
From Shockley’s Equation

( )
2
VGSQ
IDQ=IDSS . 1−
VGS ( cutoff )

( )
2
+1
IDQ=6 m A . 1−
−3
ID = 10.67 m A.
VGS = VG – ID. RS

When ID = 0m A
VGS = 1.5 V
When VGS = 0
ID = 2m A
The resulting bias line appears on Fig.
IDQ = 1.7 mA and VGSQ = - 4.3 V
b) VD = VDD – ID. RD
= 20 V - (1.7 mA) (6.2 k Ω)
= 9.46 V
Example (4): Determine the following for the network of Fig.
a. IDQ and VGSQ.
b. VD.
Solution:
mathematical approach:
a) VGSQ & IDQ
Step1: Apply KVL in gate to source circuit
-VGS – ID. RS = 0
VGS = - ID. RS
ID = - VGS / RS = - VGS / 2.4 K Ω ………………... (1)
Step2: Shockley’s Equation

( )
2
VGSQ
IDQ=IDSS . 1−
VGS ( cutoff )

( )
2
VGSQ
-VGS/2.4K Ω = 8m A 1− −8

2
-VGS/19.2 = 1/64 ( 8+VGS )

VGS = -4.25V & -15.07V

From equation (1)

ID = 4.25/2.4K Ω = 1.77mA.
ID = 15.07/ 2.4K Ω = 6.27 m A. (not valid).

Graphical Approach:

The self-bias configuration results inVGS = -ID.RS

For VGS < 0

ID = IDSS/4 = 8 mA /4 = 2 mA.
VGS = VP / 2 = - 8 / 2 = -4V.

For VGS > 0


We choose a positive value VGS = 2V.

The resulting transfer curve appears in Fig.

For the network bias line,

The resulting bias line appears on Fig, at VGS = 0 V, ID = 0 mA.


Choosing VGS = -6 V gives
b) VD = VDD - IDRD
= 20 V - (1.7 mA) (6.2 k Ω)
= 9.46 V

 ENHANCEMENT-TYPE MOSFETs
 The transfer characteristics of the enhancement-type MOSFET are
different about the JFET and depletion-type MOSFETs, resulting
the result is a different drawing.
 The drain current is zero for levels of gate-to-source voltage less
than the threshold level VGS(Th), as shown in Fig.
 For levels of VGS greater than VGS(Th), the drain current is
defined by

 The intersection point is determined on the drawing to provide the


two points (ID (on)), VGS (on) as shown in the figure.
 To complete the curve, the constant k of Eq.
 Once k is defined, other levels of ID can be determined for chosen
values of VGS. Typically, a point between VGS(Th) and VGS (on)
and one just greater than VGS (on) will provide a sufficient
number of points to plot (note ID1 and ID2 on Fig.).

 Feedback Biasing Arrangement


 The resistor RG brings a suitably large voltage to the gate to drive
the MOSFET “on.” Since IG = 0 m A, VRG = 0 V.
 The dc equivalent network appears as shown in Fig.
A direct connection now exists between drain and gate, resulting in

For the output circuit, VDS = VDD – IDRD

which becomes the following after substituting Equation

Since Equation is that of a straight line, the same procedure


described earlier can be employed to determine the two points that
will define the plot on the graph. Substituting ID = 0 mA into
Equation gives
Example (5): Determine IDQ and VDSQ for the enhancement-type MOSFET of
Fig.
Solution:
For the network Bias Line
Voltage-Divider Biasing Arrangement

Example (6):

Determine IDQ, VGSQ, and VDS for the network of Fig.

Solution:
Device

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