Starting with serial

Chapter Ten
10.3, 10.4, 10.5

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 Outline

• 10.3 The 16F87XA Master Synchronous Serial

Port module in SPI mode
– Master and Slave Mode
– Program Example
• I2C Synch. Serial Communication.

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 10.3 The 16F87XA Master Synchronous Serial
Port module in SPI mode
• The MSSP module is designed for synchronous
communication and can be configured as
– a simple synchronous port (called SPI mode) , or
– as an I2C port (Inter-Integrated Circuit).
• It has three SFRs dedicated to it, SSPCON1, SSPCON2 and
SSPSTAT, which can be found in the register file map
diagram of Figure 7.6.
• It also has a register for data transfer, SSPBUF, and is the
source of an interrupt, as seen in Figure 7.10.
• In this section we look at the module in SPI mode.

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 Port Overview
• Figure 10.7 on next slide shows the MSSP configured as an
SPI port.
• It can be configured as master or slave, with a variety of clock
speeds if master.
• At the heart of the serial port is the shift register SSPSR. When clocked, it
transfers serial data to pin SDO (if the output buffer gate is enabled) and
transfers serial data in from pin SDI.
• If the port is set up as a slave, it will receive the clock from the system
master through pin SCK.
• If the port is set up as master, it will generate the clock, which now
outputs through the SCK pin. This clock is derived either from the internal
clock oscillator, or from Timer 2.

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 Port Overview
• An important enhancement to our earlier simple serial port is
the addition of the buffer register SSPBUF.
• This holds a data byte on its way to or from the shift register,
and is actually the addressable register that the program
writes to or reads from.
• This makes the serial port much more flexible in use.

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The Master Synchronous Serial Port block diagram, in Serial
Peripheral interface

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 Port Configuration
• The two SFRs that control the action of the port in
SPI mode are SSPCON1 and SSPSTAT.
• Their use differs somewhat between the SPI and I2C
modes.
• They are shown, when used in SPI mode, in Figures
10.8 and 10.9 respectively.
• In them there are bits to do the following:
– Enable and configure the port.
– Sett clock rate and clock characteristics.
– Manage data transfer and buffering.
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 Port Configuration Cont.
• The port is enabled with bit 5 (SSPEN) of SSPCON1, and its
operating mode selected with the lower four bits of the same
register. It can be seen that these bits determine whether the port
is to work as master or slave.
• If in Master mode, four clock sources are available. As can be seen,
these are either the clock oscillator signal divided by 4, 16 or 64, or
the Timer 2 output
• If in Slave mode, the Slave Select input pin SS can be enabled,
through the four lower bits of SSPCON1. In this case, an external SS
signal can control the tristate buffer that drives the SDO pin and the
clock to the shift register.
– The SS input then effectively enables the serial port action and the
port can be used in a multi-node configuration

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 Managing Data Transfer
• If the port is set as Master, a write to the buffer register
SSPBUF automatically starts a transfer, clocking out whatever
data has been loaded into SSPBUF and clocking in whatever
data is present at the SDI pin.
• On completion of eight clock cycles, the interrupt flag SSPIF is
set and data in the shift register SSPSR is automatically
transferred to the buffer SSPBUF.
• The SSPIF flag can be used as an interrupt to alert the CPU
that the transfer is complete.
• If there is a write to SSPBUF before the previous word has
been completely sent, then the write collision bit WCOL is set.

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 Managing Data Transfer
• If it is set as Slave, then, when the SCK input starts switching,
the port clocks data into the SSPSR shift register through the
SDI pin. At the same time, data is clocked out of it from the
other end through the SDO pin. It is, of course, up to the
system designer to ensure that valid data is ready in the
SSPSR register and/or is available at the SDI input, according
to the requirement.
• When eight cycles are complete, the interrupt flag SSPIF is
set and, again, data in SSPSR is automatically transferred to
the buffer SSPBUF.
• If the previous byte has not been read from SSPBUF, then the
SSPOV bit is set, indicating a receive overflow.

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 10.4 A simple Serial Peripheral Interface example
• The program enables the Derbot microcontroller SPI
by writing to SSPCON1 (for reasons of backward
compatibility the Assembler Include File calls this
SSPCON) and sets it up as a master, with clock
frequency Fosc/16. Clock control bits SMP and CKE
are both set to zero here.
• Clock and data output pins are set up as outputs via
TRISC.
• The program then transmits two bytes in turn
repeatedly on the serial link, with a 40 ms delay in
between.
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Enhancing synchronous serial and the Inter-Integrated Circuit bus
• The Inter-Integrated Circuit (I2C) protocol was developed by Philips to
provide a serial communication standard to overcome some of the
shortcomings of Microwire or SPI.
• As its name suggests, it is meant to provide communication between ICs
within a single system.
• It is intended to be flexible and tolerant of different technologies and
speeds.
• Main Inter-Integrated Circuit features
• I2C is based on a master–slave relationship between nodes.
• The master controls all bus usage.
– Standard mode (with bit rate up to 100 kbps),
– Fast-mode (with bit rate to 400 kbps),
– Fast-mode Plus (with bit rate to 1 Mbps) and
– High-speed mode (with maximum bit rate of 3.4 Mbps).

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 I2C
• The I2C bus uses only two lines for all interconnection, called
SDA (serial data) and SCL (serial clock).
• The output of each node connects to the bus using an Open
Drain or Open Collector output
• while the node input is through a standard logic buffer.
• The two interconnect lines each have a pull-up resistor.
• Both lines are bi-directional, but the SCL clock signal is always
generated by the current master.
• When no node is accessing the bus the Open Drain outputs
are all inactive and the lines idle at Logic 1.

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 I2C Signal Chsts.
• The I2C protocol follows a very clear format for data transfer, as
shown in Figure 10.13.
• It is initiated by a Start condition, in which the SDA line is taken
low, while the SCL line stays high.
• It is terminated by a Stop condition, in which the SDA line goes
high while the clock is held high.
• The Start and Stop conditions are asserted by the current
master, as is the clock.
• Between the Start and the Stop, data is transferred in bytes.
• During this time, the SDA value can only change when SCL is low;
data must remain stable when the clock line is high. This allows
data transfer and Start or Stop to be distinguished.
• The first byte of any transfer contains address information.
• The standard allows for either a 7-bit address, within a single
byte, or a 10-bit address spread across two bytes.
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 The Master Synchronous Serial Port configured for Inter-
Integrated Circuit
• In this case the SCL line is shared with bit 3 of Port C
and SDA with bit 4 of Port C.
• In I2C mode the port is significantly more complex
than when in SPI mode, and care needs to be taken
to understand it.
• The first indication of the increased complexity is
the whole extra control register, SSPCON2, needed
for I2Cmode.

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The MSSP Inter-Integrated Circuit registers and their
preliminary use

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 Ex p 305
• Program Example 10.2 runs on the Derbot AGVand applies the I2C port as a
master. The key SFR settings are Port C (where I2C port bits must be set as inputs),
SSPADD (which determines the clock frequency) and SSPCON1 (which determines
the overall setting).
• Equation (10.1) is used to determine the value for SSPADD. The detail of the
SSPCON1 setting should be explored by comparing it with the register details in
Figure 10.14.
• All major I2C actions in the program are undertaken with the use of subroutines
and it is instructive to look at these.
• The program starts, from comment ;send opening string, by transmitting the
character message ‘Derbot’ to the hand controller.
• This is done in a single multiple-byte message. First the address is sent, using
subroutine I2C send add.

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