DAY THIRTY FIVE

Gate Circuit
Learning & Revision for the Day
u Logic Gates and Truth Table u The AND Gate u Combination of Logic Gates
u The OR Gate u The NOT Gate u Transistor as a Switch

Logic Gates and Truth Table

Logic Gates The digital circuit that can be analysed with the help of Boolean algebra is
called logic gate or logic circuit. A logic gate has two or more inputs but only one input.
There are primarily three logic gates namely the OR gate, the AND gate and the NOT
gate.
Truth Table The operation of a logic gate or circuit can be represented in a table which
contains all possible inputs and their corresponding outputs is called the truth table. To
write the truth table, we use binary digits 1 and 0.

The OR Gate
The OR gate is a device has two or more inputs and one output. This device combines
two inputs to give one output. The logic symbol of OR gate is
A
Y
B

The Boolean expression for OR gate is

Y =A+B
This indicates Y equals A OR B. PREP
Truth table for OR gate (Y = A + B ) MIRROR
A B Y Your Personal Preparation Indicator

0 0 0 u No. of Questions in Exercises (x)—

0 1 1 u No. of Questions Attempted (y)—
1 0 1 u No. of Correct Questions (z)—
(Without referring Explanations)
1 1 1
u Accuracy Level (z / y × 100)—
The output of an OR gate assumes 1 if one of more inputs assume 1. The output is high
when either of inputs A or B is high, but not if both A and B are low.
u Prep Level (z / x × 100)—

In order to expect good rank in JEE,

your Accuracy Level should be above
85 & Prep Level should be above 75.
DAY THIRTY FIVE GATE CIRCUIT 379

The logic symbol of NAND gate is shown as

The AND Gate
The AND gate a device has also two or more inputs and one A
output. The output of AND gate is equal to product of its Y
B
inputs. The logic symbol of AND gate is
A
Y The Boolean expression of NAND gate is Y = A ⋅ B, which
B
indicates ‘A AND B are negated’.
The logic symbol of AND gate is given as under. The Boolean Truth table for NAND gate
expression for AND gate is Y = A ⋅ B, this indicates Y equals to
A B Y′ Y
A AND B.
0 0 0 1
Truth table for AND gate (Y = A ⋅ B ) 1 0 0 1
A B Y 0 1 0 1
0 0 0 1 1 1 0
0 1 0
1 0 0
2. NOR Gate
1 1 1
In this type of gate, the output of OR gate is fed to input of the
The output of an AND gate is 1 only, when all the inputs NOT gate and final output is obtained at output of the NOT
assume 1. gate.
A y′
y
The NOT Gate B
The NOT gate is a device which has only one input and only
one output. Its output is complement of input. The logic The logic symbol of NOR gate is shown as
symbol of NOT gate is as shown in figure.
A
y=A+B
B
A Y
The Boolean expression for NOR gate is Y = A + B, which
The Boolean expression for NOT gate is indicates that ‘A OR B are negated’
Y = A,
Truth table for NOR gate
which indicates Y equals NOT A.
A B Y′ Y
Truth Table for NOT gate (Y = A ) 0 0 0 1
A Y 1 0 1 0
0 1 0 1 1 0
1 0 1 1 1 0

The output of a NOT gate assumes 1, if input is 0 and NOTE • NAND and NOR gates are known as universal gate.
vice-versa. These basic gates (OR, AND and NOT) can be
• The Boolean expressions obey the commutative law,
combined in various ways to provide large number of
associative law as well as distributive law.
complicated digital circuits.
Commutative law
(i) A + B = B + A (ii) A ⋅ B = B ⋅ A
Combination of Logic Gates Associative law
(iii) A + (B + C ) = ( A + B ) + C (iv) ( A ⋅ B ) ⋅ C = A ⋅ (B ⋅ C )
NAND gate and NOR gate are used to make any gate.
Distributive law
(v) A ⋅ (B + C ) = A ⋅ B + A ⋅ C
1. NAND Gate (vi) A + A ⋅ B = A + B
In this type of gate, the output of AND gate is fed to input of a (vii) A + A ⋅ B = A
NOT gate and final output is obtained at output of NOT gate. (viii) A ⋅ ( A + B ) = A
(ix) A ⋅ ( A + B ) = A ⋅ B
A
Y′ (x) A ⋅ B = A + B
Y
B (xi) A + B = A ⋅ B
(xii) A = A
380 40 DAYS ~ JEE MAIN PHYSICS DAY THIRTY FIVE

(Vce ) across it. In both the cut-off and saturation regions, the
Transistor as a Switch power dissipated by the transistor is at its minimum.
The circuit resembles that of the Common-Emitter circuit. Vcc
The difference this time is that to operate the transistor as a
switch the transistor needs to be turned either fully ‘‘OFF’’ Load
Flyback Relay
(Cut-off) fully ‘‘ON’’ (Saturated). Diode Output
An ideal transistor switch would have an infinite resistance
when turned ‘OFF’ resulting in zero current flow and zero Ic
RB ia Vce
resistance, when turned ‘‘ON’’, resulting in maximum current
flow. + β
Vin Ω R
In practice, when turned ‘‘OFF’, small leakage currents flow –
through the transistor and when fully “ON” the device has
a low resistance value causing a small saturation voltage

DAY PRACTICE SESSION 1

FOUNDATION QUESTIONS EXERCISE

1 The output of a two input OR gate is fed to a NOT gate, 6 Which of the following gates will have an output of 1 ?
the new gate obtained is
1 0
(a) OR gate (b) NOT gate (a) (b)
(c) NOR gate (d) NAND gate 0 1

2 Which of the following is the truth table for NOT gate? 0

(c) (d) None of these
 1 1  1 0  0 1  0 1 1
(a)   (b)   (c)   (d)  
 0 0  0 0  1 0  1 1
3 The output of OR gate is high 7 The following truth table is for
(a) if either or both the inputs are 1 A B Y
(b) only if both inputs are 1
1 1 0
(c) if either input is zero
(d) if both inputs are zero 1 0 1
0 1 1
4 To get an output 1 from the circuit as shown in the figure,
0 0 1
the input must be
A
(a) NAND (b) AND (c) XOR (d) NOT

B 8 Which of the following is the truth table for the circuit

Y
below?

A Y
C
A Y A Y
(a) A = 0, B = 1, C = 0
(b) A = 1, B = 0, C = 0 (a) 1 0 (b) 0 0
(c) A = 1, B = 0, C = 1 0 1 1 1
(d) A = 1, B = 1, C = 0
A Y A Y
5 Digital circuit can be made by the repetitive use of (c) (d) 0 1
1 1
(a) OR gates (b) AND gates 0 0
0 1
(c) NOT gates (d) NAND gates
DAY THIRTY FIVE GATE CIRCUIT 381

9 The circuit as shown in figure below will act as (c) NOR gate (d) NAND gate

A Y′ 15 The diagram of a logic circuit is given below. The output

Y F of the circuit is given by
B

(a) OR gate (b) AND gate W

(c) XOR gate (d) None of these X
10 The circuit as shown below will acts as F

A W
Y Y

B (a)W ⋅ (X + Y ) (b)W ⋅ (X ⋅Y )
(c)W + (X ⋅Y ) (d)W + (X + Y )
(a) AND gate (b) OR gate
(c) NAND gate (d) NOR gate 16 The output, Y of given logic circuit is
A
11 The circuit is equivalent to
B
NOR NAND NOT
A Y
Y
B
(a) AND gate (b) NAND gate
(c) NOR gate (d) OR gate C
12 The output of an OR gate is connected to both the inputs (a) A ⋅ (B + C) (b) A ⋅ (B ⋅ C)
of a NAND gate. The combination will serve as a (c) (A + B) ⋅ (A + C) (d) A + B + C
ª AIEEE 2011 17 What will be the input of A and B for the Boolean
(a) OR gate (b) NOT gate expression ( A + B ) ⋅ ( A ⋅ B ) = 1 ?
(c) NOR gate (d) AND gate
(a) 0, 0 (b) 0, 1
13 Truth table for system of four NAND gates as shown in (c) 1, 0 (d) 1, 1
figure is ª AIEEE 2012 18 Which of the following is not equal to 1 in Boolean
A algebra?
(a) A + 1 (b) A ⋅ A
Y
(c) A + A (d) A ⋅ A

B
Direction (Q.Nos. 19-21) Each of these questions contains
A B Y A B Y two statements: Statement I and Statement II. Each of these
0 0 0 0 0 0 questions also has four alternative choices, only one of which
(a) 0 1 1 (b) 0 1 0 is the correct answer. You have to select one of the codes
1 0 1 1 0 1
(a),(b), (c),(d) given below.
1 1 0 1 1 1 (a) Statement I is true, Statement II is true; Statement II is
the correct explanation for Statement I
(b) Statement I is true, Statement II is true; Statement II is
A B Y A B Y
not the correct explanation for Statement I
0 0 1 0 0 1
(c) Statement I is true; Statement II is false
(c) 0 1 1 (d) 0 1 0
(d) Statement I is false; Statement II is true
1 0 0 1 0 0
1 1 0 1 1 1 19 Statement I The logic gate NOT cannot be built using
diode.
14 The combination of gates shown below yields Statement II The output voltage and the input voltage of
the diode have 180° phase difference.
A
20 Statement I NOT gate is also called invertor.
X
Statement II NOT gate inverts the input signal.
B 21 Statement I NAND or NOR gates are called digital
building blocks.
ª AIEEE 2010
(a) OR gate (b) NOT gate Statement II The repeated use of NAND or NOR gates
can produce all the basic or complicated gates.
382 40 DAYS ~ JEE MAIN PHYSICS DAY THIRTY FIVE

DAY PRACTICE SESSION 2

PROGRESSIVE QUESTIONS EXERCISE

1 The output of an OR gate is connected to both the inputs 4 In the following combinations of logic gates, the outputs
of a NAND gate , the truth table is of A, B and C are respectively

A B Y A B Y (A) 1
1
0 0 1 0
1
(a) 0 0 (b)
1 1 1 0 1 0 (B) 0
0 1 0 1 0 0 1
1 1 0
A B Y 1
(C)
1
0 0 0 0
(c) (d) None of these
0 1 0
1 0 0 (a) 0,1,1
1 1 1 (b) 0,1, 0
(c) 1,1, 0
2 For the given combination of gates, if the logic states of (d) 1, 0,1
inputs A , B and C are as follows. A = B = C = 0 and
5 The truth table of the following combination of gates is
A = B = 1, C = 0, then the logic states of output D are
A
B A Y
B
D
C
(a) Inputs Outputs
(a) 0, 0 (b) 0, 1 (c) 1, 0 (d) 1, 1
A B A⋅B Y
3 The real time variation of input signals A and B are as
0 0 0 1
shown below.If the inputs are fed into NAND gate, then
0 1 1 0
select the output signal from the following
0 0 0 1
1 1 1 0
A
A
Y (b) Inputs Outputs
B B
A B A⋅ B Y

t(s) 1 1 0 1
0 1 0 1
1 0 0 0
Y Y
0 1 1 1
(a) (b)
(c) Inputs Outputs

0 2 4 6 8 t(s) 0 2 4 6 8 t(s) A B A+ B Y = A ⋅ ( A + B)
0 0 0 0
0 1 1 0
1 0 1 1
Y Y
(c) (d) 1 1 1 1

(d) None of the above

0 2 4 6 8 t(s) 0 2 4 6 8 t(s)
DAY THIRTY FIVE GATE CIRCUIT 383

6 The logic circuit shown below has the input waveforms A

and B as shown. Pick out the correct output waveform. A C
(a)
B
A
A
Y (b)
B C
B

Input A (c) A
B C
Input B
A
(d) C
B
(a)
9 Consider two n-p-n transistors as shown in figure. If 0 V
corresponds to false and 5 V corresponds to true, then the
(b) output at C corresponds to
5V

(c)
C
1
A
(d)

2
B
7 In the adjacent circuit, A and B represent two inputs and
C represents the output,
A
ª JEE Main (Online) 2013
C
(a) A NAND B (b) A OR B
B (c) A AND B (d) A NOR B
10 If a, b, c and d are inputs to a gate and x is its output
every time, then as per the following time graph, the gate
is ª JEE Main 2016 (Offline)
The circuit represents
(a) NOR gate (b) AND gate a. b.
(c) NAND gate (d) OR gate
8 Which of the following circuits has given outputs? c. d.

A B C x.
0 0 0 (a) NOT
0 1 0 (b) AND
1 0 1 (c) OR
1 1 0 (d) NAND
ª JEE Main (Online) 2013

ANSWERS

SESSION 1 1 (c) 2 (c) 3 (a) 4 (c) 5 (d) 6 (c) 7 (a) 8 (a) 9 (a) 10 (a)
11 (c) 12 (c) 13 (a) 14 (a) 15 (d) 16 (c) 17 (a) 18 (b) 19 (c) 20 (a)
21 (a)

SESSION 2 1 (b) 2 (d) 3 (b) 4 (c) 5 (c) 6 (a) 7 (d) 8 (c) 9 (a) 10 (c)
384 40 DAYS ~ JEE MAIN PHYSICS DAY THIRTY FIVE

Hints and Explanations

SESSION 1 = (A + B)+ (A + B) = A + B 17 The given Boolean expression can be
Output of NOT gate, written as
1 The combination of OR and NOT gates
is NOR gate. Y = Y2 = A + B Y = ( A + B ) × ( AB )
which is output of NOR gate. = ( A × B )× ( A + B )
2 Truth table of NOT gate is
12 A = ( A × A ) × B + A( B × B )
A B Y′ Y
B = A×B + A×B
A B
Y ¢= A + B and Y = Y ¢ = A + B = A×B
0 1
1 0 i.e. output of a NOR gate. So, the truth table is

3 OR gate output is high, if anyone or 13 Boolean expression for the given circuit A B Y
both input are high. 0 0 1
Y = (( A × ( A × B ))) × (B × ( A × B ))
4 The Boolean expression for the given 1 0 0
combination is Y = ( A + B ) × C = ( A + A × B ) × (B + A × B )
0 1 0
The truth table is = ( A + A × B ) + (B + ( A × B )) 1 1 0
A B C A+ B Y = (A + B) C = A ×(A × B) + B ×(A × B)
0 0 0 0 0 = A ×(A + B) + B ×(A + B)
18 Here, A × A = 0 always when either
A = 0 or 1.
0 0 1 0 0
= A×B + B× A
0 1 0 1 0 19 NOT gate inverts the signal applied to it.
0 1 1 1 1 But in diode, the input and output are in
A B A B A× B B× A Y
same phase. Thus, NOT gate cannot be
1 0 0 1 0 0 0 1 1 0 0 0 built using diode.
1 0 1 1 1 0 1 1 0 0 1 1
1 1 0 1 0 1 0 0 1 1 0 1 20 NOT gate inverts the input signal i.e. if
1 1 0 0 0 0 0 input is 1 then output will be zero or
1 1 1 1 1
vice-versa. Therefore, it is called as
So, option (a) is correct. invertor. NOT gate inverts the input
Hence, A = 1, B = 0 and C = 1
14 Truth table for given combination is order means that for low input, it gives
5 The repetitive use of NAND and NOR
high output or for high input, it gives low
gate gives digital circuits. A B X output.
6 For option (c), it is a NAND gate, its 0 0 0
output = 01
. = 0=1 0 1 1 21 NAND or NOR gates are called universal
1 0 1 (digital) building blocks because using
7 For NAND gate, Y = AB these two types of gates we can produce
1 1 1
8 The output of the NAND gate is all the basic gates namely OR, AND or
This comes out to be truth table of OR
Y = A× A = A + A = A other complex gates.
gate.
9 The output of NOR gate is made input 15 The output F = (W + X ) × (W + Y ) SESSION 2
for NOT gate.
Y = A + B= A+B
= (W + X ) + (W + Y ) 1 When two inputs of a NAND gate are
=W + X +W + Y joined together, it works as a NOT gate.
10 The output of two NOT gate is input for The OR gate connected to this NOT gate
=W + X + Y
NOR gate. results is a NOR gate.
Hence, Y = A + B = A × B = A × B 16 The gate circuit is given as
2 The output D for the given combination
(AND gate) A A+B
D = ( A + B )× C = ( A + B ) + C
11 The gate circuit can be shown by given B
two points A and B. If A = B = C = 0, then
Y
NOR NAND NOT D = (0 + 0) + 0
A Y1 Y2
Y A+C = 0+ 0
B
C =1+ 1=1
Output of NOR gate, Y1 = A + B
If A = B = 1, C = 0, then
Output of NAND gate, Y =(A+B) (A+C)
D = (1 + 1) + 0
Y2 = Y1 × Y1 = A + B × A + B For this circuit, output
=1+ 0
= A+ B+ A+ B Y = (A + B)(A + C)
= 0+ 1 = 1
DAY THIRTY FIVE GATE CIRCUIT 385

3 From real time variation of input Inputs Outputs and NOT gate
signals,we can from truth table for A X = NOT A
A B A+B Y = A × (A + B)
and B and conclude output from NAND Rs
gate. 0 0 0 0

Inputs Output 0 1 1 0

A B Y 1 0 1 1
0 0 1 1 1 1 1
1 0 1 6 Truth table V=6V
0 0 1
A B Y Clearly, the function X = NOT (A AND
1 1 0
0 0 0 B) of the logical variables A AND B is
0 0 1
called NAND gate.
0 1 0
From output, we can show real time 10 Output of OR gate is 0 when all inputs
1 0 0
variation of output signal as below.
1 1 1 are 0 and output is 1 when atleast one of
0 0 0 the inputs is 1.
Observing output x It is 0 when all
Y 7 If we give the following inputs to A and
B, then corresponding output is shows inputs are 0 and it is 1 when atleast one
in table of the inputs is 1.
t(s) A B C \ The gate is OR.
0 0 0 Alternative Method
4 A. NAND operation on (1, 1) = 0 0 1 1
NOT operation on (0) = 1 1 0 1 OR Gate
OR operation on (1, 0) = 1 1 1 1 a b c d x
B. NOT operation on (0, 1) = (1, 0) The above table is similar to OR gate. 0 0 0 0 0
NAND operation on (1, 0) = 1 0 0 0 1 1
8 Observing the given gate we observe
C. OR operation on (1, 1) = 1 that gate would be same as given in
0 0 1 0 1
AND operation on (1, 0) = 0 option in which.
The values A = 0, B = 0 gives output 0 0 0 1 1 1
5 Let us draw the given combination The values A = 0, B = 1 gives output 0
pointing out that the first gate is OR 0 1 0 0 1
The values A = 1, B = 0 gives output 1
gate second gate is AND gate. The
The value A = 1, and B = 1 gives output 0 0 1 0 1 1
inputs of the OR gate, are A and B ,
and its output is A + B that is A OR B. 9 From the figure of AND gate 0 1 1 0 1
The inputs of the AND gate are 0 1 1 1 1
A
A and A + B and its output is
A × ( A + B ) that is A AND (A or B ). The X = A and B 1 0 0 0 1
truth table for the output is Y
= A.( A + B ) is as follows B

A V = 5V
A Y
AND
OR V=0
A·(A + B)
A+B
B