UNIT-IV

Combinational Logic
 Logic circuits for digital systems may be combinational or sequential.

 A combinational circuit consists of input variables, logic gates, and output variables

Analysis procedure

To obtain the output Boolean functions from a logic diagram, proceed as follows:

1. Label all gate outputs that are a function of input variables with arbitrary symbols.
Determine the Boolean functions for each gate output.
2. Label the gates that are a function of input variables and previously labeled gates with
other arbitrary symbols. Find the Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained.
4. By repeated substitution of previously defined functions, obtain the output Boolean
functions in terms of input variables.
Design Procedure:

1. The problem is stated

2. The number of available input variables and required output variables is
determined. 3.The input and output variables are assigned letter symbols.
4.The truth table that defines the required relationship between inputs and outputs is derived.
5.The simplified Boolean function for each output is obtained.
6.The logic diagram is drawn.

BOOLEAN ALGEBRA :

 Basic Definitions

  Axiomatic Definition of Boolean Algebra

 Basic Theorems and properties of Boolean Algebra


 Boolean Functions

 Canonical and Standard Forms, Other Logic Operations

 Digital Logic Gates

 Integrated Circuits
Boolean Algebra: Boolean algebra, like any other deductive mathematical system, may be defined
with aset of elements, a set of operators, and a number of unproved axioms or postulates. A set of
elements is anycollection of objects having a common property. If S is a set and x and y are certain
objects, then x Î Sdenotes that x is a member of the set S, and y ÏS denotes that y is not an element of
S. A set with adenumerable number of elements is specified by braces: A = {1,2,3,4}, i.e. the
elements of set A are thenumbers 1, 2, 3, and 4. A binary operator defined on a set S of elements is a
rule that assigns to each pair ofelements from S a unique element from S._ Example: In a*b=c, we
say that * is a binary operator if it specifies a rule for finding c from the pair (a,b)and also if a, b, c Î
S.

CLOSURE: The Boolean system is closed with respect to a binary operator if for every pair of
Boolean values,it produces a Boolean result. For example, logical AND is closed in the Boolean
system because it accepts only Boolean operands and produces only Boolean results.

_ A set S is closed with respect to a binary operator if, for every pair of elements of S, the binary
operator specifies a rule for obtaining a unique element of S.

For example, the set of natural numbers N = {1, 2, 3, 4, … 9} is closed with respect to the binary
operator plus (+) by the rule of arithmetic addition, since for any a, b Î N we obtain a unique c Î N by
the operation a + b = c.
ASSOCIATIVE LAW:A binary operator * on a set S is said to be associative whenever (x * y) * z
= x * (y * z) for all x, y, z Î S, forall Boolean values x, y and z.

COMMUTATIVE LAW:

A binary operator * on a set S is said to be commutative whenever x * y = y * x for all x, y, z є

IDENTITY ELEMENT:
A set S is said to have an identity element with respect to a binary operation * on S if there exists
an element e є S with the property e * x = x * e = x for every x є S
BASIC IDENTITIES OF BOOLEAN ALGEBRA

Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two
or more elements and the two operators · and + which refer to logical AND and logical OR

 x + 0 = x


 x · 0 = 0


 x + 1 = 1


 x · 1 = 1


 x + x = x


 x · x = x


 x + x’ = x


 x · x’ = 0


 x + y = y + x

 xy = yx
 x + ( y + z ) = ( x + y ) + z

 x (yz) = (xy) z
 x ( y + z ) = xy + xz


 x + yz = ( x + y )( x + z)

 ( x + y )’ = x’ y’


 ( xy )’ = x’ + y’


 (x’)’ = x


DeMorgan's Theorem

(a) (a + b)' = a'b'

(b) (ab)' = a' + b'

Generalized DeMorgan's Theorem

(a) (a + b + … z)' = a'b' … z'

(b) (a.b … z)' = a' + b' + … z„


AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA:

1. Closure
a. Closure with respect to (wrt) OR (+)
b. Closure with respect to AND (•)
2. Identity
a. Identity element wrt to OR : 0
b. Identity element wrt to AND : 1 3.
Commutative Property
a. Commutative Property wrt to OR : x + y = y + x
b. Commutative Property wrt to AND : x · y = y ·x

4. Distributive Property
a. x · (y + z) = (x·y) + (x·z)
b. x + (y·z) = (x + y)(x + z) 5.
Existence of Complement
a. x + x‟ = 1
b. x · x‟ = 0

LOGIC GATES

Formal logic: In formal logic, a statement (proposition) is a declarative sentence that is either
true(1) or false (0). It is easier to communicate with computers using formal logic.

• Boolean variable: Takes only two values – either true (1) or false (0). They are used as basic
units of formal logic.
• Boolean algebra: Deals with binary variables and logic operations operating on those
variables.
• Logic diagram: Composed of graphic symbols for logic gates. A simple circuit sketch that
represents inputs and outputs of Boolean functions.

Properties of XOR Gates

1. XOR (also ) : the “not-equal” function
 2. XOR(X,Y) = X  Y = X’Y + XY’
3. Identities:
– X0=X
– X1=X’
– XX=0
– XX’=1
4. Properties:
– XY=YX
– (XY)W=X(YW)

Universal Logic Gates

NAND and NOR gates are called Universal gates. All fundamental gates (NOT, AND, OR) can
be realized by using either only NAND or only NOR gate. A universal gate provides flexibility
and offers enormous advantage to logic designers.

NAND as a Universal Gate

NAND Known as a “universal” gate because ANY digital circuit can be implemented with
NAND gates alone.
To prove the above, it suffices to show that AND, OR, and NOT can be implemented
using NAND gates only.

\
Canonical and Standard Forms
We need to consider formal techniques for the simplification of Boolean functions.
Identical functions will have exactly the same canonical form.
5. Minterms and Maxterms
6. Sum-of-Minterms and Product-of- Maxterms
7. Product and Sum terms
8. Sum-of-Products (SOP) and Product-of-Sums (POS)

Definitions
Literal: A variable or its complement
Product term: literals connected by •
Sum term: literals connected by +
Minterm: a product term in which all the variables appear exactly once, either complemented or
uncomplemented.
Maxterm: a sum term in which all the variables appear exactly once, either complemented or
uncomplemented.
Canonical form: Boolean functions expressed as a sum of Minterms or product of Maxterms are said to be
in canonical form.

Minterm
3. Represents exactly one combination in the truth table.
4. Denoted by mj, where j is the decimal equivalent of the minterm’s corresponding binary
combination (bj).
5. A variable in mj is complemented if its value in bj is 0, otherwise is uncomplemented.

Example: Assume 3 variables (A, B, C), and j=3. Then, bj = 011 and its corresponding minterm is
denoted by mj = A’BC

Maxterm
7. Represents exactly one combination in the truth table.
8. Denoted by Mj, where j is the decimal equivalent of the maxterm’s corresponding binary
combination (bj).
9. A variable in Mj is complemented if its value in bj is 1, otherwise is uncomplemented.

Example: Assume 3 variables (A, B, C), and j=3. Then, bj = 011 and its corresponding maxterm is
denoted by Mj = A+B’+C’
Truth Table notation for Minterms and Maxterms
 Minterms and Maxterms are easy to denote using a truth table.
Example: Assume 3 variables x,y,z (order is fixed)

x y z Minterm Maxterm
0 0 0 x’y’z’ = m0 x+y+z = M0
0 0 1 x’y’z = m1 x+y+z’ = M1
0 1 0 x’yz’ = m2 x+y’+z = M2
0 1 1 x’yz = m3 x+y’+z’= M3
1 0 0 xy’z’ = m4 x’+y+z = M4
1 0 1 xy’z = m5 x’+y+z’ = M5
1 1 0 xyz’ = m6 x’+y’+z = M6
1 1 1 xyz = m7 x’+y’+z’ = M7

Canonical Forms
  Every function F() has two canonical forms:
– Canonical Sum-Of-Products (sum of minterms)
– Canonical Product-Of-Sums (product of maxterms)
Canonical Sum-Of-Products:
The minterms included are those mj such that F( ) = 1 in row j of the truth table for F( ).
Canonical Product-Of-Sums:
The maxterms included are those Mj such that F( ) = 0 in row j of the truth table for F( ).

Example a b c f1
Consider a Truth table for f1(a,b,c) at right 0 0 0 0
The canonical sum-of-products form for f1
is f1(a,b,c) = m1 + m2 + m4 + m6 0 0 1 1
= a’b’c + a’bc’ + ab’c’ + abc’ 0 1 0 1
The canonical product-of-sums form for f1 0 1 1 0
is f1(a,b,c) = M0 • M3 • M5 • M7
(a+b+c)•(a+b’+c’)• (a’+b+c’)•(a’+b’+c’). 1 0 0 1
1 0 1 0
 Observe that: mj = Mj’ 1 1 0 1
1 1 1 0
Shorthand: ∑ and ∏
 f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-products form, and
m(1,2,4,6) indicates that the minterms to be included are m1, m2, m4, and m6.
 f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is a product-of-sums form, and
M(0,3,5,7) indicates that the maxterms to be included are M0, M3, M5, and M7.
 Since mj = Mj’ for any j,
m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)
•
Conversion between Canonical Forms
 Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in the original form with those
that do not.
 Example:
f1(a,b,c)= a’b’c + a’bc’ + ab’c’ + abc’
m1 + m2 + m4 + m6
∑(1,2,4,6)
∏(0,3,5,7)
 (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
Standard Forms

Another way to express Boolean functions is in standard form. In this configuration, the terms that form
the function may contain one, two, or any number of literals.
There are two types of standard forms: the sum of products and products of sums.
The sum of products is a Boolean expression containing AND terms, called product terms, with one or more
literals each. The sum denotes the ORing of these terms. An example of a function expressed as a sum of
products is
F1 = y’ + xy + x’yz’
The expression has three product terms, with one, two, and three literals. Their sum is, in effect, an OR
operation.
A product of sums is a Boolean expression containing OR terms, called sum terms. Each term may have any
number of literals. The product denotes the ANDing of these terms. An example of a function expressed as a
product of sums is
F2 = x(y’ + z)(x’ + y + z’)
This expression has three sum terms, with one, two, and three literals. The product is an AND operation.
Conversion of SOP from standard to canonical form
Example-1.
Express the Boolean function F = A + B’C as a sum of minterms.
Solution: The function has three variables: A, B, and C. The first term A is missing two variables;
therefore, A=A(B+B’)=AB+AB’
This function is still missing one variable, so
A = AB(C + C’) + AB’ (C + C’)
= ABC + ABC’ + AB’C + AB’C’
The second term B’C is missing one variable; hence,
B’C = B’C(A + A’) = AB’C + A’B’C
Combining all terms, we have
F=A+B’C
= ABC + ABC’ + AB’C + AB’C’+ A’B’C
But AB’C appears twice, and according to theorem (x + x = x), it is possible to remove one of
those occurrences. Rearranging the minterms in ascending order, we finally obtain
F = A’B’C + AB’C + AB’C + ABC’ + ABC
= m1 + m4 + m5 + m6 + m7
When a Boolean function is in its sum‐of‐minterms form, it is sometimes convenient to express the
function in the following brief notation:
F(A, B, C) = ∑m (1, 4, 5, 6, 7)

Example-2.
Express the Boolean function F = xy + x’z as a product of maxterms.
Solution: First, convert the function into OR terms by using the distributive law:
F = xy + x’z = (xy + x’)(xy + z)
(x + x’)(y + x’)(x + z)(y + z)
 (x’+ y)(x + z)(y + z)
The function has three variables: x, y, and z. Each OR term is missing one variable;
therefore, x’+ y = x’ + y + zz’ = (x’ + y + z)(x’ + y + z’)
x + z = x + z + yy’ = (x + y + z)(x + y’ + z)
y + z = y + z + xx’ = (x + y + z)(x’ + y + z)
Combining all the terms and removing those which appear more than once, we finally obtain
F = (x + y + z)(x + y’ + z)(x’ + y + z)(x’ + y + z)
F= M0M2M4M5
A convenient way to express this function is as
follows: F(x, y, z) = πM(0, 2, 4, 5)
The product symbol, π, denotes the ANDing of maxterms; the numbers are the indices of the maxterms of
the function.
 Minimization Techniques

Two-variable k-map:
2
A two-variable k-map can have 2 =4 possible combinations of the input variables A and
B. Each of these combinations, , B,A ,AB(in the SOP form) is called a minterm. The minterm
may be represented in terms of their decimal designations – m0 for , m1 for
B,m2 for A and m3 for AB, assuming that A represents the MSB. The letter m stands for
minterm and the subscript represents the decimal designation of the minterm. The presence or
absence of a minterm in the expression indicates that the output of the logic circuit assumes logic
1 or logic 0 level for that combination of input variables.
The expression f= ,+ B+A +AB , it can be expressed using min

term as F= m0+m2+m3=∑m(0,2,3)

Using Truth Table:

Inputs Minterm
Output
A B F
0 0 0 1
1 0 1 0
2 1 0 1
3 1 1 1
A 1 in the output contains that particular minterm in its sum and a 0 in that column indicates that
the particular mintermdoes not appear in the expression for output . this information can also be
indicated by a two-variable k-map.

Mapping of SOP Expresions:

A two-variable k-map has 22=4 squares .These squares are called cells. Each square on the k-
map represents a unique minterm. The minterm designation of the squares are placed in any
square, indicates that the corresponding minterm does output expressions. And a 0 or no entry in
any square indicates that the corresponding minterm does not appear in the expression for output.

The minterms of a two-variable k-map

The mapping of the expressions =∑m(0,2,3)is

k-map of ∑m(0,2,3)

EX: Map the expressions f= B+A

F= m1+m2=∑m(1,2)The k-map is

Minimizations of SOP expressions:

To minimize Boolean expressions given in the SOP form by using the k-map, look for
adjacent adjacent squares having 1‘s minterms adjacent to each other, and combine them to form
larger squares to eliminate some variables. Two squares are said to be adjacent to each other, if
their minterms differ in only one variable. (i.e, B & A differ only in one variable. so they may be
combined to form a 2-square to eliminate the variable B.similarly all other.

The necessary condition for adjacency of minterms is that their decimal designations must
differ by a power of 2. A minterm can be combined with any number of minterms adjacent to it
to form larger squares. Two minterms which are adjacent to each other can be combined to form
a bigger square called a 2-square or a pair. This eliminates one variable – the variable that is not
common to both the minterms. For EX:

m0 and m1 can be combined to yield,

f1 = m0+m1= + B= (B+

)= m0 and m2 can be combined to yield,

( +

f = + = )=
2 m0+m2=

m1 and m3 can be combined to yield,

 f3= m1+m3= B+AB=B( + )=B

m2 and m3 can be combined to yield,

f4 = m2+m3=A +AB=A(B+ )=A

m0 ,m1 ,m2 and m3 can be combined to yield,

 ++A +AB

 (B+ ) +A(B+ )

 +A

=1

f1= f2= f3=B f4=A f5=1

The possible minterm groupings in a two-variable k-map.

Two 2-squares adjacent to each other can be combined to form a 4-square. A 4-square
eliminates 2 variables. A 4-square is called a quad. To read the squares on the map after
minimization, consider only those variables which remain constant through the square, and
ignore the variables which are varying. Write the non complemented variable if the variable is
remaining constant as a 1, and the complemented variable if the variable is remaining constant as
a 0, and write the variables as a product term. In the above figure f 1 read as , because, along the
square , A remains constant as a 0, that is , as , where as B is changing from 0 to 1.

EX: Reduce the minterm f= +A +AB using mapping Expressed in terms of minterms, the given
expression is F=m0+m1+m2+ m3=m∑(0,1,3)& the figure shows the k-map for f and its reduction .
In one 2-square, A is constant as a 0 but B varies from a 0 to a 1, and in the other 2-square, B is
constant as a 1 but A varies from a 0 to a 1. So, the reduced expressions is +B.

It requires two gate inputs for realization as

f= +B (k-map in SOP form, and logic diagram.)
 The main criterion in the design of a digital circuit is that its cost should be as low as
possible. For that the expression used to realize that circuit must be minimal.Since the cost is
proportional to number of gate inputs in the circuit in the circuit, an expression is considered
minimal only if it corresponds to the least possible number of gate inputs. & there is no guarantee
for that k-map in SOP is the real minimal. To obtain real minimal expression, obtain the minimal
expression both in SOP & POS form form by using k-maps and take the minimal of these two
minimals.

The 1‘s on the k-map indicate the presence of minterms in the output expressions, where
as the 0s indicate the absence of minterms .Since the absence of a minterm in the SOP expression
means the presense of the corresponding maxterm in the POS expression of the same .when a
SOP expression is plotted on the k-map, 0s or no entries on the k-map represent the maxterms.
To obtain the minimal expression in the POS form, consider the 0s on the k-map and follow the
procedure used for combining 1s. Also, since the absence of a maxterm in the POS expression
means the presence of the corresponding minterm in the SOP expression of the same , when a
POS expression is plotted on the k-map, 1s or no entries on the k-map represent the minterms.

Mapping of POS expressions:

Each sum term in the standard POS expression is called a maxterm. A function in two
variables (A, B) has four possible maxterms, A+B,A+ , +B, +

. They are represented as M 0, M1, M2, and M3respectively. The uppercase letter M stands for
maxterm and its subscript denotes the decimal designation of that maxterm obtained by treating
the non-complemented variable as a 0 and the complemented variable as a 1 and putting them
side by side for reading the decimal equivalent of the binary number so formed.

For mapping a POS expression on to the k-map, 0s are placed in the squares
corresponding to the maxterms which are presented in the expression an d1s are placed in the
squares corresponding to the maxterm which are not present in the expression. The decimal
designation of the squares of the squares for maxterms is the same as that for the minterms. A
two-variable k-map & the associated maxterms are asthe maxterms of a two-variable k-map

The possible maxterm groupings in a two-variable k-map

Minimization of POS Expressions:

To obtain the minimal expression in POS form, map the given POS expression on to the
K-map and combine the adjacent 0s into as large squares as possible. Read the squares putting
the complemented variable if its value remains constant as a 1 and the non-complemented
variable if its value remains constant as a 0 along the entire square ( ignoring the variables which
do not remain constant throughout the square) and then write them as a sum term.

Various maxterm combinations and the corresponding reduced expressions are shown in
figure. In this f1 read as A because A remains constant as a 0 throughout the square and B
changes from a 0 to a 1. f2 is read as B‘ because B remains constant along the square as a 1 and
A changes from a 0 to a 1. f5
Is read as a 0 because both the variables are changing along the square.

Ex: Reduce the expression f=(A+B)(A+B‘)(A‘+B‘) using mapping.

The given expression in terms of maxterms is f=πM(0,1,3). It requires two gates inputs
for realization of the reduced expression as

F=AB‘
K-map in POS form and logic diagram

In this given expression ,the maxterm M2 is absent. This is indicated by a 1 on the k-map. The
corresponding SOP expression is ∑m2 or AB‘. This realization is the same as that for the POS
form.

Three-variable K-map:

A function in three variables (A, B, C) expressed in the standard SOP form can have eight
possible combinations: A B C , AB C,A BC ,A BC,AB C ,AB C,ABC , and ABC. Each one of
these combinations designate d by m0,m1,m2,m3,m4,m5,m6, and m7, respectively, is called a
minterm. A is the MSB of the minterm designator and C is the LSB.
In the standard POS form, the eight possible combinations are:A+B+C, A+B+C , A+B
+C,A+B + C ,A + B+ C,A + B + C ,A + B + C,A + B + C . Each oneof these combinations
designated by M0, M1, M2, M3, M4, M5, M6, and M7respectively is called a maxterm. A is the
MSB of the maxterm designator and C is the LSB.
3
A three-variable k-map has, therefore, 8(=2 ) squares or cells, and each square on the
map represents a minterm or maxterm as shown in figure. The small number on the top right
corner of each cell indicates the min term or max term designation.
 The three-variable k-map.

The binary numbers along the top of the map indicate the condition of B and C for each
column. The binary number along the left side of the map against each row indicates the
condition of A for that row. For example, the binary number 01 on top of the second column in
fig indicates that the variable B appears in complemented form and the variable C in non-
complemented form in all the minterms in that column. The binary number 0 on the left of the
first row indicates that the variable A appears in complemented form in all the minterms in that
row, the binary numbers along the top of the k-map are not in normal binary order. They are,
infact, in the Gray code. This is to ensure that twophysically adjacent squares are really adjacent,
i.e., their minterms or maxterms differ by only one variable.

Ex: Map the expression f=: C+ + + +ABC

In the given expression , the minterms are : C=001=m1 ; =101=m5;

=010=m2;

=110=m6;ABC=111=m7.
So the expression is f=∑m(1,5,2,6,7)= ∑m(1,2,5,6,7). The corresponding k-map is

K-map in SOP form

++)(++)(A++)(++)

Ex: Map the expression f= (A+B+C),

(
In the given expression the maxterms are
:A+B+C=000=M0; + + =101=M5; + + = 111=M7; A + + =011=M3; + +
=110=M6.
So the expression is f = π M (0,5,7,3,6)= π M (0,3,5,6,7). The mapping of the expression
is
 K-map in POS form.

Minimization of SOP and POS expressions:

For reducing the Boolean expressions in SOP (POS) form plotted on the k-map, look
at the 1s (0s) present on the map. These represent the minterms (maxterms). Look for the
minterms (maxterms) adjacent to each other, in order to combine them into larger squares.
Combining of adjacent squares in a k-map containing 1s (or 0s) for the purpose of simplification
of a SOP (or POS)expression is called looping. Some of the minterms (maxterms) may have
many adjacencies. Always start with the minterms (maxterm) with the least number of
adjacencies and try to form as large as large a square as possible. The larger must form a
geometric square or rectangle. They can be formed even by wrapping around, but cannot be
formed by using diagonal configurations. Next consider the minterm (maxterm) with next to the
least number of adjacencies and form as large a square as possible. Continue this till all the
minterms (maxterms) are taken care of . A minterm (maxterm) can be part of any number of
squares if it is helpful in reduction. Read the minimal expression from the k-map, corresponding
to the squares formed. There can be more than one minimal expression.
Two squares are said to be adjacent to each other (since the binary designations along
the top of the map and those along the left side of the map are in Gray code), if they are
physically adjacent to each other, or can be made adjacent to each other by wrapping around.
For squares to be combinable into bigger squares it is essential but not sufficient that their
minterm designations must differ by a power of two.

General procedure to simplify the Boolean expressions:

T Plot the k-map and place 1s(0s) corresponding to the minterms (maxterms) of the SOP
(POS) expression.
U Check the k-map for 1s(0s) which are not adjacent to any other 1(0). They are isolated
minterms(maxterms) . They are to be read as they are because they cannot be combined
even into a 2-square.
V Check for those 1s(0S) which are adjacent to only one other 1(0) and make them pairs (2
squares).
W Check for quads (4 squares) and octets (8 squares) of adjacent 1s (0s) even if they contain
some 1s(0s) which have already been combined. They must geometrically form a square
or a rectangle.
X Check for any 1s(0s) that have not been combined yet and combine them into bigger
squares if possible.
Y Form the minimal expression by summing (multiplying) the product the product (sum)
terms of all the groups.
Reading the K-maps:
 While reading the reduced k-map in SOP (POS) form, the variable which remains
constant as 0 along the square is written as the complemented (non-complemented) variable and
the one which remains constant as 1 along the square is written as non-complemented
(complemented) variable and the term as a product (sum) term. All the product (sum) terms are
added (multiplied).
Some possible combinations of minterms and the corresponding minimal expressions
readfrom the k-maps are shown in fig: Here f6 is read as 1, because along the 8-square no
variable remains constant. F5 is read as , because, along the 4-square formed by0,m 1,m2 and m3 ,
the variables B and C are changing, and A remains constant as a 0. Algebraically,
f5= m0+m1+m2+m3
= + C+ +
 ( +C)+ B(C+ )

+ B
( +B)=

f3 is read as + , because in the 4-square formed by m0,m2,m6, and m4, the variable A and B are
changing , where as the variable C remains constant as a 0. So it is read as . In the 4-square formed
by m0, m1, m4, m5, A and C are changing but B remains constant as a 0. So it is read as
. So, the resultant expression for f3 is the sum of these two, i.e., + .
f1 is read as + + ,because in the 2-square formed by m0 and m4 , A is changing from a 0 to a 1.
Whereas B and C remain constant as a 0. So it s read as . In the 2-square formed
by m0 and m1, C is changing from a 0 to a 1, whereas A and B remain constant as a 0. So it is
read as .In the 2-square formed by m 0 and m2 , B is changing from a 0 to a 1 whereas A and C
remain constant as a 0. So, it is read as . Therefore, the resultant SOP expression is

++

Some possible maxterm groupings and the corresponding minimal POS expressions read from
the k-map are
In this figure, along the 4-square formed by M 1, M3, M7, M5, A and B are changing from a 0 to
a 1, where as C remains constant as a 1. SO it is read as . Along the 4-squad formed by M 3, M2,
M7, and M6, variables A and C are changing from a 0 to a 1. But B remains constant as a 1. So it
is read as . The minimal expression is the product of these two terms , i.e., f 1 = ( )( ).also in this
figure, along the 2-square formed by M4 and M6 , variable B is changing from a 0 to a 1, while
variable A remains constant as a 1 and variable C remains constant as a 0. SO, read it as

+C. Similarly, the 2-square formed by M7 andM6 is read as + , while the 2-square formed by
M2 and M6 is read as +C. The minimal expression is the product of these sum terms, i.e, f2 =(
+ )+( + )+( +C)

Ex:Reduce the expression f=∑m(0,2,3,4,5,6) using mapping and implement it in AOI logic as
well as in NAND logic.The Sop k-map and its reduction , and the implementation of the minimal
expression using AOI logic and the corresponding NAND logic are shown in figures below

In SOP k-map, the reduction is done as:

.1 m5 has only one adjacency m4 , so combine m5 and m4 into a square. Along this 2-
square A remains constant as 1 and B remains constant as 0 but C varies from 0 to 1. So
read it as A .
.2 m3 has only one adjacency m2 , so combine m3 and m2 into a square. Along this 2-
square A remains constant as 0 and B remains constant as 1 but C varies from 1 to 0. So
read it as B.
.3 m6 can form a 2-square with m2 and m4 can form a 2-square with m0, but observe that
by wrapping the map from left to right m0, m4 ,m2 ,m6 can form a 4-square. Out of these
m2 andm4 have already been combined but they can be utilized again. So make it. Along
this 4-square, A is changing from 0 to 1 and B is also changing from 0 to 1 but C is
remaining constant as 0. so read it as .
4. Write all the product terms in SOP form. So the minimal SOP expression is

fmin=
k-map AOI logic NAND logic

Four variable k-maps:

Four variable k-map expressions can have 24=16 possible combinations of input variables such
as , ,------------ABCD with minterm designations m0,m1 -------------------- m15 respectively in
SOP form & A+B+C+D, A+B+C+ ,---------- + + + with maxterms M0,M1, --------- -
-M15 respectively in POS form. It has 2 4=16 squares or cells.The binary number designations of
rows & columns are in the gray code. Here follows 01 & 10 follows 11 called Adjacency
ordering.

SOP form POS form

EX:
 Five variable k-map:
5
Five variable k-map can have 2 =32 possible combinations of input variable as
, E,--------ABCDE with minterms m0, m1-----m31 respectively in SOP &
A+B+C+D+E, A+B+C+ ,----------
+ + + + with maxterms M0,M1, -----------
5
M31 respectively in POS form. It has 2 =32 squares or cells of the k-map are divided into 2
blocks of
16 squares each.The left block represents minterms from m0 to m15 in which A is a 0, and the
right block represents minterms from m16 to m31 in which A is 1.The 5-variable k-map may
contain 2-squares, 4-squares , 8-squares , 16-squares or 32-squares involving these two blocks.
Squares are also considered adjacent in these two blocks, if when superimposing one block on
top of another, the squares coincide with one another.

Grouping s is
Ex: F=∑m(0,1,4,5,6,13,14,15,22,24,25,28,29,30,31) is SOP

POS is F=πM(2,3,7,8,9,10,11,12,16,17,18,19,20,21,23,26,27)

The real minimal expression is the minimal of the SOP and POS forms.

The reduction is done as

 There is no isolated 1s
 M12 can go only with m13. Form a 2-square which is read as A‘BCD‘
 M0 can go with m2,m16 and m18 . so form a 4-square which is read as B‘C‘E‘
 M20,m21,m17 and m16 form a 4-square which is read as AB‘D‘
 M2,m3,m18,m19,m10,m11,m26 and m27 form an 8-square which is read as C‘d
 Write all the product terms in SOP form.

So the minimal expression is

Fmin= A‘BCD‘+B‘C‘E‘+AB‘D‘+C‘D(16 inputs)

In the POS k-map ,the reduction is done as:

1. There are no isolated 0s

3.

4.M8

∗ M28

6.M30

7. Sum terms in POS form. So the minimal expression in POS

is Fmin= A‘BcD‘+B‘C‘E‘+AB‘D‘+C‘D
Six variable k-map:
6
Six variable k-map can have 2 =64 combinations as ,
,---------
---ABCDEF with minterms m0, m1-----m63 respectively in SOP & (A+B+C+D+E+F),
---------- (
+ + ++ + ) with maxterms M0,M1, -----------M63 respectively in POS form. It has

6
2 =64 squares or cells of the k-map are divided into 4 blocks of 16 squares each.

Some possible groupings in a six variable k-map

Binary Adder
The most basic arithmetic operation is addition. The circuit, which performs the addition of two
binary numbers is known as Binary adder. First, let us implement an adder, which performs
the addition of two bits.
Half Adder
Half adder is a combinational circuit, which performs the addition of two binary numbers A and
B are of single bit. It produces two outputs sum, S & carry, C.

The Truth table of Half adder is shown below.

Inputs Outputs

A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Let, sum, S is the Least significant bit and carry, C is the Most significant bit of the resultant
sum. For first three combinations of inputs, carry, C is zero and the value of S will be either
zero or one based on the number of ones present at the inputs. But, for last combination of
inputs, carry, C is one and sum, S is zero, since the resultant sum is two.

From Truth table, we can directly write the Boolean functions for each output as S=A⊕B

C=AB
We can implement the above functions with 2-input Ex-OR gate & 2-input AND gate.
The circuit diagram of Half adder is shown in the following figure.
In the above circuit, a two input Ex-OR gate & two input AND gate produces sum, S & carry, C
respectively. Therefore, Half-adder performs the addition of two bits.

Full Adder
Full adder is a combinational circuit, which performs the addition of three bits A, B and Cin.
Where, A & B are the two parallel significant bits and C in is the carry bit, which is generated
from previous stage. This Full adder also produces two outputs sum, S & carry, C out, which are
similar to Half adder.

The Truth table of Full adder is shown below.

Inputs Outputs

A B Cin Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0
 1 1 0 1 0

1 1 1 1 1

Let, sum, S is the Least significant bit and carry, C out is the Most significant bit of resultant sum. It
is easy to fill the values of outputs for all combinations of inputs in the truth table. Just count the
number of ones present at the inputs and write the equivalent binary number at outputs. If C in is
equal to zero, then Full adder truth table is same as that of Half adder truth table.
We will get the following Boolean functions for each output after simplification. S=A⊕B⊕Cin
cout=AB+(A⊕B)cin
he sum, S is equal to one, when odd number of ones present at the inputs. We know that Ex-OR
gate produces an output, which is an odd function. So, we can use either two 2input Ex-OR gates
or one 3-input Ex-OR gate in order to produce sum, S. We can implement carry, Cout using two
2-input AND gates & one OR gate. The circuit diagram of Full adder is shown in the
following figure.

This adder is called as Full adder because for implementing one Full adder, we require two
Half adders and one OR gate. If Cin is zero, then Full adder becomes Half adder. We can verify
it easily from the above circuit diagram or from the Boolean functions of outputs of Full adder.
4-bit Binary Adder
The 4-bit binary adder performs the addition of two 4-bit numbers. Let the 4-bit binary
numbers, A=A3A2A1A0A=A3A2A1A0 and B=B3B2B1B0B=B3B2B1B0. We can implement
4-bit binary adder in one of the two following ways.
 Use one Half adder for doing the addition of two Least significant bits and three Full
adders for doing the addition of three higher significant bits.

 Use four Full adders for uniformity. Since, initial carry Cinis zero, the Full adder which
is used for adding the least significant bits becomes Half adder.

For the time being, we considered second approach. The block diagram of 4-bit binary adder is
shown in the following figure.

Here, the 4 Full adders are cascaded. Each Full adder is getting the respective bits of two
parallel inputs A & B. The carry output of one Full adder will be the carry input of subsequent
higher order Full adder. This 4-bit binary adder produces the resultant sum having at most 5 bits.
So, carry out of last stage Full adder will be the MSB.

In this way, we can implement any higher order binary adder just by cascading the required
number of Full adders. This binary adder is also called as ripple carry (binary) adder
because the carry propagates (ripples) from one stage to the next stage.

Binary Subtractor
The circuit, which performs the subtraction of two binary numbers is known as Binary
subtractor. We can implement Binary subtractor in following two methods.

 Cascade Full subtractors

  2‟s complement method
In first method, we will get an n-bit binary subtractor by cascading „n‟ Full subtractors. So, first
you can implement Half subtractor and Full subtractor, similar to Half adder & Full adder.
Then, you can implement an n-bit binary subtractor, by cascading „n‟ Full subtractors. So, we
will be having two separate circuits for binary addition and subtraction of two binary numbers.

In second method, we can use same binary adder for subtracting two binary numbers just by
doing some modifications in the second input. So, internally binary addition operation takes
place but, the output is resultant subtraction.

We know that the subtraction of two binary numbers A & B can be written as,
A−B=A+(2′scomplimentofB)
⇒A−B=A+(1′scomplimentofB)+1

4-bit Binary Subtractor:

The 4-bit binary subtractor produces the subtraction of two 4-bit numbers. Let the 4bit binary
numbers, A=A3A2A1A0A=A3A2A1A0 and B=B3B2B1B0B=B3B2B1B0. Internally, the
operation of 4-bit Binary subtractor is similar to that of 4-bit Binary adder. If the normal bits of
binary number A, complemented bits of binary number B and initial carry (borrow), C in as one
are applied to 4-bit Binary adder, then it becomes 4-bit Binary subtractor. The block diagram
of 4-bit binary subtractor is shown in the following figure.
This 4-bit binary subtractor produces an output, which is having at most 5 bits. If Binary number
A is greater than Binary number B, then MSB of the output is zero and the remaining bits hold
the magnitude of A-B. If Binary number A is less than Binary number B, then MSB of the
output is one. So, take the 2‟s complement of output in order to get the magnitude of A-B.

Binary Adder / Subtractor

The circuit, which can be used to perform either addition or subtraction of two binary numbers
at any time is known as Binary Adder / subtractor. Both, Binary adder and Binary subtractor
contain a set of Full adders, which are cascaded. The input bits of binary number A are directly
applied in both Binary adder and Binary subtractor.

There are two differences in the inputs of Full adders that are present in Binary adder and
Binary subtractor.

 The input bits of binary number B are directly applied to Full adders in Binary adder,
whereas the complemented bits of binary number B are applied to Full adders in Binary
subtractor.

 The initial carry, C0 = 0 is applied in 4-bit Binary adder, whereas the initial carry
(borrow), C0 = 1 is applied in 4-bit Binary subtractor.

We know that a 2-input Ex-OR gate produces an output, which is same as that of first input
when other input is zero. Similarly, it produces an output, which is complement of first input
when other input is one.

Therefore, we can apply the input bits of binary number B, to 2-input Ex-OR gates. The other
input to all these Ex-OR gates is C 0. So, based on the value of C 0, the Ex-OR gates produce
either the normal or complemented bits of binary number B.

4-bit Binary Adder / Subtractor

The 4-bit binary adder / subtractor produces either the addition or the subtraction of two 4-bit
numbers based on the value of initial carry or borrow, C0. Let the 4-bit binary numbers,
A=A3A2A1A0A=A3A2A1A0 and B=B3B2B1B0B=B3B2B1B0. The operation of 4-bit Binary
adder / subtractor is similar to that of 4-bit Binary adder and 4-bit Binary subtractor.
Apply the normal bits of binary numbers A and B & initial carry or borrow, C0 from externally
to a 4-bit binary adder. The block diagram of 4-bit binary adder / subtractor is shown in the
following figure.
If initial carry, C0 is zero, then each full adder gets the normal bits of binary numbers A & B. So,
the 4-bit binary adder / subtractor produces an output, which is the addition of two binary
numbers A & B.

If initial borrow, 0 is one, then each full adder gets the normal bits of binary number A &
complemented bits of binary number B. So, the 4-bit binary adder / subtractor produces an output,
which is the subtraction of two binary numbers A & B.

Binary Multipliers:
In binary multiplication by the paper and pencil method, is modified somewhat in digital
machines because a binary adder can add only two binary numbers at a time.
In a binary multiplier, instead of adding all the partial products at the end, they are added two at a
time and their sum accumulated in a register (the accumulator register). In addition, when the
multiplier bit is a 0,0s are not written down and added because it does not affect the final result.
Instead, the multiplicand is shifted left by one bit.

The multiplication of 1110 by 1001 using this processis

Multiplicand 1110
Multiplier 1001
1110 The LSB of the multiplier is a 1; write down the
multiplicand; shift the multiplicand one position to the left
(11100)
1110 The second multiplier bit is a 0; write down the previous
result 1110; shift the multiplicand to the left again (1 1 1 0
0 0)
 +1110000 The fourth multiplier bit is a 1 write down the new
multiplicand add it to the first partial product to obtain
the final product.
1111110
This multiplication process can be performed by the serial multiplier circuit , which
multiplies two 4-bit numbers to produce an 8-bit product. The circuit consists of following
elements
X register: A 4-bit shift register that stores the multiplier --- it will shift right on the falling
edge of the clock. Note that 0s are shifted in from the left.
B register: An 8-bit register that stores the multiplicand; it will shift left on the falling edge of
the clock. Note that 0s are shifted in from the right.
A register: An 8-bit register, i.e, the accumulator that accumulates the partial products.
Adder:An 8-bit parallel adder that produces the sum of A and B registers. The adder outputs
S7 through S0 are connected to the D inputs of the accumulator so that the sum can be
transferred to the accumulator only when a clock pulse gets through the AND gate.
The circuit operation can be described by going through each step in the multiplication of
1110 by 1001. The complete process requires 4 clock cycles.
1. Before the first clock pulse: Prior to the occurrence of the first clock pulse, the register A
is loaded with 00000000, the register B with the multiplicand 00001110, and the register X
with the multiplier 1001. Assume that each of these registers is loaded using its asynchronous
inputs(i.e., PRESET and CLEAR). The output of the adder will be the sum of A and B,i.e.,
00001110.
2. First Clock pulse:Since the LSB of the multiplier (X0) is a 1, the first clock pulse gets through
the AND gate and its positive going transition transfers the sum outputs into the
accumulator. The subsequent negative going transition causes the X and B registers to shift
right and left, respectively. This produces a new sum of A andB.
3. Second Clock Pulse: The second bit of the original multiplier is now in X 0 . Since this bit is a
0, the second clock pulse is inhibited from reaching the accumulator. Thus, the sum outputs
are not transferred into the accumulator and the number in the accumulator does not
change. The negative going transition of the clock pulse will again shift the X and B registers.
Again a new sum is produced.
4. Third Clock Pulse:The third bit of the original multiplier is now in X 0;since this bit is a 0, the
third clock pulse is inhibited from reaching the accumulator. Thus, the sum outputs are not
transferred into the accumulator and the number in the accumulator does not change. The
negative going transition of the clock pulse will again shift the X and B registers. Again a new
sum is produced.
5.Fourth Clock Pulse: The last bit of the original multiplier is now in X 0 , and since it is a 1, the
positive going transition of the fourth pulse transfers the sum into the accumulator. The
accumulator now holds the final product. The negative going transition of the clock pulse
shifts X and B again. Note that, X is now 0000, since all the multiplier bits have been shifted
out.
1. Magnitude Comparator:

1- bit Magnitude Comparator:

 n
Decoder is a combinational circuit that has „n‟ input lines and maximum of 2 output lines.
One of these outputs will be active High based on the combination of inputs present, when the
decoder is enabled. That means decoder detects a particular code. The outputs of the decoder are
nothing but the min termsof „n‟ input variables (lines), when it is enabled.

2 to 4 Decoder:
Let 2 to 4 Decoder has two inputs A 1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block
diagram of 2 to 4 decoder is shown in the following figure.
One of these four outputs will be „1‟ for each combination of inputs when enable, E is „1‟.
The Truth table of 2 to 4 decoder is shown below.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as
Y3=E.A1.A0Y3=E.A1.A0
Y2=E.A1.A0′Y2=E.A1.A0′
Y1=E.A1′.A0Y1=E.A1′.A0
Y0=E.A1′.A0′
The circuit diagram of 2 to 4 decoder is shown in the following figure.

Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables A1
& A0, when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder will be
equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of three input variables A2, A1 & A0 and 4 to
16 decoder produces sixteen min terms of four input variables A3, A2, A1 & A0.

Encoder:

An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
n
maximum of 2 input lines and „n‟ output lines. It will produce a binary code equivalent to the
n
input, which is active High. Therefore, the encoder encodes 2 input lines with „n‟ bits. It is
optional to represent the enable signal in encoders.

4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block
diagram of 4 to 2 Encoder is shown in the following figure.
The Truth table of 4 to 2 encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as
A1=Y3+Y2A1=Y3+Y2
A0=Y3+Y1A0=Y3+Y1

We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.

Multiplexer is a combinational circuit that has maximum of 2 ndata inputs, „n‟ selection lines
and single output line. One of these data inputs will be connected to the output based on the
values of selection lines.
n
Since there are „n‟ selection lines, there will be 2 possible combinations of zeros and ones. So,
each combination will select only one data input.
4x1 Multiplexer:
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y.
The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs present
at these two selection lines. Truth table of 4x1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean functionfor output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I2Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I2

We can implement this Boolean function using Inverters, AND gates & OR gate.
The circuit diagram of 4x1 multiplexer is shown in the following figure.

De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It

n
has single input, „n‟ selection lines and maximum of 2 outputs. The input will be connected to
one of these outputs based on the values of selection lines.

Since there are „n‟ selection lines, there will be 2 n possible combinations of zeros and ones. So,
each combination can select only one output. De-Multiplexer is also called as De-Mux.

1x4 De-Multiplexer :
1x4 De-Multiplexer has one input I, two selection lines, s 1 & s0and four outputs Y3, Y2, Y1
&Y0. The block diagram of 1x4 De-Multiplexer is shown in the following figure.

The single input „I‟ will be connected to one of the four outputs, Y3 to Y0 based on the values
of selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.
Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output
as Y3=s1s0IY3=s1s0I
Y2=s1s0′IY2=s1s0′I
Y1=s1′s0IY1=s1′s0I
Y0=s1′s0′IY0=s1′s0′I

We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit
diagram of 1x4 De-Multiplexer is shown in the following figure.