Boolean Algebra

Sheis Abolmaali

School of ECE
Semnan University
1
 Algebra
• A deductive mathematical system
1. set of elements
2. set of operators
3. Number of unproved axioms (postulates)
• Set of elements
– a set with countable number of elements
– S = {a, b, c, d}
– x  S, and y  S
• Operators
– binary operators: x, y  S  z  S
– unary operators: x  S  z  S
2
 Axioms of Algebra 1/2
1. Closure:
• A set is closed w.r.t. a binary operation *
• Is the set of natural numbers closed w.r.t. (+) (-)?
2. Associative law:
• (x * y) * z = x * (y * z) for all x, y, z  S
3. Commutative law:
• x*y=y*x for all x, y  S
4. Identity element:
• S is said to have an identity element “e” if  x  S,
e * x = x * e = x.
• Set of integers: e = ? w.r.t.  and e = ? w.r.t. +
3
 Axioms of Algebra 2/2
5. Inverse
• S having an identity element “e” w.r.t. * is said to have
an inverse  x  S, whenever there exists an element
y  S such that
x*y=e
• Example: set of integers
6. Distributive law
• If * and  are two binary operators on S, * is said to
be distributive over  whenever
• x * (y  z) = (x * y)  (x * z)

4
 Boolean Algebra 1/2
• A set of elements B
– There exist at least two elements x, y  B s. t. x  y
• Binary operators: + and ·
– closure w.r.t. both + and ·
– additive identity ?
– multiplicative identity ?
– commutative w.r.t. both + and ·
– Associative w.r.t. both + and ·
• Distributive law:
– · is distributive over + ?
– + is distributive over · ?
– We do not have both in ordinary algebra 5
 Boolean Algebra 2/2
• Complement
–  x  B, there exist an element x’  B 
a. x + x’ = ? and
b. x · x’ = ?
– Not available in ordinary algebra
• Differences btw ordinary and Boolean algebra
– Ordinary algebra with real numbers
– Boolean algebra with elements of set B
– Complement
– Distributive law
– Do not substitute laws from one to another where
they are not applicable
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 Two-Valued Boolean Algebra 1/3
• To define a Boolean algebra
– The set B
– Rules for two binary operations
– The elements of B and rules should conform to our
axioms
• Two-valued Boolean algebra
– B = {0, 1}
x y x · y x y x + y x x’
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
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 Two-Valued Boolean Algebra 2/3
• Check the axioms
– Two distinct elements, 0  1
– Closure, associative, commutative, identity elements
– Complement
• x + x ’ = 1 and x · x ’ = 0
– Distributive law
x y z yz x+(y·z) x + y x + z (x + y) · (x + z)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 8
 Two-Valued Boolean Algebra 3/3
• Two-valued Boolean algebra is actually equivalent
to the binary logic defined heuristically before
– Operations:
• ·  AND
• +  OR
• Complement  NOT
• Binary logic is application of Boolean algebra to
the gate-type circuits
– Two-valued Boolean algebra is developed in a formal
mathematical manner
– This formalism is necessary to develop theorems and
properties of Boolean algebra
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 Duality Principle
• An important principle
– every algebraic expression deducible from the axioms
of Boolean algebra remains valid if the operators and
identity elements are interchanged
• Example:
– x+x=x
– x+x = (identity element)
= (complement)
= (+ over ·)
= (complement)
– duality principle
x+x=x  ?
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 Duality Principle & Theorems
• Theorem a:
– x+1=1
– x+1 =
=
=
=
=1
• Theorem b: (using duality)
– ?

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 Absorption Theorem
a. x + xy = x

b. ?

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Involution & DeMorgan’s Theorems
• Involution Theorem:
– (x’)’ = x
– x + x’ = 1 and x · x’ = 0
– Complement of x’ is x
– Complement is unique
• DeMorgan’s Theorem:
a. (x + y)’ = x’ · y’
b. From duality ?

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Truth Tables for DeMorgan’s Theorem
– (x + y)’ = x’ · y ’ x y x+y (x+y)’ x · y (x · y)’
0 0
0 1
1 0
1 1

x’ y’ x’ · y ’ x’ + y’
1 1
1 0
0 1
0 0 14
 Operator Precedence
1. Parentheses
2. NOT
3. AND
4. OR
• Example:
– (x + y)’
– x’ · y’
– x + x · y’

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 Boolean Functions
• Consists of
– binary variables (normal or complement form)
– the constants, 0 and 1
– logic operation symbols, “+” and “·”
• Example:
– F1(x, y, z) = x + y’ z
– F2(x, y, z) = x’ y’ z + x’ y z + xy’
x y z F1 F2
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 0
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1 1 1 1 0
 Logic Circuit Diagram of F1
F1(x, y, z) = x + y’ z

x
y
x + y’ z
z
y’

y’z

Gate Implementation of F1 = x + y’ z

17
 Logic Circuit Diagram of F2
F2 = x’ y’ z + x’ y z + xy’

y
F2
z

– Algebraic manipulation
– F2 = x’ y’ z + x’ y z + xy’
=?

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Alternative Implementation of F2
F2 = x’ z + xy’
x

y
F2
z

F2 = x’ y’ z + x’ y z + xy’
x

y
F2
z
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 OTHER LOGIC OPERATORS - 1
• AND, OR, NOT are logic operators
– Boolean functions with two variables
– three of the 16 possible two-variable Boolean functions
x y F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1

x y F8 F9 F10 F11 F12 F13 F14 F15

0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 20
 OTHER LOGIC OPERATORS - 2
• Some of the Boolean functions with two variables
– Constant functions: F0 = 0 and F15 = 1
– AND function: F1 = xy
– OR function: F7 = x + y
– XOR function:
• F6 = x’ y + xy’ = x  y (x or y, but not both)
– XNOR (Equivalence) function:
• F9 = xy + x’ y’ = (x  y)’ (x equals y)
– NOR function:
• F8 = (x + y)’ = (x  y) (Not-OR)
– NAND function:
• F14 = (x y)’ = (x  y) (Not-AND)
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Logic Gate Symbols
NOT TRANSFER

AND XOR

OR XNOR

NAND

NOR

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 Universal Gates
• NAND and NOR gates are universal
• We know any Boolean function can be written in
terms of three logic operations:
– AND, OR, NOT
• In return, NAND gate can implement these three
logic gates by itself
– So can NOR gate
x y (xy)’ x’ y ’ (x’ y’ )’
0 0 1 1 1
0 1 1 1 0
1 0 1 0 1
1 1 0 0 0 23
 NAND Gate

x
y

24
 NOR Gate

x
y

25
 Designs with NAND gates
Example 1/2
• A function:
– F1 = x’ y + xy’

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 Example 2/2
– F2 = x’ y’ + xy’

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 Multiple Input Gates
• AND and OR operations:
– They are both commutative and associative
– No problem with extending the number of inputs
• NAND and NOR operations:
– they are both commutative but not associative
– Extending the number of inputs is not obvious
• Example: NAND gates
– ((xy)’z)’  (x(yz)’)’
– ((xy)’z)’ =?

– (x(yz)’)’ =?
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Nonassociativity of NOR operation

29
 Multiple Input Universal Gates
• To overcome this difficulty, we define multiple-
input NAND and NOR gates in slightly different
manner
x
Three input NAND gate: (x y z)’ y
(x y z)’
z

x
Three input OR gate:(x + y + z)’ y (x + y + z)’
z

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 Multiple Input Universal Gates
x x
y (x + y + z)’ y (xyz)’
z z

3-input NOR gate 3-input NAND gate

A
B
C
D F=
E

Cascaded NAND gates

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 XOR and XNOR Gates
• XOR and XNOR operations are both commutative
and associative.
• No problem manufacturing multiple input XOR and
XNOR gates
• However, they are more costly from hardware
point of view.
• Therefore, we usually have 2-input XOR and
XNOR gates
x
y xyz

z
32
3-input XOR Gates

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 Algebraic Manipulations
• Previous example:
– F(x, y, z) = x’ y’ z + x’ y z + x y’
= x’z + xy’
• The goal:
– The reduce the number of terms
– The reduce the number of literals in a term
– to simplify the circuit
• Examples:
– x (x’ + y) = xy
– x + x’ y = ?
– (x + y)(x + y’) = ?
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 Complement of a Function
• F’ is complement of F
– We can obtain F’, by interchanging of 0’s and 1’s in the
truth table
x y z F F’
0 0 0 0 F=?
0 0 1 0
0 1 0 1 F’ = ?
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0 35
 Generalizing Demorgan’s Theorem
• We can also utilize DeMorgan’s Theorem
– (x + y)’ = x’ y’
– (A + B + C)’
=
=
= = A’B’C’
• We can generalize DeMorgan’s Theorem
1. (x1 + x2 + … + xN )’ = x1’ · x2’ · … · xN’
2. (x1 · x2 · … · xN )’ = x1’ + x2’ + … + xN’

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Example: Complement of a Function
• Example:
– F1 = x’yz’ + x’y’z
– F1’ = (x’yz’ + x’y’z)’
=?
= (x + y’ + z)(x + y + z’)
– F2 = x(y’z’ + yz)
– F2’ = (x(y’z’ + yz))’
=?
= x’ + (y + z) (y’ + z’)
• Easy Way to Complement: take the dual of the
function and complement each literal
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 Canonical & Standard Forms
• Minterms
– A product term: all variables appear (either in its
normal, x, or its complement form, x’)
– How many different terms we can get with x and y?
• x’y’  00  m0
• x’y  01  m1
• xy’  10  m2
• xy  11  m3
– m0, m1, m2, m3 (minterms or AND terms, standard
product)
– n variables can be combined to form 2n minterms
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 Canonical & Standard Forms
• Maxterms (OR terms, standard sums)
– M0 = x + y  00
– M1 = x + y’  01
– M2 = x’ + y 10
– M3 = x’ + y’  11
• n variables can be combined to form 2n maxterms
• m0’ = M0
• m1’ = M1
• m2’ = M2
• m3’ = M3
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 Example
xyz mi Mi F
000 m0=x’y’z’ M0=x+y+z 0
001 m1=x’y’z M1=x+y+z’ 1
010 m2=x’yz’ M2=x+y’+z 1
011 m3=x’yz M3=x+y’+z’ 0
100 m4=xy’z’ M4=x’+y+z 0
101 m5=xy’z M5=x’+y+z’ 0
110 m6=xyz’ M6=x’+y’+z 1
111 m7=xyz M7=x’+y’+z’ 0

F(x, y, z) = x’y’z + x’yz’ + xyz’ =

F(x, y, z) = (x+y+z)(x+y’+z’)(x’+y+z)(x’+y+z’)(x’+y’+z’)
= 40
 Min- & Maxterms with n = 3

Minterms Maxterms
x y z term designation term designation
0 0 0 x’y’z’ m0 x+y+z M0
0 0 1 x’y’z m1 x + y + z’ M1
0 1 0 x’yz’ m2 x + y’ + z M2
0 1 1 x’yz m3 x + y’ + z’ M3
1 0 0 xy’z’ m4 x’ + y + z M4
1 0 1 xy’z m5 x’ + y + z’ M5
1 1 0 xyz’ m6 x’ + y’ + z M6
1 1 1 xyz m7 x’ + y’ + z’ M7
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Boolean Functions in Standard Form
x y z F1 F2
0 0 0 0 1
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
• F1(x, y, z) =
• F2(x, y, z) =
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 Important Properties
• Any Boolean function can be expressed as a sum
of minterms
• Any Boolean function can be expressed as a
product of maxterms
• Example:
– F’ =  (0, 2, 3, 5, 6)
= x’y’z’ + x’yz’ + x’yz + xy’z + xyz’
– How do we find the complement of F’?
– F = (x + y + z)(x + y’ + z)(x + y’ + z’)(x’ + y + z’)(x’ + y’ + z)
=
=
43
 Canonical Form
• If a Boolean function is expressed as a sum of
minterms or product of maxterms the function is
said to be in canonical form.
• Example: F = x + y’z  canonical form?
– No
– But we can put it in canonical form.

– F = x + y’z =  (7, 6, 5, 4, 1)
• Alternative way:
– Obtain the truth table first and then the canonical
44
term.
 Example: Product of Maxterms
• F = xy + x’z
– Use the distributive law + over ·
– F =?
=

=  (4, 5, 0, 2) 45
Conversion Between Canonical Forms
• Fact:
– The complement of a function (given in sum of
minterms) can be expressed as a sum of minterms
missing from the original function
• Example:
– F(x, y, z) =  (1, 4, 5, 6, 7)
– F’(x, y, z) =
– Now take the complement of F’ and make use of
DeMorgan’s theorem
– (F’ )’ = =
– F = M0 · M2 · M3 =  (0, 2, 3)

46
 General Rule for Conversion
• Important relation:
– mj’ = Mj.
– Mj’ = mj.
• The rule:
– Interchange symbols  and , and
– list those terms missing from the original form
• Example: F = xy + x’z

– F = (1, 3, 6, 7)  F = (?, ?, ?, ?)
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 Standard Forms
• Fact:
– Canonical forms are very seldom the ones with the
least number of literals
• Alternative representation:
– Standard form
• a term may contain any number of literals
– Two types
1. the sum of products
2. the product of sums
– Examples:
• F1 = y’ + xy + x’yz’
• F2 = x(y’ + z)(x’ + y + z’)
48
 Example: Standard Forms
• F1 = y’ + xy + x’yz’
• F2 = x(y’ + z)(x’ + y + z’)

49
 Nonstandard Forms
• Example:
– F3 = AB(C+D) + C(D + E)
– This hybrid form yields three-level implementation
A
B
C
D F3
D
E
C

– The standard form: F3 = ABC + ABD + CD + CE

A
B
C
A
B
D
C F3
D
C 50
E
 Positive & Negative Logic
• In digital circuits, we have two digital signal levels:
– H – (higher signal level; e.g. 3 ~ 5 V)
– L - (lower signal level; e.g. 0 ~ 1 V)
• There is no logic-1 or logic-0 at the circuit level
• We can do any assignment we wish
– For example:
• H  logic-1
• L  logic-0

51
 Signal Designation - 1

x y F
x digital
F L L L
y gate
L H H
H L H
H H H

• What kind of logic function does it implement?

52
 Signal Designation - 2

x y F
x
0 0 0 F
y
0 1 1
1 0 1 positive logic
1 1 1
polarity
indicator
x y F
1 1 1 x
F
1 0 0 y
0 1 0
0 0 0 negative logic
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Another Example

x y F
L L H
L H H
H L H
H H L

74LS00

54
 Integrated Circuits
• IC – silicon semiconductor crystal (“chip”) that
contains gates.
– gates are interconnected inside to implement a
“Boolean” function
– Chip is mounted in a ceramic or plastic container
– Inputs & outputs are connected to the external pins of
the IC.
– Many external pins (14 to hundreds)

55
 Levels of Integration
• SSI (small-scale integration):
– Up to 10 gates per chip
• MSI (medium-scale integration):
– From 10 to 1,000 gates per chip
• LSI (large-scale integration):
– thousands of gates per chip 904 million transistors
• VLSI (very large-scale integration):
– hundreds of thousands of gates per chip
• ULSI (ultra large-scale integration):
– Over a million gates per chip

56
 Digital Logic Families
• Circuit Technologies
– TTL  transistor-transistor logic
– ECL  Emitter-coupled logic
• fast
– MOS  metal-oxide semiconductor
• high density
– CMOS  Complementary MOS
• low power

57
 Parameters of Logic Gates - 1
• Fan-out
– load that the output of a gate drives

• If a, say NAND, gate drives four such inverters,

then the fan-out is equal to 4.0 standard loads.
58
 Parameters of Logic Gates - 2
• Fan-in
– number of inputs that a gate can have in a particular
logic family
– In principle, we can design a CMOS NAND or NOR gate
with a very large number of inputs
– In practice, however, we have some limits
– 4 for NOR gates
– 6 for NAND gates
• Power dissipation
– power consumed by the gate that must be available
from the power supply

59
Power Dissipation

Difference in
voltage level !

60
 Parameters of Logic Gates - 3
• Propagation delay:
– the time required for a change in value of a signal to
propagate from input to output.
logic-1
logic-0 logic-1
x logic-0
logic-1 F
y
tPHL tPLH

x time

F
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 Computer-Aided Design - 1
• CAD
– Design of digital systems with VLSI circuits containing
millions of transistors is not easy and cannot be done
manually.
• To develop & verify digital systems we need CAD
tools
– software programs that support computer-based
representation of digital circuits.
• Design process
– design entry
– …
– database that contains the photomask used to
fabricate the IC
62
 Computer-Aided Design - 2
• Different physical realizations
– ASIC (application specific integrated circuit)
– PLD
– FPGA
– Other reconfigurable devices
• For every piece of device we have an array of
software tools to facilitate
– design,
– simulating,
– testing,
– and even programming

63
Xilinx Foundation

64
 Schematic Editor
• Editing programs for creating and modifying
schematic diagrams on a computer screen
– schematic capturing or schematic entry
– you can drag-and-drop digital components from a list in
an internal library (gates, decoders, multiplexers,
registers, etc.)
– You can draw interconnect lines from one component to
another

65
Schematic Editor

66
 Hardware Description Languages
• HDL
– Verilog, VHDL
– resembles a programming language
– designed to describe digital circuits so that we can
develop and test digital circuits
module devre(x, y, A, B, C);
A e
g1 x input A, B, C;
B g3
output x, y;
C g2 y wire e;
nand g1(e, A, B);
not g2(y, C);
or g3(x, e, y);
endmodule 67