Semiconductor Devices and Models

 Resistor
 Capacitor
 Diode
 Bipolar Transistor
 MOSFET
 SPICE Model
 Appendix

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-1 郭泰豪, Analog IC Design, 2018
 Resistors
 Material V1 metal V2 metal

 Diffusion layers: e.g. n+, p+, well SiO2 SiO2

n+
 Conductors : e.g. polysilicon, … p-substrate

 Resistance calculation
 R=ρL/A=ρL/tW= R□L/W
 R□=ρ/t is sheet resistance

L Cross-section
 Resistivity W area, A

t L
Resistivity=ρ R
A

L
 Sheet resistance
W Sheet resistance
= R□
R 口L
R
W

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-2 郭泰豪, Analog IC Design, 2018
 Resistors (Cont.)
 Graphical calculations from sheet resistance

W R

W W W W
7 .5 R
1 1 1 1 1 1 1 ½

W W W W/2

.5
1 1

1 1
8 .1 R
R .55 1 .5 1 .55

 VC (voltage coefficient) and TC (temperature coefficient) of R (or C)

⇨ nonlinearity ⇨ THD

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-3 郭泰豪, Analog IC Design, 2018
 Capacitors
 Metal-or polysilicon-over-diffusion
V1 metal V2 metal
 C is voltage dependent
SiO2 SiO2 l
n +

p-

 Metal-Insulator-metal V1
 High linearity
metal n
metal n-1
V2
 Inter-metal and intra-metal
 Inter: different layer
V1
 Intra: same layer V2
metal n

Via
metal n-1
Via

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-4 郭泰豪, Analog IC Design, 2018
 Resister ratio-matching considerations
Resistor Contact
Metal

R1 w

R2 w

3L

R3
w

R4 w

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-5 郭泰豪, Analog IC Design, 2018
 Capacitor ratio-matching considerations

C1
C4
2X C3
7  17
L L
2
L
L
X L
2X
C2 L 5  17
L
2
2X

3L
3L L

X X

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-6 郭泰豪, Analog IC Design, 2018
 Diode
Acceptor ions Donor ions IO

Holes Electrons

IS
x VO
VT
p-type -Xp 0 Xn n-type

Depletion Region
V
2K S 0 ( 0  VR ) ND
I  I S( exp  1)
VT Xp  [ ]1/ 2
q NA (NA  ND )
kT 2K S 0 ( 0  VR )
where VT  Xn  [
NA
]1/ 2
q q ND (NA  ND )
IS  saturation current
K S  relative permitivity of silicon
 0  bulit  in potential
VR  reverse  bias voltage

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-7 郭泰豪, Analog IC Design, 2018
 Junction Capacitance
 For abrupt junction:
N A N D 1/ 2
Q   Q   [2qK S 0 ( 0  VR ) ]
NA  ND
dQ  qK S 0 N A N D 1/ 2 C j0
Cj  [ ] 
dVR 2( 0  VR ) N A  N D VR
1
0
qK S 0 N A N D 1/ 2
[ C j0  [ ] ]
2 0 N A  N D

 For graded junction

N A N D 1 m
Q   Q   [2qK S 0 ( 0  VR ) ]
(NA  ND )
dQ  N A N D 1 m 1 C j0
Cj   (1  m)[2qK S 0 ] 
dVR NA  ND ( 0  VR ) m (1  VR ) m
0
N A N D 1 m 1
[ C j0  (1  m)[2qK S 0 ] ]
NA  ND  0m
m depend on the doping profile
m ≈ 1/3 for a linearly graded junction

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-8 郭泰豪, Analog IC Design, 2018
 Diode Model
 DC Model ID
ID A
 For V < Vr (off)
+
 For V > Vr (on)
Rf
dI 1 VT VT IS
Rf  ( )   V
dV ISe VD / VT I D Vr VO
Vr
-

 Small Signal Model

 For forward-biased diode
VT
rd 
ID
T
Diffusion capacitance: C d  rd
rd Cd Cj
Junction capacitance: C j  2C j0

Normally, Cd>>Cj (Cd≈100Cj)

C j0 : Capacitance at 0-V bias
 T : Diode transit time
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-9 郭泰豪, Analog IC Design, 2018
 Bipolar Process
 Vertical and lateral transistor in a bipolar process
collector base emitter
base collector
emitter

n+ n+ n+ p p
p p+
n+ n p+
n
n n
n+ n+

vertical lateral
 Vertical PNP or NPN npn pnp
 high β transistor transistor

 Lateral PNP or NPN

 low β

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-10 郭泰豪, Analog IC Design, 2018
 BJT Model: Ebers-Moll model (DC Model)

αRIR αFIF NPN PNP

C C

E C IC IC
- -
IE IC VBC + VBC +
IF IR + +
B VCE B VCE
+ +
VBE VBE
VEB VCB IB - - IB - -
- -
IE IE
B
IB E E

  VBB VT   IS   VBC VT  

IC  I S e  1 - e  1
  α R  
-IS   VBB VT     VBC VT  
IE  e  1 -IS e  1
αR    

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-11 郭泰豪, Analog IC Design, 2018
 Small Signal BJT Model

Aluminum contacts
Emitter

n+ n+
P Base
P
P+
Isolation island
Collector n
p substrate

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-12 郭泰豪, Analog IC Design, 2018
 Small Signal BJT Model (Cont.)

Sub rμ

CBS
rb CBC RC
B C
+

rn CBE vbe gmvbe ro CCS

-

RE Sub

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-13 郭泰豪, Analog IC Design, 2018
 MOS Transistors
 MOS structure
NMOS CONDUCTOR symbol
GATE INSULATOR
DRAIN
GATE

SOURCE

n n
DRAIN SOURCE
P - DOPED
SUBSTRATE
SEMICONDUCTOR SUBSTRATE

PMOS CONDUCTOR symbol

GATE INSULATOR
GATE
DRAIN

SOURCE
DRAIN SOURCE
p p
SUBSTRATE
n - DOPED

SEMICONDUCTOR SUBSTRATE

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-14 郭泰豪, Analog IC Design, 2018
 MOS Transistors (Cont.)
Source Gate Drain
Vs Vgs
VD
Metal
-Enhancement NMOS Polysilicon
P Oxide
n-diffusion
Source Gate Drain
p-diffusion

-Depletion NMOS p-substrate

P n-depletion
substrate
Implant

-Enhancement PMOS -Depletion PMOS

Source Gate Drain Source Gate Drain

n n

Implant

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-15 郭泰豪, Analog IC Design, 2018
 MOS Transistor Symbol (Cont.)

nMOS nMOS pMOS

enhancement depletion enhancement

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-16 郭泰豪, Analog IC Design, 2018
 MOS Transistor Operation
 Example : nMOS
 Vgs > Vt, Vds = 0 (linear region)

gate
GND (0 V)
Vgs
vd
+++

( inversion layer)
0V Channel
( inversion layer)

 Vgs > Vt, Vds = Vgs-Vt

Vgs
GND (0 V)

0V

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-17 郭泰豪, Analog IC Design, 2018
 MOS Transistor Operation (Cont.)
 Example : nMOS
 Vgs > Vt, Vds > Vgs-Vt (saturation region)
GND (0 V)

0V
Pinch off, Xd

 I-V characteristic of nMOS Vgs- Vt = Vds

LINEAR
REGION SATURATION
REGION
Vgs4

Ids Vgs3

Vgs2
Vgs1

Vds
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-18 郭泰豪, Analog IC Design, 2018
 Large Signal Behavior of MOSFETs
 Threshold voltage
Vt  Vt 0 
2 qε SiO2 N A
C ox
 2 f  VSB - 2 f 
 Vt 0    2 f  VSB - 2 f 
2 qε SiO2 N A k ox ε 0 ε
where γ  and C OX   ox
C ox t ox t ox
 Large-Signal I-V
C ox W
I DS  VGS  Vt 2  kW VGS  Vt 2
2L 2L
If depletion-layer width Xd is considered Leff = L-Xd
I DS 
kW
VGS  Vt 2
2L eff

 Channel length modulation

I DS I dx
  2 VGS  Vt 
kW 2 dL eff
 DS d
VDS 2L eff dVDS L eff dVDS
1
Let  I DS   r  1  VA    1  1  dx d 
 V     I DS  kW VGS  Vt 2 1  VDS 
I DS I DS
o
 DS  VA L eff  dVDS  2L
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-19 郭泰豪, Analog IC Design, 2018
 Small Signal Model of MOSFETs in Saturation
 Equivalent circuit model

C gd
G D
+
v gs g mvgs g mb vbs rds
C gs
-
-
vbs Csb
S
+
C gb C db

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-20 郭泰豪, Analog IC Design, 2018
Small Signal Model of MOSFETs in Saturation (Cont.)
 gm 
I DS
 k ' VGS  Vt   2k I DS
W W VDS  1
VGS L L

 g mb 
I DS
k
W
VGS  Vt  Vt  g m Vt


 Vto   2f  VSB  2f




VBS L VBS VBS V BS 2 2f  VBS

-1
 I  L dX d -1 1 V
 ro   DS   eff ( )   A
 VDS  I DS dVDS λI DS I DS

Csb0
 Csb  1
 VSB  2
1  
 0 
Cdb 0
 Cdb 
 VDS 
1
2  Derivation of C gs
1  
 0   Total charge stored in the channel QT
Q T 2
 C gs   WLCOX
VGS 3
L
Q T  WCox  [VGS - V(y) - Vt ]dy 
W 2 C ox
2
μ
VGS - V - Vt 2 dV
0 ID
W
K (VGS - V t )
WLCox VGS  Vt 
2
g 1 L 
ft  m  3
2πCgs 2 2
WLCox
3 Q T 2
C gs   WLCox
3 VGS 3
t  2f t  VGS  Vt 
2L2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-21 郭泰豪, Analog IC Design, 2018
 Example—Small Signal Model
 Derive the complete small-signal model for an NMOS transistor with
IDS=100μA, VSB=0.15V, VDS=0.6V. Device parameters are 2  f = 0.65,
W=2.5 μm, L=45 nm, γ= 0.45V1/2, μnCox = 280μA/V2 , λ = 2.22V-1, tox =
1.2 nm, Ψ0 = 0.69 V, Csb0 = Cdb0 = 1.125 fF. Overlap capacitance from
gate to source and gate to drain is 1.25 fF. Assume Cgb =5fF.

W 2.5 A
g m = 2μ n C ox I D = 2 × 280× 10 6 × × 100× 10 6
= 1.76 mA
L 0.045 V V

W 2.5
 n C ox ID 8       
g mb  L  .5 .045 A  443A
 f  VSB    .  . V V

 
ro   
 .k
I D .    

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-22 郭泰豪, Analog IC Design, 2018
 Example—Small Signal Model (Cont.)
C sb 1.125
 With VSB=0.15V,we find C sb  / 
 / 
fF  1fF
 VSB   . 
     
    . 

 The voltage from drain to body is VDB  VDS  VSB  0.75V

C db  1.125
Hence , C db  / 
 / 
fF  1.85fF
 VDB   . 
     
    . 

 The oxide capacitance per unit area is

 r  SiO .  .    F
C ox   cm  28.7 fF
t ox 1.2   m 9
m 
 The intrinsic portion of the gate source capacitance is

C gs   2.5  .045  28.7fF  2.15fF


Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-23 郭泰豪, Analog IC Design, 2018
 Example—Small Signal Model (Cont.)
 The addition of overlap capacitance gives Cgs = 2.4 fF

 Gate-drain capacitance is overlap capacitance Cgd = 1.25 fF

 The complete small-signal equivalent circuit is shown below

G D
+ 1fF
v gs .76    v gs 44   v bs 22.2k
11fF
-
-
vbs 1fF
S
+

5fF 1.85fF
B
 The fT of the device can be calculated with Cgb = 5fF giving
 gm  .76  
fT    Hz  32.2GHz
 C gs  C gd  C gb  2.45  .25     

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-24 郭泰豪, Analog IC Design, 2018
 Subthreshold Conduction in MOSFETs
W
VGS

nVt 
 VDS
nVt 

I DS  k x exp 1 - exp 
L  
wh ere k x depends on process parameters
n  1.5

I DS ( A)

0.5
0.4

0.3
VDS = 5V
0.2 W = 20 μ m
L = 20μm
0.1
VGS (V )
0.1 0.2 0.3 0.4 0.5

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-25 郭泰豪, Analog IC Design, 2018
 Subthreshold Conduction in MOSFET (cont.)
 Plotted on linear scales as I DS versus VGS ,showing the square-law
characteristic.

I DS (A )1/ 2

20

15
VDS = 5V
10 W = 20 μm
L = 20μm
5

VGS (V )
1 2 3 4 5

Extrapolated Vt = 0.7V

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-26 郭泰豪, Analog IC Design, 2018
 Subthreshold Conduction in MOSFET (cont.)
 Plotted on log-linear scales showing the exponential characteristic in the
subthreshold region.

I DS (A)
Square-law region
10-4

VDS = 5V
10-7
W = 20 μ m
L = 20μm
10-10
Subthreshold exponential region
VGS (V )
0.1 0.2 0.3 0.4

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-27 郭泰豪, Analog IC Design, 2018
 Mobility Degradation
 Large lateral electric fields accelerate carriers up to a maximum velocity
 Larger vertical electric fields  effective channel depth ↓  collisions ↑
 These effects can be modeled by an effective carrier mobility
n
 n ,eff 
[1  ( Veff ) m ]1/ m
1 W 2 1 1 W 
ID   n C ox Veff ( ) ID   n C ox Veff
2 L [1  ( Veff ) m ]1/ m 2 L , 2
This effect can also expressed as
where θ and m are device parameters
α-law model from curve-fitting

ID (A) Without mobility degradation

Source Gate Drain

With mobility degradation

n+ Lateral Electric Field n+

p-substrate
VDS (V)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-28 郭泰豪, Analog IC Design, 2018
 Substrate Current Flow in MOSFETs

 k2 
I DB  k1(VDS - VDSsat )IDS exp- 
 (VDS - VDSsat ) 

where k1 and k 2 are process-dependent parameters and VDSsat is the

value of VDS where the drain characteristics enter the saturation region

I DB I DB
  k2
 
g db
VDB VDS - VDSsat
2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-29 郭泰豪, Analog IC Design, 2018
 Example (1/2)
 Calculate rdb  1/gdb for VDS  2 V and 4 V, and compare with the
device ro .
Assume IDS = 100μA, λ = 0.45 V-1, VDS(sat) = 0.3 V, K1 = 5 V-1, and
K2 = 30 V.

For VDS = 2 V, we have

 30 
I DB  5  1.7  100 106  exp    1.8  1011 A
 1.7 
30 1.8 1011 10 A
g db   1.9  10
1.7 2 V

and thus
1
rdb   5.3 109   5.3 G
g db

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-30 郭泰豪, Analog IC Design, 2018
 Example (2/2)
This result is negligibly large compared with
 
ro   
 2.2 k
λI D .4    
However, for VDS  4 V
 30 
I DB  5  3.7  100 106  exp -   5.6  107 A
 3.7 
The substrate leakage current is now about 0.5% of the drain current.
We find
30  5.6 107 6 A
g db   1.2  10
3.7 2 V
and thus
1
rdb   8.33  105 Ω  833 kΩ
g db
This parasitic resistor is now comparable to ro and can have a
dominant effect on high-output-impedance MOS current mirrors.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-31 郭泰豪, Analog IC Design, 2018
 Summary of MOSFET Parameters
 Large-Signal Operation
Quantity Formula
μCox W
Drain current (saturation region) I ds  (Vgs - Vt ) 2
2 L

μCox W
I ds 
2
Drain current (triode region) [2(Vgs - Vt )Vds - Vds ]
2 L

Threshold voltage Vt  Vt 0  γ[ 2φ f - Vsb - 2φ f ]

1
Threshold voltage parameter γ 2 q N A
C ox

ε ox ο

Oxide capacitance C ox   3.45 fF m for t ox  100 A

2

t ox

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-32 郭泰豪, Analog IC Design, 2018
 Summary of MOSFET Parameters
 Large-Signal Operation
Quantity Formula
W W
Top-gate transconductance g m  μCox (VGS - Vt )  2I DSCox
L L

gm 2
Transconductance-to-current ratio 
I DS VGS - Vt

γ
Body-effect transconductance g mb  g m  χg m
2 2φ f  VSB

1 1 dX d
Channel-length modulation parameter λ 
VA Veff dVDS

1
1 L  dX d 
Output resistance ro   eff  
λI DS I DS  DS 
dV

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-33 郭泰豪, Analog IC Design, 2018
 Summary of MOSFET Parameters

Quantity Formula

Effective channel length L eff  L drwn - 2Ld - X d

1 2 2VA
Maximum gain g m ro  
λ VGS - Vt VGS - Vt

Csb0
Source-body depletion capacitance Csb  0.5
 VSB 
1  
 ψ 0 

Cdb0
Drain-body depletion capacitance Cdb  0.5
 VDB 
1  
 ψ 0 

2
Gate-source capacitance C gs  WLCox
3
gm
Transition frequency fT 
2πCgs  Cgd  Cgb 
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-34 郭泰豪, Analog IC Design, 2018
 SPICE MOSFET Model Parameters of A Typical
NMOS Process (MOSIS)
Parameter
(Level 2 model) Enhancement Depletion Units

VTO 1.14 -3.79 V

KP 37.3 32.8 μA/V 2
1
GAMMA 0.629 0.372 V 2
PHI 0.6 0.6 V
LAMBDA 3.1E-2 1.00E-6 V 1
CGSO 1.60E-4 1.60E-4 fF/ width
CGDO 1.60E-4 1.60E-4 fF/ width
CGBO 1.70E-4 1.70E-4 fF/ width
RSH 25.4 25.4 Ω/
CJ 1.1E-4 1.1E-4 pF/μ2
MJ 0.5 0.5
CJSW 5.0E-4 5.0E-4 pF/μ2 perimeter
MJSW 0.33 0.33 
TOX 544 544 

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-35 郭泰豪, Analog IC Design, 2018
 SPICE MOSFET Model Parameters of A Typical
NMOS Process (MOSIS) (Cont.)
(Level 2 model) Enhancement Depletion Units

NSUB 2.09E15 1.0E16 1/cm23

NSS 0 0 1/cm
NFS 1.90E12 4.3E12 1/cm2
TPG 1 1
XJ 1.31 0.6
LD 0.826 1.016 
UO 300 900 
UCRIT 1.0E6 0.805E6 cm2 /(v  s)
UEXP 1.001E-3 1.001E-3 V/cm
VMAX 1.0E5 6.75E5 m/s
NEFF 1.001E-2 1.001E-2
DELTA 1.16 2.80
 The SPICE parameters: Empirical parameters
 Fitting measured device characteristics to the mathematical equations
 Using a numerical optimization algorithm
 This approach gives good fit to the model but causes a deviation from the typical
parameters.
 Parameter relationships may not be self-consistent with some of the fundamental
relationships.
*Please refer to the chapters about SPICE model in the HSPICE document suggested in assignment 1
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 2-36 郭泰豪, Analog IC Design, 2018
 Appendix
 Resistance Estimation

 Capacitance Estimation

 Inductance Estimation

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-1

2-37 郭泰豪, Analog IC Design, 2018
 Resistance Estimation
 Sheet Resistance
 R=ρL/A=ρL/tW= R□L/W
 R□=ρ/t

 : resistivity W
t : thickness t
L : conductor length L
W : conductor width Current
R□ : sheet resistanceohm/square, / □ 

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-2

2-38 郭泰豪, Analog IC Design, 2018
 Resistance Estimation (cont.)
 Typical sheet resistance for conductors

Material Min. Typical Max.

Intermatal
0.05 0.07 0.1
(metal1-metal2)

Top-metal(metal3) 0.03 0.04 0.05

Polysilicon 15 20 30

Silicide 2 3 6

Diffusion(n+, p+) 10 25 100

Silicided diffusion 2 4 10

N-well 1K 2K 5K

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-3

2-39 郭泰豪, Analog IC Design, 2018
 Resistance Estimation of Nonrectangular Shapes
 Direct estimation Shape Ratio Resistance
W
Current
L R = L/W
A 1 1
L A 5 5
R = L/W W1
W1 B 5 5
W
Current 4L
2L B 1 2.5
R = L
R = L
L + 4W 1
L + 2W 2
B 2 2.55
W2
W2 B 3 2.66
 Table-assisted estimation C 1.5 2.1
C 2 2.25
RATIO =
L
RATIO =
W1
W2 W2 RATIO =
W1 C 3 2.5
W

L
W1 W2 W2
C 4 2.65
W1 W1
W W2 W2 W1 D 1 2.2
A B C
D 1.5 2.3
D 2 2.3
W2
W2
RATIO =
W2 D 3 2.6
W1

RATIO =
W2
W1
W2
W1
E 1.5 1.45
W1 W1 W1
D
E 2 1.8
E
E 3 2.3
E 4 2.65
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-4
2-40 郭泰豪, Analog IC Design, 2018
 Contact and Via Resistance
 Proportional to the area of the contact
 e.g. feature size↓ =>Rcontact↑

 0.25Ω ~ a few tens of Ωs

 Multiple contacts to obtain low-resistance interlayer connections

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-5

2-41 郭泰豪, Analog IC Design, 2018
 MOS-Capacitor Characteristics
 C-V plot
accumulation depletion inversion

1.0
Three regions in the plot
low frequency
(i)Accumulation region
(ii)Depletion region
high frequency
Cmin (iii)Inversion region

0 Vt
Vgs

 Accumulation region gate Vg< 0

ε SiO2 ε o gate
Co  A  C ox  A
t ox
- - - - - - - - - - - - - - -t
C o : gate capacitance Co ox
+ + +
ε SiO2 : dielectricconstant of SiO 2 ( 3.9) + + + + + + + +

ε o : permittivity of free space + +

A : gate area + p-substrate +

ε SiO2 ε o
C ox  : gate capacitance per unit area
t ox
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-6
2-42 郭泰豪, Analog IC Design, 2018
 MOS-Capacitor Characteristics (cont.)
 Depletion region
ε Siε o gate Vth > Vg > 0
C dep  A  C ox gate
d
d : depletion layer depth
Co tox
ε Si : dielectricconstant of Si ( 12)
Cdep depletion layer d
C o C dep
C gb  : gate capacitance per unit area +
+ +
+
C o  C dep +
+ p-substrate +
Where C o is low frequency capacitance
between gate and surface

 Inversion region


Co : static (i.e. low frequency, 100Hz)
gate gate Vg > Vth
C gb  Co Cdep
 Cmin : dynamic (i.e. high frequency)
Co  Cdep
C min Co ++++++++++++++
tox
---- - --
 Cdep depends on the depth of the depletoin region, Cdep channel- - -
depletion layer
d
i.e. depends on substrate doping density. +
+

O + p-substrate +
 For t ox  100 ~ 200 A, C min /Co varies from 0.02 ~ 0.3
for substrate doping density varies from110-14 cm-3 to 5 10-15 cm-3
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-7
2-43 郭泰豪, Analog IC Design, 2018
 MOS Device Capacitance
 Cross section of MOS device
GATE

Cgs Cgb Cgd

tox

SOURCE CHANNEL DRAIN

DEPLETION LAYER
Csb Cdb

SUBSTRATE
 Equivalent circuit
d

Cgd Cdb

GATE DRAIN
g SUBSTRAT
SOURCE bE
Cgs Csb
s

Cgb

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-8

2-44 郭泰豪, Analog IC Design, 2018
 MOS Device Capacitance (cont.)
 Approximation of gate capacitance
Self-aligned process is assumed (i.e. overlap caps. are negligible)
Parameter off Non-saturated Saturated
Cgb A 0 0
tox
A 2A
Cgs
0 2tox 3tox
Cgd A 0(finite for short channel devices)
0 2tox
Cg=Cgb+Cgs+Cgd A A 2A 0.9 A (short channel)
tox tox 3tox tox

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-9

2-45 郭泰豪, Analog IC Design, 2018
 Cgs,Cgd and Cox
 Example 1: W=49.2 m, L=4.5 m (long channel)
 Cgs and Cgd

large L 1.0

＊ large Cg & small

Cgd (in saturation 0.8
4 5
region) 2
3
Vgs - Vt
Cgd 0.6 1 Cgs

Cg 0 Cgs , Cgd
CoxWL
(Cgd is due to 0.4 5
channel side 4
3
fringing fields
2
between 0.2
1
gate and drain.) Vgs - Vt Cgd
0.0
1 2 3 4 5
Vds (volts)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-10

2-46 郭泰豪, Analog IC Design, 2018
 Cgs,Cgd and Cox (cont.)
 Example 2: L=0.75 m (short channel)
 Cgs and Cgd

small L
0.8
＊ small Cg & small
Vgs - Vt
Cgd (in saturation Cgs

region) 0.6 1 2 3 4 5
Cgd Cgs , Cgd
CoxWL
 0.2
5
Cg 0.4 3
4
2
(Cgd is due to
channel side Vgs - Vt 1
0.2 Cgd
fringing fields
between
gate and drain.) 0.0
1 2 3 4 5
Vds (volts)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-11

2-47 郭泰豪, Analog IC Design, 2018
 Cox, gate capacitance per unit area
ε SiO2 ε o
 Cox = A ; where ε SiO2  3.9 and ε o  8.8541014
t ox
o
e.g. t ox  350 A  Cox  110-3 pF/μF 2  1fF/μf 2

 Unit transistor L
 It is the same width
as a metal-diffusion
W 4
contact
5
2
 Minimum-size transistor L

W 4

5
2
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-12
2-48 郭泰豪, Analog IC Design, 2018
 Diffusion Capacitance
 Area and periphery
Cd=Cja*(ab)+Cjp*(2a+2b)
Cja: junction capacitance per μm2 C jp
C ja
Cjp: periphery capacitance per μm poly
a: width of diffusion region Diffusion
b: length of diffusion region a Area

 Typical value (1μm n-well process) b

Cja: 2*10-4pf/μm2 (n+ diffusion)

5*10-4pf/μm2 (p+ diffusion)
Cjp: 4*10-4pf/μm2 (n+ diffusion)
4*10-4pf/μm2 (p+ diffusion)
 Voltage dependent Vj is junction voltage
Vb is built - in junction potential ~ 0.6V
m
 Vj 
C j Vj   C j0 1  
C j0 is zero bias capacitanc e
m  0.3graded junction  ~
 Vb 
0.5abrupt junction 
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-13
2-49 郭泰豪, Analog IC Design, 2018
 SPICE Modeling of MOS Capacitances
 SPICE
.
example
M1 4 3 5 0 NFET W  4U L  1U AS  15P AD  15P PS  11.5U PD  11.5U
.
.
.MODEL NFET NMOS
 TOX  100E - 8
 CGBO  200P CGSO  600P CGDO  600P
 CJ  200U CJSW  400P MJ  0.5 MJSW  0.3 PB  0.7
 .....
.
.
o
node4 - drain TOX  100 A Cgbo occours due to the polysilico n extesion
node3 - gate source area AS  15 m 2 
beyond the channel. 200  10 -12F/M 
node5 - source drain area AD  15 m 2 Cgso and Cgdo represent the gate - to - source/dra in
node0 - substrate source periphery PS  11.5 m capacitanc e due to overlap in the physical
channel width  4 m drain periphery PD  11.5 m  
structure of the transistor . 600  10 -12F/M
channel length  1m

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-14

2-50 郭泰豪, Analog IC Design, 2018
 SPICE Modeling of MOS Capacitances (cont.)
 Capacitance
gate capacitanc e
Cg(intrinsic)  W  L  COX  4  1 35  10  4 PF  0.014PF
Cg(extrinsic)  W  Cgs0   W  Cgd0   2L  Cgb0 
 
 4  6  10  4  4  6  10  4  2  1 2  10  4 PF
 0.0052PF
Cg(total)  Cg(intrinsic)  Cg(extrinsic)  0.02PF
source and drain capacitanc e
  VJ   
MJ
 VJ 
MJSW


C j  Area  C j  1   periphery  CJSW  1  
  PB       PB  
 
where
C j  the zero - bias capacitanc e per junction area
CJSW  the zero - bias capacitanc e per junction periphery
MJ  the grading coefficient of the junction bottom
MJSW  the grading coefficient of the junction sidewall
VJ  the junction potential
PB  the built - in voltage ~ 0.4 - 0.8volts 
Area  AS or AD, the area of the souce or drain
Periphery  PS or PD, the periphery of the source or drain
C j(drain)  0.0043PF VJ  2.5V is assumed 
C j(source)  0.0043PF VJ  2.5V is assumed 

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-15

2-51 郭泰豪, Analog IC Design, 2018
 Routing Capacitance
 Single wire capacitance
 Parallel-plate effect and fringing effect
Fringing field

W L

T
Insulator(Oxide)
H

Substrate

 Accurate capacitance evaluation : use computer

 Hand calculation : use simple model (less than 10% error)
Half cylinders

t
w h
Parallel plate

 w  w
0.25
t 
0.5

C  ε    0.77  1.06   1.06  

 h  h  h  
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-16
2-52 郭泰豪, Analog IC Design, 2018
 Routing Capacitance (cont.)
 Multiple conductor capacitances
 Three-layer example

layer3
c23 c22
layer2
c21
layer1

Capacitance calculation is very complex—refer to textbook

 Typical dielectric and conductor thicknesses
o o
Thin  oxide 200 A Metal1 6000 A
o o
Field  oxide 6000 A M1  M2 oxide 6000 A
o o
Polysilicon 3000 A Metal2 12000 A
o o
M1  poly  oxide 6000 A Passivatio n 20000 A

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-17

2-53 郭泰豪, Analog IC Design, 2018
 Distributed RC Effects
 Transmission line
conductor layer
l
isolation
layer
Substrate

 Delay time from one end to the other end

rc 2
t l
2
r : resistance per unit length
c : capacitance per unit length
l : length of the wire

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-18

2-54 郭泰豪, Analog IC Design, 2018
 Distributed RC Effects (cont.)
 Disadvantages of long wire:
 Long delay
 Reduction in sensitivity to noise

t0 t1 t2
t0 t1
t0 t2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-19

2-55 郭泰豪, Analog IC Design, 2018
 Distributed RC Effects (cont.)
 Method to improve disadvantages mentioned previously

g
2 2
rc  l  rc  l 
delay      g   
2 2 2 2
rcl2
  g
4
 rcl2 
If     g , delay time is reduced
 4 
 rcl2 
If     g , more buffers should be used
 2 
In actual design, if possible,
rcl2 2 g
 τ g  l 
2 rc

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-20

2-56 郭泰豪, Analog IC Design, 2018
 Distributed RC Effects (cont.)
 Transmission line effect is particularly severe in poly wire because of
the relatively high resistance of this layer. Gate poly layer is the worst
one because of its high capacitance to substrate.

 Strategies
 Use metal line : small r
 Use wider metal for signal distribution line
 (e.g. clock distribution line) : small r, a tiny bit large C

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-21

2-57 郭泰豪, Analog IC Design, 2018
 Inductance
 On-chip inductance are normally small.
 Bond-wire inductance is larger.
 Inductance of bonding wires and the pins on packages
  4h 
L ln  H/cm
2  d 
 : the magnetic permeabili ty of the wire
(typically 1.257  10 -8 H/cm)
h : the height above the ground plane
d : the diameter of the wire

 Inductance of on-chip wires

  8h w 
L ln   H/cm
2  w 4h 
w : conductor width
h : the height above the substrate

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP2-22

2-58 郭泰豪, Analog IC Design, 2018