IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO.

3, MARCH 2011 455

Using Launch-on-Capture for Testing Scan

Designs Containing Synchronous and
Asynchronous Clock Domains
Shianling Wu, Member, IEEE, Laung-Terng Wang, Fellow, IEEE, Xiaoqing Wen, Senior Member, IEEE,
Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Member, IEEE, Wen-Ben Jone, Senior Member, IEEE,
Michael S. Hsiao, Senior Member, IEEE, James Chien-Mo Li, Member, IEEE,
Jiun-Lang Huang, Member, IEEE, and Lizhen Yu, Member, IEEE

Abstract—This paper presents a hybrid automatic test pattern Index Terms—Aligned launch-on-capture, at-speed scan
generation (ATPG) technique using the staggered launch-on- testing, double-capture, hybrid launch-on-capture, launch-on-
capture (LOC) scheme followed by the one-hot LOC scheme capture, one-hot launch-on-capture, staggered launch-on-capture.
for testing delay faults in a scan design containing asynchronous
clock domains. Typically, the staggered scheme produces small
test sets but needs long ATPG runtime, whereas the one-hot I. Introduction
scheme takes short ATPG runtime but yields large test sets. The
CAN DESIGN is a design-for-testability (DFT) technique
proposed hybrid technique is intended to reduce test pattern
count with acceptable ATPG runtime for multi-million-gate scan
designs. In case the scan design contains multiple synchronous
S in which the storage elements in a sequential circuit
are converted into scan cells and then these scan cells are
clock domains, each group of synchronous clock domains is stitched together to form scan chains during scan testing [1]–
treated as a clock group and tested using a launch aligned or [5]. By reconfiguring all storage elements into scan cells, the
a capture aligned LOC scheme. By combining these schemes
together, we found the pattern counts for two large industrial
complexity of automatic test pattern generation (ATPG) for
designs were reduced by approximately 1.7X to 2.1X, while the sequential circuits is transformed to that of manageable ATPG
ATPG runtime was increased by 10% to 50%, when compared for combinational circuits. Since the late 1990s, scan design
to the one-hot clocking scheme alone. has become the most widely used DFT technique.
In recent years, with shrinking device geometry due to
Manuscript received September 11, 2009; revised September 7, 2010; advances in design and manufacturing technologies, circuits
accepted September 15, 2010. Date of current version February 11, 2011. This containing millions or tens of millions of logic gates have
work was supported in part by the National Science Foundation of America,
under Grant CCF-0541103, and by the Japan Society for the Promotions of become common. While the scan design technique has offered
Science Grant-in-Aid for Scientific Research (B) 22300017. This paper was many benefits, it is now becoming a bottleneck for such
recommended by Associate Editor F. Lombardi. large designs due to the associated explosive increase in
S. Wu is with SynTest Technologies, Inc., Princeton, NJ 08550 USA, and
also with the Department of Creative Informatics, Kyushu Institute of Tech- test data volume. To fully detect defects in manufactured
nology, Iizuka, Fukuoka 820-8502, Japan (e-mail: shianlingwu@syntest.com). chips, the amount of scan test data can easily overflow the
L.-T. Wang is with SynTest Technologies, Inc., Sunnyvale, CA 94086 USA, storage capacity of automatic test equipment (ATE). These all
and also with the Department of Electrical Engineering, National Taiwan
University, Taipei 106, Taiwan (e-mail: wang@syntest.com). contribute to an increase in test cost.
X. Wen is with the Department of Creative Informatics, Kyushu Traditionally, one of the most popular capture-clocking
Institute of Technology, Iizuka, Fukuoka 820-8502, Japan (e-mail: schemes is one-hot clocking, in which every clock domain
wen@cse.kyutech.ac.jp).
Z. Jiang is with the ATPG Research and Development Group, SynTest is tested one by one. This scheme, however, often only saves
Technologies, Inc., Sunnyvale, CA 94086 USA (e-mail: zjiang@syntest.com). ATPG runtime but results in much more test patterns than
L. Tan, Y. Zhang, and L. Yu are with SynTest Technologies, Inc., Shanghai expected. Another scheme is simultaneous clocking in which
201200, China (e-mail: ltan@syntest.com.cn; yzhang@syntest.com.cn;
lzyu@syntest.com.cn). all clock domains are tested in parallel as long as data
Y. Hu is with the Institute of Computing Technology, Chinese Academy of propagating across clock domains are marked with unknown
Sciences, Beijing 100190, China (e-mail: huyu@ict.ca.cn). (X) values whenever needed during ATPG. This scheme can
W.-B. Jone is with the Department of Electrical and Computer En-
gineering, University of Cincinnati, Cincinnati, OH 45221 USA (e-mail: result in small pattern count but may lead to significant fault
wjone@ececs.uc.edu). coverage loss caused by the Xs.
M. S. Hsiao is with the Department of Electrical and Computer Engineering, In this paper, we first propose two capture-clocking
Virginia Polytechnic Institute and State University, Blacksburg, VA 24061
USA (e-mail: mhsiao@vt.edu). schemes, namely aligned clocking and staggered clocking,
J. C.-M. Li and J.-L. Huang are with the Department of Electrical which can be used to remedy the problems found in one-hot
Engineering and the Graduate Institute of Electronics Engineering, Na- clocking and simultaneous clocking. For ease of explanation,
tional Taiwan University, Taipei 106, Taiwan (e-mail: cmli@cc.ee.ntu.edu.tw;
jlhuang@cc.ee.ntu.edu.tw). we consider only delay faults, such as transition and path-delay
Digital Object Identifier 10.1109/TCAD.2010.2092510 faults. Aligned clocking is mainly used for testing synchronous
0278-0070/$26.00

c 2011 IEEE
456 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 3, MARCH 2011

Fig. 2. One-hot LOC.

Fig. 3. Simultaneous LOC.

Fig. 1. Basic at-speed test schemes. (a) Launch-on-shift (a.k.a. skewed-

load). (b) Launch-on-capture (a.k.a. broad-side or double-capture). Unlike the LOS technique, which uses the last shift clock
pulse to launch a transition, LOC uses a capture clock pulse
to launch the transition. Fig. 1 shows the two basic at-speed
clock domains; whereas staggered clocking is for testing asyn- test schemes. Typically, testing a scan-based BIST design
chronous clock domains. Next, we propose to partition clock based on LOS for at-speed delay fault testing can achieve
domains into clock groups, each of which contains a group of higher fault coverage with a shorter test pattern count [8]–
synchronous clock domains or noninteracting asynchronous [14]. The problems are that LOS can cause unwanted over-
clock domains. Synchronous clock domains are a group of testing because more false paths may be exercised, and incur
clock domains whose frequencies have integer multiple rela- higher implementation costs because the scan enable signal
tions, e.g., 25, 50, and 100 MHz. Asynchronous clock domains SE must be operated at-speed for each clock domain. This
are a group of clock domains whose frequencies are totally is in sharp contrast to LOC in which only a slow-speed,
unrelated, e.g., 30, 48, and 100 MHz. By clock grouping, we global scan enable signal GSE for all clock domains is
can effectively reduce the number of clock controls during needed.
ATPG. We then analyze why using the staggered clocking
scheme alone achieves smaller pattern count but its ATPG A. One-Hot Launch-on-Capture
runtime could be much longer. Lastly, we demonstrate that Using the one-hot LOC approach, a launch clock pulse
using a hybrid scheme, which combines staggered clocking followed by a capture clock pulse are applied to only one
and one-hot clocking, we can reduce pattern counts by 1.7X to clock domain during each capture window, while all other
2.1X for two large industrial designs while the ATPG runtime clocks are held inactive. An example timing diagram is
is increased by 10% to 50%, when compared to the case of shown in Fig. 2. It applies two capture pulses (C1 -followed-
using the one-hot clocking scheme alone. by-C2 or C3 -followed-by-C4 ) at their respective clock do-
The rest of this paper is organized as follows. Section II mains’ frequencies (of period d1 or d2 ) to detect intra-
discusses two basic test timing control diagrams for detecting clock-domain delay faults, and uses a single, slow-speed
delay faults. Section III presents the proposed hybrid launch- GSE to drive both clock domains. Thus, this approach can
on-capture (LOC) schemes. Section IV discusses the hybrid be used for at-speed testing of intra-clock-domain delay
ATPG techniques. Section V shows results on two industrial faults. The major disadvantage of one-hot LOC is long test
designs, and Section VI concludes this paper. time.

B. Simultaneous Launch-on-Capture
II. Background The long test time problem of one-hot LOC can be resolved
There are two basic capture-clocking schemes for testing by using the simultaneous LOC scheme illustrated in Fig. 3.
multiple clock domains at-speed: 1) launch-on-capture (LOC), The simultaneous LOC scheme allows testing to be performed
and 2) launch-on-shift (LOS). LOC was referred to as broad- on all clock domains in parallel, which is quite helpful when
side in [6] or double-capture in [4]. LOS was referred to as clock domains do not interact with each other. For clock
skewed-load in [7]. Both schemes are helpful in detecting domains where data may propagate from one clock domain
structural faults and delay faults within each clock domain to the other, the values of source scan cells in the originating
(called intra-clock-domain faults) or across clock domains clock domains will have to be forced to Xs during ATPG
(called inter-clock-domain faults). Delay faults include tran- in order to avoid any pattern mismatch. This could cause
sition faults and path-delay faults. significant fault coverage loss.
WU et al.: USING LAUNCH-ON-CAPTURE FOR TESTING SCAN DESIGNS CONTAINING SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAINS 457

Fig. 5. Launch aligned LOC.

Fig. 4. Capture aligned LOC.
applicable for at-speed testing of intra-clock-domain and inter-
clock-domain delay faults in synchronous clock domains.
III. Proposed Test Timing Control
Consider the three clock domains, driven by CK1 , CK2 , and
This section proposes test timing control methods for CK3 , again. The eight arrows among the dashed line C and
capture-clocking. Techniques to improve fault coverage and the three capture pulses, C1 , C2 , and C3 , represent the intra-
reduce pattern count and ATPG runtime are discussed in clock-domain and inter-clock-domain delay faults detected by
Section IV. the corresponding clocks. Note that in order to detect the inter-
clock-domain delay faults from CK1 to CK3 a special capture
A. Aligned Launch-on-Capture for Synchronous Domains pulse C4 is required. As this method requires much more
The X-masking problem in simultaneous LOC can be mit- complex timing-control diagram, a clock suppression circuit
igated by using the proposed aligned LOC scheme for syn- similar to those proposed in [15]–[19] is needed to enable or
chronous clock domains, where the clock frequency in either disable the selected capture pulses. The dotted clock pulses
of two clock domains is an integer multiple of the other. The shown in the figure indicate the suppressed capture pulses.
aligned LOC scheme is effective in reducing the sequential The main advantages of both aligned LOC approaches are
depth of the capture clocks as opposed to the staggered scheme that: 1) all intra-clock-domain faults and inter-clock-domain
(to be described later) in the capture window. Hence, test faults can be detected, and 2) a single, slow-speed GSE is
time can become shorter. Also, the scheme can detect inter- used. Hence, both approaches can be used for true at-speed
clock-domain faults among all synchronous clock domains testing of synchronous clock domains. However, one major
simultaneously. drawback is that precise alignment of the capture pulses is
There are two possible ways to implement the aligned LOC still required.
scheme, namely, capture aligned LOC and launch aligned
LOC. Fig. 4 shows the timing of the capture aligned LOC B. Staggered Launch-on-Capture for Asynchronous Domains
scheme. The major advantage of this approach is that all intra- The staggered LOC scheme relaxes the capture alignment
clock-domain and inter-clock-domain faults can be tested. A requirement problem in the aligned LOC approaches [20],
Ci to C arrow in Fig. 4 represents a set of delay faults that [21]. A test timing control example is shown in Fig. 6. In this
can be detected by a pair of clocks. For example, there are figure, capture pulses C1 -followed-by-C2 and C3 -followed-by-
three arrows from C1 to C. The horizontal arrow from C1 C4 are applied in a sequential or staggered order in the capture
to C represents those intra-clock-domain delay faults within window to test all intra-clock-domain faults and inter-clock-
the clock domain CK1 . The other two arrows represent those domain structural faults in the two clock domains. A daisy-
inter-clock-domain delay faults from CK1 to CK2 and from chain clock-triggering or token-ring clock-enabling technique
CK1 to CK3 , respectively. The remaining six arrows can be similar to that described in [22] can be employed to generate
interpreted in the same manner. the ordered sequence of capture clock pulses.
Since the active edges (rising edges) of the three capture Although this figure only shows the case of C1 -followed-
pulses (see dashed line C) must be aligned precisely, the by-C2 occurring before C3 -followed-by-C4 , the reversed
circuit must contain one reference clock, and the frequency of order is also feasible. We will explain the selection of clock
all remaining test clocks must be derived from the reference order in the later section. The two capture pulses (C1 and
clock. In the example given here, CK1 is the reference clock C3 ) are used to launch transitions at the outputs of some
operating at the highest frequency, and CK2 and CK3 are scan cells, and the output responses to these transitions are
derived from CK1 and designed to operate at 1/2 and 1/4 the captured by the following two capture pulses (C2 and C4 ),
frequency of CK1 , respectively. Therefore, this approach is respectively. Both delays d2 and d4 are set according to the
only applicable for at-speed testing of intra-clock-domain and operating frequency of their respective clock domains. Since
inter-clock-domain delay faults in synchronous clock domains. d1 , d3 , and d5 do not affect the detection of delay faults,
A similar aligned LOC approach is shown in Fig. 5 that we can simply use a single, slow-speed GSE for driving all
aligns all first capture edges (i.e., the launch edges) rather than clock domains. Hence, this scheme can be used to test all
second capture edges. This approach is referred to as launch intra-clock-domain faults and inter-clock-domain structural
aligned LOC. Similar to capturing aligned LOC, it is also only faults in asynchronous clock domains.
458 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 3, MARCH 2011

Fig. 6. Staggered LOC.

When the logic crossing synchronous clock domains is

tested, d3 must satisfy the specified timing relation between
the two clock domains. However, there can be some delay Fig. 7. Clock grouping example.
fault coverage loss among clock domains if a fixed order of
capture clocks is used across all capture windows. This fault and fault simulation processes. Clock grouping is a process
coverage loss is mostly related to sequentially redundant faults used to analyze all data paths in the circuit in order to
that can be detected when one-hot clocking is employed. determine all independent or noninteracting clocks, which can
be grouped and applied simultaneously. Note that we can
IV. Hybrid ATPG Techniques still group two noninteracting asynchronous domains together
when the operating frequencies are different. The reason is
This section discusses the hybrid ATPG techniques that because an on-chip clock is typically used for controlling each
can be used to reduce pattern count with reasonable ATPG asynchronous clock domain.
runtime. First, clock grouping and clock ordering along with An example of the clock grouping process is shown in
clock specification are performed. Then, the proposed hybrid Fig. 7. This example shows the results of performing a circuit
staggered-followed-by-one-hot ATPG scheme, combining the analysis operation on a scan design to identify all clock domain
staggered LOC and one-hot LOC approaches, based on the interactions, where an arrow indicates a data transfer from
clock grouping results, is discussed. one clock domain to a different clock domain. As shown in
Fig. 7, the circuit in this example has seven clock domains,
A. Clock Grouping
CD1 –CD7 , and five crossing-clock-domain data paths, CCD1 –
The first step in reducing ATPG runtime of testing a scan CCD5 . From this example it can be seen that CD2 and CD3
design is to identify all asynchronous clock domains that are independent from each other, and hence their related clocks
do not interact with each other or run in a synchronous can be applied simultaneously during test of CK2 . Similarly,
manner. For data paths that originate and terminate at different clock domains CD4 through CD7 can also be applied simulta-
asynchronous clock domains, additional care must be taken in neously during test of CK3 . Therefore, in this example, three
terms of the way the clocks are applied, in order to guarantee grouped clocks instead of seven individual clocks can be used
the success of the capture operation. This is mainly due to the to test the circuit during the capture operation.
fact that the clock skew between different clock domains is
typically nondeterministic. A data path originating in one clock B. Clock Ordering
domain and terminating in another might result in erroneous Each clock group thus consists of a group of noninteracting
captured values when both clocks are pulsed simultaneously, asynchronous clock domains or a group of synchronous clock
and the clock skew between the two clocks is larger than domains running at frequencies of multiple integers. As each
the data path delay from the originating clock domain to the clock group varies in gate count (circuit size), the order of
terminating clock domain. In order to avoid the mismatch, the these clock groups plays an important role in the circuit’s fault
timing governing the relationship of such a data path shown coverage that can be obtained.
in the following equation must be observed: There are n! different ways to order n clock groups when
Clock-skew < Data-path-delay + Originating-Clock-to-Q staggered clocking is employed. Using the gate count of each
clock group as an ordering criterion, a common approach
delay.
is to place the clock groups either in descending order or
If the above relation does not hold, a mismatch may occur in ascending order. Although it is difficult to predict which
during the capture operation. In order to prevent this problem, of the n! clock orders would give the best result [23], [24],
clocks belonging to different clock domains can be applied one logical reasoning would be that the descending order can
sequentially (using the staggered clocking scheme), as opposed yield better results than the ascending order. In the staggered
to simultaneously, such that any clock skew which exists approach, the clock groups that receive their capture clock
between the clock domains can be ignored during the test pairs later are at a disadvantage due to higher sequential depth
generation process. It is also possible to apply only one during ATPG. This is because their generated patterns should
clock during each capture operation using the one-hot clocking traverse through a larger number of clock cycles to justify
scheme. However, almost all designs have noninteracting clock values through the storage elements of other clock groups
domains that can be applied simultaneously to reduce the that received their clock pairs earlier. Thus, larger sized clock
complexity and final pattern count of the pattern generation groups should receive their clock pairs earlier, so justification
WU et al.: USING LAUNCH-ON-CAPTURE FOR TESTING SCAN DESIGNS CONTAINING SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAINS 459

Because all of the above-mentioned clocking schemes can

cause fault coverage loss, large pattern count, or long ATPG
runtime, we propose a hybrid scheme below to reduce pattern
count with reasonable ATPG runtime while maintaining the
same fault coverage as the one-hot clocking scheme.

D. Staggered-Followed-by-One-Hot ATPG
The hybrid approach is to apply the staggered LOC scheme
in the first phase and the one-hot LOC scheme in the second
phase. During the first phase, all clock groups are specified in
a predetermined, sequential, or staggered order. ATPG is then
performed based on the given staggered order. In order to
reduce ATPG runtime, circuit expansion based on the ordered
sequences of clock groups is done on the scan design during
a preprocessing step. Since the staggered clocking scheme
specifically deploys physically disjoint capture clock pulses
from different clock domains (in our case, different clock
Fig. 8. Clock order when GCD1 is larger than GCD2 . (a) In descending
order. (b) In ascending order. groups), there is no need to insert Xs at the fanout branches
of each originating flip–flop in any originating clock domain.
Therefore, this staggered approach will not create unnecessary
can be done earlier, resulting in better fault coverage, pattern Xs, complicating response compaction in a compression de-
count, and ATPG runtime overall. sign. Since staggered clocking can cause the ATPG program
Assume the gate count of grouped clock domain GCD1 to mark hard-detected faults as untestable or undetected due
is larger than that of grouped clock domain GCD2 , to the ordered sequence of clock groups, the second phase
Fig. 8(a) and (b) shows the clock order of CK1 (controlling running one-hot ATPG is required to detect those missed
GCD1 ) and CK2 (controlling GCD2 ) in descending order and faults.
ascending order, respectively. During ATPG, fault coverage, pattern count, and ATPG
runtime are closely monitored in the program to determine the
C. Clock Specification timing to switch over from staggered ATPG to one-hot ATPG.
The identified ordered clock groups can now be used for The switch-over criteria of this two-phase capture-clocking
capture-clocking using the basic LOC schemes described scheme can be made more intelligent, e.g., by monitoring the
in the previous two sections. During ATPG, we specify the increment in fault coverage and runtime versus pattern count
clock pulses in the capture window according to the given or a percentage of faults already processed. All such rule sets
clock order. For instance, in Fig. 8(a), we can specify the two are used in the program to automatically determine a switch-
clocks and GSE as over point that achieves a balance between ATPG runtime and
pattern count.
%CK1 = “010100000”;
%CK2 = “000001010”;
V. Experimental Results
%GSE = “000000000.”
The proposed hybrid staggered-followed-by-one-hot LOC
Similarly, in Fig. 5, we can specify the clock order as scheme has been applied to many industrial designs. We
present two large designs in the range of 1–5 million primitives
%CK1 = “01010001000000”; to illustrate the effectiveness of the proposed scheme.
%CK2 = “01100110000000”;
%CK3 = “01111000011110”; A. Design Statistics
%GSE = “00000000000000.” Table I summarizes the statistics of the two designs. We
developed a program to identify all independent clock groups.
The idea on specifying the clocks in the above format is A clock group consists of the clocks that do not interact
to allow for the ATPG program to properly perform circuit with each other or control a group of synchronous clock
expansion (time-frame expansion) prior to ATPG, depending domains. This allows all clocks in the clock group to be
on whether some clocks may have overlapping or nonover- activated simultaneously during capture without suffering from
lapping clock pulses. For example, 10 rather than 14 time any clock skew issue. In the experiments, we then performed
frames will be expanded for the ATPG process of Fig. 5 shown ATPG based on the number of clock groups identified by the
above, so as not to have two or more consecutive clock phases program.
(columns), like “0100” or “0010.” This is particularly helpful As an LOC scheme is employed for testing scan designs
when an aligned LOC approach is used for testing synchronous and an internal PLL-triggered on-chip test clock is often
clock domains. used to control a clock domain, the proposed hybrid LOC
460 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 3, MARCH 2011

TABLE I TABLE IV
Design Statistics Hybrid Clocking Results on Two Industrial Designs

Design A Design B Fault Pattern ATPG

No. of primitives 1.1 M 4.7 M Circuit Coverage Count Runtime
No. of faults 3 109 012 8 879 940 Design 78.84% 1505 6:18:16
No. of flip–flops 102 K 281 K A + + +
5.40% 3192 7:05:58
No. of clock domains 33 8
(84.24%) (4697) (13:24:14)
No. of clock groups 5 8 (1.77X)
Design 76.34% 1792 08:04:52
TABLE II B + + +
Application Results on Design A 10.00% 16 857 39:09:43
(86.34%) (18 649) (47:14:35)
(2.10X)
One-Hot Staggered
Hard-detected faults 2 556 801 2 490 101 TABLE V
Fault coverage (%) 84.24% 80.09%
Results on Design A in Descending and Ascending Orders
Pattern count (one-hot/staggered) 8309 7705(1.08X)
ATPG runtime 9:09:06 21:20:40
Design A Fault Pattern ATPG
Coverage Count Runtime
TABLE III
In descending 78.84% 1505 6:18:16
Application Results on Design B order + + +
5.40% 3192 7:05:58
One-Hot Staggered (84.24%) (4697) (13:24:14)
(1.77X)
Hard-detected faults 7 667 136 7 063 030
In ascending 78.60% 1428 6:06:12
Fault coverage (%) 86.34% 82.93%
order + + +
Pattern count (one-hot/staggered) 39 099 12 401(3.15X) 5.64% 3522 7:45:33
ATPG runtime 41:45:53 66:19:39 (84.24%) (4950) (13:51:45)
(1.68X)

scheme presented here would not have any additional impact The ATPG runtime, on the other hand, was increased by
on design and its implementations. One only has to ensure that approximately 50%. On the contrary, for Design B, the pattern
in the staggered approach, enough delay is inserted between count using one-hot clocking alone given in Table III is 2.10
interacting clock domains so data can propagate from an (= 39099/18649) times the pattern count using the hybrid
originating domain to all receiving domains. approach given in Table IV. The ATPG runtime, on the other
The one-hot clocking and staggered clocking schemes were hand, was increased by approximately 10%.
first applied independently to the two industrial designs listed
in Table I. Only intra-clock-domain transition faults are con- C. Comparison
sidered. The computer used was a 64-bit based PC operating Table V shows the ATPG results using hybrid clocking
at 2.5 GHz under the Linux operating system. with the gate counts in the five clock groups processed in
descending and ascending orders for Design A. ATPG in
B. Results descending order means that a clock group with the largest
Tables II and III summarize the test application results. gate count is captured first. The result indicates that performing
We consider only transition faults existing between flip–flops ATPG based on the descending order of the gate counts of all
within each clock domain. The results show that one-hot clock groups yields smaller pattern count and ATPG runtime
clocking leads to shorter ATPG runtime and higher fault than on the ascending order. The reason was mainly due to
coverage but larger pattern count than staggered clocking. This reduced sequential depth, as explained in Section IV-B. By
is expected as staggered clocking can result in sequentially making larger sized clock groups receive their clock pairs
untestable faults. earlier, faults inside these clock groups would not have to
The results using the proposed hybrid clocking scheme justify through other smaller sized clock groups. This will lead
on Designs A and B are listed in Table IV. In our experi- to higher fault coverage, smaller pattern count, and shorter
ments, staggered clocking is automatically switched to one- ATPG runtime.
hot clocking after the switch-over criteria are met. The first
column shows the circuit name. In the next three columns, D. Summary
fault coverage, pattern count, and ATPG runtime are associated In summary, the applications results show that: 1) proper
with three numbers each. The first number is the result using clock grouping and clock ordering help reduce pattern count,
staggered clocking, the second using one-hot clocking, and the and 2) the proposed hybrid scheme on average can yield
third is the sum of the two steps. 1.7X to 2.1X reduction in pattern count as compared to using
For Design A, the pattern count using one-hot clocking the one-hot scheme alone. One-hot clocking, however, has
alone given in Table II is 1.77 (= 8309/4697) times the the benefit of shorter ATPG runtime. Hence, we recommend
pattern count using the hybrid approach given in Table IV. simply using one-hot ATPG at the early development stage
WU et al.: USING LAUNCH-ON-CAPTURE FOR TESTING SCAN DESIGNS CONTAINING SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAINS 461

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[15] G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan,
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together. The hybrid staggered-followed-by-one-hot scheme pp. 358–367.
[16] M. Beck, O. Barondeau, M. Kaibel, F. Poehl, X. Lin, and R. Press,
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and X. Wen, “Multiple-capture DFT system for detecting or locating
Acknowledgment crossing clock-domain faults during self-test or scan-test,” European
Patent 1 360 513, Apr. 2, 2008.
The authors are grateful to the anonymous referees for [22] L.-T. Wang, X. Wen, S. Wu, H. Furukawa, H.-J. Chao, B. Sheu, J.
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462 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 3, MARCH 2011

Shianling Wu (S’88–M’09) received the M.S. de- holds 23 U.S. patents and five Japanese patents in logic built-in self-test,
gree in computer science from Columbia University, test compression, and low-capture-power (LCP) test generation. His current
New York, NY. research interests include design, test, and diagnosis of integrated circuits.
She joined SynTest Technologies, Inc., Princeton, Dr. Wen is a member of the IEICE, IPSJ, and REAJ. He received the 2008
NJ, in 2003, and is currently the Vice President of IEICE-ISS Best Paper Award for LCP X-filling/test generation.
Engineering focusing on advanced very large scale
integration design-for-testability (DFT) research and
development. Prior to SynTest, she was with Bell Zhigang Jiang received the B.S. degree from
Laboratories, Madison, WI, for over 23 years. In the Department of Electrical Engineering, Tsinghua
2008, she was with the Department of Creative In- University, Beijing, China, in 1995, the M.S. degree
formatics at Kyushu Institute of Technology, Iizuka, from the Department of Electrical Engineering, San
Fukuoka, Japan, where she is now a Ph.D. candidate. She currently holds Jose State University, San Jose, CA, in 1997, and
five U.S. patents and has three pending U.S. patents. She has published over the Ph.D. degree from the Department of Electrical
15 DFT papers and contributed chapters to two DFT textbooks: VLSI Test Engineering, University of Southern California, Los
Principles and Architectures in 2006 and Electronic Design Automation in Angeles, in 2005.
2009. He currently manages the ATPG Research and De-
Ms. Wu has served as a Program Committee Member for the IEEE velopment Group, SynTest Technologies, Sunnyvale,
International Test Conference, the Asian Test Symposium, and the North CA. His current research interests include design for
Atlantic Test Workshop. She won numerous AT&T and Lucent Awards testability, built-in self-test, fault diagnosis, and design of high-performance
and received the Best Panel Award with her panelists in the 2005 IEEE computer-aided design tools.
International Test Conference. She was a member of SEMATECH, SRC,
GSRC, STARC-International, VSIA, and the IEEE1500 Standard Committee.
Lang Tan received the B.S. degree in computer
Laung-Terng Wang (M’87–SM’04–F’08) received science from Central South University, Changsha,
the B.S.E.E. and M.S.E.E. degrees from National China, in 2004, and the M.S. degree from the
Taiwan University, Taipei, Taiwan, in 1975 and Department of Computer Science, Shanghai Jiaotong
1977, respectively, and the M.S.E.E. and E.E.Ph.D. University, Shanghai, China, in 2007.
degrees under the Honors Cooperative Program from He is currently a Research and Development En-
Stanford University, Stanford, CA, in 1982 and gineer with SynTest Technologies, Inc., Shanghai.
1987, respectively. His current research interests include design for
He has been the Chairman and Chief Executive testability, test compression, low-power testing, and
Officer with SynTest Technologies, Inc., Sunnyvale, fault diagnosis.
CA, since January 1990, and a Visiting Professor
with the Department of Electrical Engineering and
the Graduate Institute of Electronics Engineering, National Taiwan University
since July 2009. Prior to founding SynTest in 1990, he held several positions Yu Zhang received the B.S. degree from the De-
in industry, including Intel, Santa Clara, CA, from 1980 to 1983, and partment of Computer Science, Anhui University,
Daisy Systems, Mountain View, CA, from 1983 to 1986, and was with the Hefei, China, in 2005, and the M.S. degree from
Department of Electrical Engineering, Stanford University, as a Research the Department of Computer Science, University of
Associate and Lecturer from 1987 to 1991. He currently holds 28 U.S. Science and Technology of China, Hefei, in 2008.
patents, 15 European patents, one Japanese patent, and one Chinese patent He is currently a Research and Development En-
in the areas of scan synthesis, test generation, at-speed scan testing, test gineer with the ATPG Group, SynTest Technologies,
compression, logic built-in self-test, and design for debug-and-diagnosis. The Inc., Shanghai, China. His primary research interests
design-for-testability technologies developed by him have been successfully include design for testability, fault modeling, test
implemented in thousands of application-specific integrated circuit designs generation, test compression, and low-power testing.
worldwide. He has also co-authored and co-edited three internationally used
DFT/EDA textbooks: VLSI Test Principles and Architectures in 2006, System-
on-Chip Test Architectures in 2007, and Electronic Design Automation in
2009. Yu Hu (M’06) received the B.S., M.S., and Ph.D.
Dr. Wang is a member of Sigma Xi. He received the 2007 Meritorious degrees, all in electrical engineering from the Uni-
Service Award from the IEEE Computer Society and was a co-recipient of versity of Electronic Science and Technology of
the 2008 IEICE Information and Systems Society Excellent Paper Award for China, Chengdu, China, in 1997, 1999, and 2003,
an excellent series of papers that appeared in the IEICE Transactions on respectively.
Information and Systems during a period of 5 years. He is a Golden Core She is currently an Associate Professor with the In-
Member of the IEEE Computer Society, and is a member of the 2010 IEEE stitute of Computing Technology, Chinese Academy
Computer Society Fellow Evaluation Committee. of Sciences, Beijing, China. Her current research
interests include reliable design, fault diagnosis, and
testing.
Xiaoqing Wen (S’89–M’93–SM’08) received the Dr. Hu is a member of ACM, IEICE, and CCF.
B.E. degree in computer science and technology
from Tsinghua University, Beijing, China, in 1986,
the M.E. degree in information engineering from Wen-Ben Jone (M’84–SM’02) was born in Taipei,
Hiroshima University, Hiroshima, Japan, in 1990, Taiwan. He received the B.S. degree in computer sci-
and the Ph.D. degree in applied physics from Osaka ence and the M.S. degree in computer engineering,
University, Osaka, Japan, in 1993. both from National Chiao-Tung University, Hsinchu,
From 1993 to 1997, he was an Assistant Professor Taiwan, in 1979 and 1981, respectively, and the
with Akita University, Akita, Japan. He was a Vis- Ph.D. degree in computer engineering and science
iting Researcher with the University of Wisconsin, from Case Western Reserve University, Cleveland,
Madison, from October 1995 to March 1996. He OH, in 1987.
joined SynTest Technologies, Inc., Sunnyvale, CA, in 1998, and served as In 1987, he joined the Department of Computer
its Chief Technology Officer until 2003. In 2004, he joined the Department Science, New Mexico Institute of Mining and Tech-
of Creative Informatics, Kyushu Institute of Technology, Iizuka, Fukuoka, nology, Socorro, where he was promoted as an
Japan, where he is currently a Professor. He co-authored and co-edited two Associate Professor in 1992. From 1993 to 2000, he was a Full Professor
books: VLSI Test Principles and Architectures: Design for Testability (San with the Department of Computer Engineering and Information Science,
Francisco, CA: Morgan Kaufmann, 2006) and Power-Aware Testing and Test National Chung-Cheng University, Chiayi, Taiwan. Since 2001, he has been
Strategies for Low Power Devices (New York: Springer, 2009). He currently an Associate Professor with the Department of Electrical and Computer
WU et al.: USING LAUNCH-ON-CAPTURE FOR TESTING SCAN DESIGNS CONTAINING SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAINS 463

Engineering, University of Cincinnati, Cincinnati, OH. He was a Visiting James Chien-Mo Li (S’93–M’02) received the
Scholar with the Institute of Information Science, Academia Sinica, Taipei, B.S.E.E. degree from National Taiwan University,
Taiwan, and with the Department of Computer Science and Engineering, Taipei, Taiwan, in 1993, and the M.S.E.E. and Ph.D.
Chinese University of Hong Kong, Shatin, Hong Kong. His current research degrees in electrical engineering from Stanford Uni-
interests include very large scale integration design for testability and reliabil- versity, Stanford, CA, in 1997 and 2002, respec-
ity, low-power circuit design and test, and computer architecture and parallel tively.
processing. He is currently an Associate Professor with the
Dr. Jone was a co-recipient of the 2003 IEEE Donald G. Fink Prize Paper Graduate Institute of Electronics Engineering, Na-
Award. He was also a co-recipient of the Best Paper Award of the 2008 tional Taiwan University. His current research in-
International Symposium on Low-Power Electronics and Design. terests include design for testability, built-in self-
testing, low-power testing, and fault diagnosis.

Michael S. Hsiao (S’95–M’97–SM’04) received

the B.S. degree in computer engineering (highest Jiun-Lang Huang (S’96–M’99) received the B.S.
honors), and the M.S. and Ph.D. degrees in elec- degree in electrical engineering from National
trical engineering from the University of Illinois Taiwan University, Taipei, Taiwan, in 1992, and the
at Urbana-Champaign, Urbana, in 1992, 1993, and M.S. and Ph.D. degrees in electrical and computer
1997, respectively. engineering from the University of California, Santa
He was a Visiting Scientist with NEC America, Barbara (UCSB), in 1995 and 1999, respectively.
Inc., Princeton, NJ, in 1997, and in 2002 he was a From 2000 to 2001, he was an Assistant Re-
Visiting Professor with Intel, Santa Clara, CA. He search Engineer with the ECE Department, UCSB.
was an Assistant Professor with the Department of In 2001, he joined National Taiwan University and is
Electrical and Computer Engineering, Rutgers, NJ, currently an Associate Professor with the Graduate
and the State University of New Jersey, Piscataway, between 1997 and 2001. Institute of Electronics Engineering and the Depart-
From 2001 to 2006, he was an Associate Professor with the Department ment of Electrical Engineering. His current research interests include design
of Electrical and Computer Engineering, Virginia Polytechnic Institute and for testability, built-in self-test, and calibration for mixed-signal systems.
State University, Blacksburg. Since 2006, he has been a Professor with the
same department. He and his research group have published more than 180
refereed journal and conference papers. His current research interests include Lizhen Yu (M’10) received the B.S. degree in com-
very large scale integration testing, design verification, diagnosis, and power puter science and applications and the M.S. degree
management. in nuclear technologies and applications, both from
Dr. Hsiao was a recipient of the Digital Equipment Corporation Fellowship, the University of Science and Technology of China,
the McDonnell Douglas Scholarship, the National Science Foundation CA- Hefei, China, in 2001 and 2005, respectively.
REER Award, and is recognized for most influential papers in the first 10 She is currently a Research and Development
years (1998–2007) of the Design Automation and Test Conference in Europe. Manager with Syntest Technologies, Inc., Shanghai,
He has served on the program committees for more than 40 IEEE international China. Her current research interests include design
conferences and workshops, in addition to serving as an Associate Editor on for testability, design methodology, simulation, and
ACM Transactions Design Automation of Electronic Systems, as well as on so on, for static random access memories and digital
editorial boards of several journals. logic. She has published three papers in these areas.