Test Pattern Verification: Tessent Scan & ATPG

This article introduces the Verify Test Pattern of Chapter 8 Test Pattern Generation
in UG.

Why do we need to do timing-based simulation? The significance is that we can

compare the differences between ATPG tools and simulator tools.

The difference in timing leads to different results.

Design Simulation with Timing.

First you need to write the pattern using the write_pattern cmd line. The default
mode is parallel, unless you specify to write serial with -serial. Because serial files are
very large, you can use the -sample switch to write a partial pattern. The tool will
save at least one pattern for each type.

In addition, you can also use the -start -end switch to reduce the file size, but such
interception is unreliable and not as reliable as -sample. In the end, you still have to
run the full pattern set.

If no error occurs in the simulator, the following message will be printed:

no error between simulated and excepted patterns

Parameter passing adopts + default Verilog testbench supports several Verilog

parameter passing:

 STARTPAT Set pattern number to start simulation.

 ENDPAT Set pattern number to end the simulation pattern number
 CHAINTEST causes the STARTPAT and ENDPAD parameters to be applied to the
chain test pattern instead of the scan test.
 END_AFTER_SETUP causes the simulation to simulate only the vectors in the
test_setup phase and then ends the simulation.
 SKIP_SETUP causes the testbench to skip simulating the test_setup vector and
start simulating the first pattern, chain or scan test.
 CONFIG specifies the .cfg file, which controls the .vec waveform file. For specific
usage, see CONFIG Usage
 NEWPATH The file path of the tb file. The default file name length is 512 bytes.

Example of parameter passing:

1. By default, CHAINTEST=0, which means that only the scan test pattern will be
simulated, unless you specify CHAINTEST=1.
2. If CHAINTEST=1 and ENDPAT is specified, it will start from the chaintest pattern,
but will not simulate the scan test pattern.
3. If CHAINTEST=1 and STARTAT is specified, it will also start simulation from the
specified STARTPAT chain test pattern and continue to all scan test patterns.

vsim <testbench_tp> -c -do “run -all” +STARTPAT=5 +ENDPAT=8

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STARTPAT,END PAT, and CHAINTEST Usage:

Parallel vs Serial Patterns.

Although parallel simulation is faster, it cannot locate some scan shift problems.
Therefore, it is recommended to run several serial patterns and then run parallel
patterns.

Potential causes of Simulation Mismatches

1. There are many reasons for simulation mismatch. The biggest difficulty is to
know where to start.
2. First, does the chain test fail?
3. Does the scan test serial/parallel pass?
4. DRC problem causes: C6 and T24 are the most likely to cause mismatch. You can
avoid C6 problems by using set_clock_off_simulation

Simulation mismatch investigation:

 Does the mismatch occur in PO, scan cell, or both? If
 the mismatch occurs in the scan cell, it is usually due to a capture problem or a
timing problem. However, if it occurs in the PO port, it is more likely that the
data loaded into the scan cell is incorrect. (I don’t understand???) Does
 the mismatch occur in part of the pattern or the entire pattern?
 If it is a partial patern, it can be cut separately. If it is the entire pattern, it is
generally a common problem.
 Does the mismatch occur in a few cells/pins or in most of the cells/pins? If it
occurs in a few cells/pins, it indicates a problem with a small number of
instances or logic. If it occurs in most of the cells/pins, it is more likely to be
some common problems.
 Does the chain test fail?
 To determine whether the serial pattern fails, the chain test simply shifts the
data from scanin to scanout. This is also the debugging method I will add later,
that is, to turn on the EDT bypass mode.

 Is it a specific pattern type that fails?

 If only the ram sequential pattern fails, then the problem may be with the ram
(incorrect model). If only the clock_sequential pattern fails, then the problem is
most likely related to the non-scan FF and latch.

Simulation data analysis

 Compare the simulator value with the ATPG tool value, and then debug.
 When the simulated value does not match the ATPG value, Verilog parallel tb
can report the time, pattern num, and scan cell or which PO is wrong. But for
serial tb, it will only report which PO is wrong and the time of the error, so it is
more difficult for serial to find out the incorrect value captured by the scan cell.
You need to trace back in both the ATPG tool and the simulator tool to find the
source of the mismatch.

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When you compare simulation data with ATPG tool data, it is very helpful to use the
SIM_VECTYPE_SIGNAL parameter file.
 When this keyword is used in the parameter file. tb will include additional
keywords to make it easier for you to understand and debug.

As shown in the figure, paying attention to these signals can help you debug
 mgcdft_shift,
 mgcdft_launch_capture
 _pattern_count

 From the figure, we can see that the mismatch occurs at the shift procedure
after pattern 6, that is, the mismatch occurs when shifting out pattern 6 (shifting
in pattern 7).
 At this point, if we want to see the data in the ATPG tool, you can use the time
of 1100ns in the figure.

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Demo2:
 It is recommended to use parallel testbench with a small number of serial shift
cycles. This allows you to catch shift and capture problems in a pattern.

 To apply serial post shift cycles, write out the patterns with the
“SIM_POST_SHIFT”.
For example, to define 5 post-shift cycles, use:

write_patterns <pat.v> -verilog -parameter_list {SIM_POST_SHIFT 5}

 When you use tb dump waveform, the following signals can help you:
 _procedure_string describes the shift/load_unload phase.
 _pattern_count pattern number. It should be noted that when pattern_count is
0, procedure_string is in the SHIFT phase. It means that the data is shifting out
for pattern 0 (shifting in for pattern 1), so it is important to remember that
pattern_count refers to the shift out phase
 _cycle_count cycle number
 _compare_fail comparison failure is 1
 _chain_test _Is it a chain test, 1 if it is, and 0 if it is a scan test

To view relevant data in ATPG, use

set_gate_report 0. 0 is the pattern index

report_scan_cell <mismatch_chain_name> <mismatch_cell_num> -display

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 As shown in the figure above, first tell the ATPG tool the chain name and which
cell has failed. After the ATPG tool locates that cell, set_gate_report pattern 0 is
used to specify the failed pattern.
 Then report_gates to see the expected value of SDFF.

My personal understanding of the meaning of D (100) above is that the ATPG tool
will treat it as a change within the cycle, rather than a complete alignment with the
clock. As shown in the figure below, I drew 010 below, which represents the D port.
First, 0 is the starting state, and then a change occurs. As for where the change
occurs, it cannot be extracted from the pattern because the pattern is not based on
the timing_base tool, but on the event tool. Finally, it changes again to 0 (i.e. the
final state).

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 So from the information D(100) above, we can see that in the current cycle, the
initial state of port D is 1, then at some point it changes to 0, and the final state
is 0.

1. Comparison At the beginning of capture, we first need to check that the scan cell
is loaded with the correct value. In this example, at the beginning of the capture
procedure, ff0/Q is 1. As shown in the figure above, both simulation and tessent
visualizer are 1 at the beginning of the capture phase. ff0/Q (111)
If this value is correct, it means that the scan cell is loaded with the correct value and
there is no problem in the shift phase.

2. Next, compare the capture phase. The clock is 010, SE (000) D (100). That is, the D
port changes from 1 at the beginning to 0, and finally remains at 0. Q captures 1, and
the output remains at 111.

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As shown in the figure above, we can see from the dump waveform that the clock
piulse is fine, SE is 0, and D changes from 1 to 0. The problem is that Q does not
capture the expected value 1, but 0 instead. That is to say, the clock does not step on
the correct value due to the hold problem. And becomes 100.

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