Scribd
Upload
17 views5 pages

S5 Honours - Internal2 - Keyscheme

FPGA based system design exam 2 key

Uploaded by

suma_hari6244
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
17 views5 pages

S5 Honours - Internal2 - Keyscheme

FPGA based system design exam 2 key

Uploaded by

suma_hari6244
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

ECT 393 Reg.

No _________________
Name _________________

RAJAGIRI SCHOOL OF ENGINEERING & TECHNOLOGY


KTU B.TECH DEGREE SECOND INTERNAL EXAMINATION, MARCH 2022
Fifth Semester
Honours
FPGA BASED SYSTEM DESIGN
Time: 2 Hour Max. Marks: 50
PART A
Answer all questions. Each question carries 5 marks
1. Write a short note on the look-up-table based logic cells in FPGA.

Explanation 3 marks
Diagram 2 marks

2. List the applications of FPGA.


o Application-Specific Integrated Circuits (ASICs) :
o Implementation of Random Logic : 3 applications 5
o Replacement of SSI Chips for Random Logic : marks
o Prototyping
3. Write a short note on the power dissipation in FPGAs. Each components :
• Static and Active power components 2.5marks each

4. What is the principle of segmented routing? Mention its advantages.


• In order to reduce the area overhead associated with using full-length
tracks for each net, we can use segmented tracks
• Instead of being full length, a track is divided into segments.

Principle 3 marks
Advantages 2 marks

1
• If a track in row 1 is segmented into two segments, one could use the
same track for one more net.
• For example, nets “x” and “z” can both be routed on row 1 in Figure
c). That is the principle of segmented track routing.
• More nets can be routed using the same number of tracks;
• However, when long nets are desired, intersegment switches must be
used to join the segments. These switches introduce more resistance
and capacitance into the net. However, the overall routing resource
area will reduce with segmented routing.

5. Briefly discuss the different routing resources present in Xilinx FPGAs.


a. Switch matrices
b. Wire segments : distinguished by their relative segment lengths
i. length-1 wires (Single-length lines)
Switch matrices 2 marks
ii. length-2 wires (Double-length lines) Wire segments 3 marks
iii. long wires
6. Explain the min-cut placement algorithm used in FPGAs.
• Partitioning algorithm
• The partitioning-based placement can be realized as recursively calling
the partitioning process by picking a region containing some circuit
modules, dividing the region into a set of subregions, and assigning each
module to one of the subregions to optimize some predefined metric
(e.g., wirelength and cut size).
o minimizing the number of cuts in the nets across the boundary
between two partitions
o placing highly-connected blocks in the same partition.
• These procedures are recursively repeated until the number of modules
in each region is smaller than a threshold

2
Explanation 5 marks

PART B
Each question carries 10 marks
7. Discuss the different architectural/topological options of FPGA.
a. Matrix-based (symmetrical array) architectures
b. Row-based architectures 2.5 marks each
c. Hierarchical PLD architectures
d. Sea-of-gates architecture
OR
8. What are the different configurations of FPGA based on granularity? Explain.
FPGA logic blocks differ greatly in their size and implementation capability.
• Granularity can be defined in various ways, for example, as the number of
Boolean functions that the logic block can implement, the number of
equivalent two-input NAND gates, the total number of transistors, total
normalized area, or the number of inputs and outputs.
o Fine grain
o Coarse grain

9. Why is the delay associated with placement and routing considered to be


significant with respect to the performance of FPGAs? How is it calculated?
Give two examples of the delay model.

3
Different parts of a circuit contribute to path delays : I/O pads, the logic
blocks and the interconnects.
Source and sink can be an I/O block or a logic block
For Xilinx FPGAs , I/O blocks and logic blocks have constant delays
I/O blocks : 15 ns, Combinational logic blocks : 8 ns
Routing delays vary quite a lot

4
OR
10. Explain the phases of Maze routing algorithm with an example.
• Maze routing models the routing surface as a grid.
• Each grid point can be a terminal of a desired connection (known as either the
source or target), a wire that connects adjacent grid points, or an obstacle that
represents space that is not available for interconnections.
• The grid is described by a two dimensional array which records the state of
each grid point
• The Lee algorithm for maze routing is popular because it is guaranteed to find
a shortest-path connection if one exists.
• This algorithm operates in three phases. During the expansion phase, the
algorithm searches outward from the source terminal while labeling each node
with its distance from the source.
• When the target is reached, the backtrace phase selects a path by following
decreasing label values and marks these as wires (which act as obstacles for
later routings).
• The cleanup phase erases unused expansion labels.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy