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DESCRIPTIVE QUESTIONS:
UNIT-I
Short Answer Questions-
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. Define Computer Architecture? L1:Remember CO2
2. Define a Digital Computer ? L1:Remember CO2
Draw block diagram of Computer.
3. What is the need of Register? L1:Understand CO3
Explain the different types of
Registers.
4. What is control memory? L1:Understand CO3
5. Define a Micro Program & Micro L1:Remember CO2
Instruction?
Long Answer Questions-
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. How to do address sequencing L2:Understand CO4
with diagram.
2. What is instruction format? L2:Understand CO3
Explain the different instruction
formats in detail.

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3. Explain the different phases of L2:Understand CO4

Instruction Cycle?
4. Explain the Micro Program L2:Understand CO4
Control with Diagram &
Examples?
5. List out any 5 Registers with L1:Remember CO5
explains in detail.
6. Demonstrate the Three – State L2:Understand CO3
Bus Buffer with neat diagram
7. List and Explain in detail about L1:Remember CO5
the memory reference
Instructions
8. Draw the flowchart for interrupt L3:Applying CO4
cycle and experiment with it with
explanation
9. Determine the input-outpu L5: Evaluating CO3
configuration
10. Explain the stored program L2:Understand CO3
organization with neat diagram
UNIT-2
Short Answer Questions
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. Define Data path. L1:Remember CO2
2. Define Latency and throughput L1:Remember CO2
3. Discuss the principle operation of L2:Understand CO1
micro programmed control unit.
4. What is control store? L2:Understand CO3
5. Define Processor clock. L1:Remember CO2
Long Answer Questions-
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. Draw and explain typical hardware L2:Understand CO4
control unit.
2. Draw and explain about micro L2:Understand CO4
program control unit.
3. Write short notes on L2:Understand CO1
(i)Micro instruction format (ii)
Symbolic micro instruction.
4. Explain multiple bus organization L2:Understand CO3

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in detail.
5. Explain in detail about conditional L2:Understand CO3
branching with neat diagram
6. Explain general register L2:Understand CO3
organization in detail with neat
diagrams
7. **Explain Stack organization in L2:Understand CO3
detail with neat diagrams
8. Evaluate the following program L5: Evaluate CO2
using three address Instruction
format
X = (A+B) * (C+D)
9. Evaluate the following program L5: Evaluate CO2
using two address Instruction
format
X = (A+B) * (C+D)
10. Evaluate the following program L5: Evaluate CO2
using one address Instruction
format
X = (A+B) * (C+D)
UNIT-3
Short Answer Questions-
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. Convert the following decimal L5: Evaluate CO4
number to the base indicated
a. 7562 to octal
b. 1938 to hexadecimal
2. Find the 1’s and 2’s complement of L1: Remember CO1
the following eight digit binary
number
a. 10101110
b. 10000001
3. List the steps of Booth’s L4:Analyze CO3
Multiplication algorithm
4. Convert the following decimal L5: Evaluate CO1
number to the base indicated
a. 17562 to octal
b. 11938 to hexadecimal
5. Briefly explain r’s complement with L2:Understand CO2
example

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Long Answer Questions-

S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. Draw and explain the hardware for L2:Understand CO3
signed – magnitude addition and
subtraction.
2. Explain the booth’s multiplication L6:Design CO4
algorithm with neat sketch of
hardware design
3. Perform division of 1000 and 0011 L5:Evaluate CO2
using restoring division algorithm.
4. Multiply 7 and 3 using Booth’s L4:Analyse CO1
algorithm.
5. Draw a flowchart for adding and L2:Understand CO3
subtracting two fixed point binary
numbers where negative numbers
are signed 1’s complement
presentation
6. Multiply each of the following pairs L4:Analyse CO1
of signed 2's compliment numbers
using the Booth multiplication and
n- bit multipliers. In each case
assume that A is multiplicand and B
is multiplier. (i) A=010111 and
B=110110. (ii) A=110011 and
B=101100
7. Discuss about the IEEE standard for L2:Understand CO2
binary floating point arithmetic
8. Draw the flowchart for divide L2:Understand CO3
operation and explain
9. Draw and explain the one stage L2:Understand CO3
decimal arithmetic unit
10. **Explain in detail about the L2:Understand CO3
derivation of BCD adder
UNIT-4
Short Answer Questions-
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. What is DMA? L2:Understand CO2
2. What is the need of IO Interface? L2:Understand CO2
3. Define Priority Interrupt? L1:Remember CO3

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4. List out any 5 IO Devices? L1:Remember CO3

5. What are peripheral devices? Give a L2:Understand CO2
note on video monitors.
Long Answer Questions-
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. What is asynchronous data transfer? L2:Understand CO2
Explain the different types of
Asynchronous data transfer
techniques.
2. Explain in detail floating point L2:Understand CO3
arithmetic operations with examples.
3. What is IOP? Explain the L2:Understand CO2
communication between IOP and
CPU.
4. Explain the following data transfer L2:Understand CO2
modes/techniques.
a)Program Controlled IO
b)Interrupt Initiated IO
5. Write a note on memory hierarchy L2:Understand CO3
with the neat diagram.

6. Consider a cache consisting of 256 L4: Analyse CO1

blocks of 8 words each, for a total of
2048 words, and assume that the main
memory is addressable by a 16-bit
address. The main memory has 64K
words which are divided into 8192
blocks of 8 words each. Find the
number of bits
in Tag, Block and Word Field of the
main memory address for direct
mapping scheme.
7. Explain in detail about DMA operation L2:Understand CO2
with neat diagram
8. Describe in brief the different modes L1: Remember CO3
by which data transfer can take place
between a computer unit and its I/O
devices. What is the difference
between synchronous and
asynchronous data transfer?

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9. Explain in detail about Cache memory L2:Understand CO2

mechanisms
10. Explain in detail about Associative L2:Understand CO2
memory mechanisms
UNIT-5
Short Answer Questions-
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. List out the memory hierarchy? L1:Remember CO3
2. What is associative memory? L2:Understand CO2
3. What is the need of Cache Memory? L1:Understand CO2
4. Define a Pipeline? Give an example. L2:Remember CO3
5. What is inter process arbitration? L2:Understand CO3
Long Answer Questions-
S.NO QUESTION BLOOMS Course Outcome
Taxonomy
1. Explain the different types of Pipeline L2:Understand CO3
techniques.
2. What is mean by IPC. Explain the L2:Understand CO3
Concurrency & Synchronization with
IPC?
3. What is Multiprocessors? Explain in L1:Remember CO4
detail .
4. List out Cache mapping techniques and L2:Understand CO3
Explain all the mapping techniques?
5. Define Auxiliary memory ? Explain L2:Understand CO2
with neat diagram
6. Explain in detail about the RISC L2:Understand CO3
Characteristics
7. Explain in detail about the CISC L2:Understand CO3
Characteristics
8. Explain in detail about the Instruction L2:Understand CO3
Pipeline
9. List the Characteristics of L4:Analyse CO2
Multiprocessors
Explain in detail about the
Interconnection structures of
Multiprocessor
10. Explain in detail about the Interprocessor L2:Understand CO3
arbitration

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OBJECTIVE QUESTIONS:
UNIT-I
1. The register that includes the address of the memory unit is termed as the ____
a) MAR
b) PC
c) IR
d) None of these
2. Which is the operation that a computer performs on data that put in register?
a) Register transfer
b) Arithmetic
c) Logical
d) All of these
3. Which micro operations carry information from one register to another?
a) Register transfer
b) Arithmetic
c) Logical
d) All of these
4. The ‘heart’ of the processor which performs many different operations _____________.
a) Arithmetic and logic unit
b) Motherboard
c) Control Unit
d) Memory
5. Operation of memory transfer are ----------------------.
a) Read
b) Write
c) Both
d) None
6. In memory read the operation puts memory address on to a register known as
a) PC
b) ALU
c) MAR
d) All of these
7. Which operation is binary type, and is performed on bits string that is placed in register?
a) Logical micro operation
b) Arithmetic micro operation
c) Both
d) None
8. Which operation is extremely useful in serial transfer of data?
a) Logical micro operation
b) Arithmetic micro operation
c) Shift micro operation
d) None of these
9. _____ is a command given to a computer to perform a specified operation on some given data:
a) An instruction
b) Command
c) Code
d) None of these
10. An instruction is guided by_____ to perform work according:
a) PC

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b) ALU
c) Both a and b
d) CPU
Fill in the Blanks
11.During the execution of the instructions, a copy of the instructions is placed in the _____
Ans: Cache
12.A processor performing fetch or decoding of different instruction during the execution of
another instruction is called ______
Ans: Pipe-lining
13.When Performing a looping operation, the instruction gets stored in the ______
Ans: Cache
14.The main virtue for using single Bus structure is ____________
Ans: Cost effective connectivity and ease of attaching peripheral devices
15.To extend the connectivity of the processor bus we use ________
Ans: PCI bus
Unit – II
1 A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned
2. What does the hardwired control generator consist of?
a) Decoder/encoder
b) Condition codes
c) Control step counter
d) All of the mentioned
3. The name hardwired came because the sequence of operations carried out is determined by the
wiring.
a) True
b) False
4. The instruction format ‘register to register’ has a length of.
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
5 The instruction “JUMP” belongs to.
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
6 The part of a processor which contains hardware necessary to perform all the operations
required by a computer:
a) Data path
b) Controller
c) Registers
d) Cache

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7 What does MAR stand for?

a) Main Address Register
b) Memory Access Register
c) Main Accessible Register
d) Memory Address Register
8 If the control signals are generated by combinational logic, then they are generated by a type of
_______________ controlled unit.
a) Micro programmed
b) Software
c) Logic
d) Hardwired
9. A set of microinstructions for a single machine instruction is called ___________.
a) Program
b) Command
c) Micro program
d) Micro command
10 In the case of, Zero-address instruction method the operands are stored in _____.
a) Registers
b) Accumulators
c) Push down stack
d) Cache
Fill in the Blanks
11.The _________micro operator can be used to selective set bit of a register
12.The transfer of information from a memory word to the outside environment is called a
___________
13.The Data Register sometimes called a ______________register
14.The addressing mode/s, which uses the PC instead of a general purpose register is ______
15.In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address
is ______ Ans:E=5+[R1]
16.The method of accessing the I/O devices by repeatedly checking the status flags is
___________.
Ans: Status flags
17.The method of accessing the I/O devices by repeatedly checking the status flags is
___________.
Ans: a) Program-controlled I/O
Unit - III
1. Which of the following is not a decimal number?
a) 114
b) 43.47
c) 99.9A
d) 10101
2. A computer language that is written in binary codes only is _____.
a) Machine language
b) C
c) C#
d) pascal
3. The input hexadecimal representation of 1110 is _______________.

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a) 0111
b) E
c) 15
d) 14
4. Convert the binary equivalent 10101 to its decimal equivalent.
a) 21
b) 12
c) 22
d) 31
5. Which of the following is not a binary number?
a) 1111
b) 101
c) 11E
d) 000
6. Which of the following is the correct representation of a binary number?
a) (124)2
b) 1110
c) (110)2
d) (000)2
7. What could be the maximum value of a single digit in an octal number system?
a) 8
b) 7
c) 6
d) 5
8. The maximum number of bits sufficient to represent an octal number in binary is _______.
a) 4
b) 3
c) 7
d) 8
9. The binary number 111 in octal format is ________________.
a) 6
b) 7
c) 8
d) 5
10. The octal equivalent of the binary number (0010010100)2 is ______________.
a) 422
b) 242
c) 224
d) 226
Fill in the Blanks
11.The pipelining process is also called as ______.
Ans: Assembly line operation
12.The fetch and execution cycles are interleaved with the help of ________
Ans: Clock
13.To increase the speed of memory access in pipelining, we make use of _______.
Ans: Cache
______ have been developed specifically for pipelined systems.

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Ans: Optimizing compilers

14.The clock rate of the processor can be improved by _________
Ans: Reducing the amount of processing done in one step By using the overclocking method

UNIT – IV
1. Any electronic holding place where data can be stored and retrieved later whenever required is
____________.
a) memory
b) drive
c) disk
d) circuit
2. Which of the following is the fastest means of memory access for CPU?
a) Registers
b) Cache
c) Main memory
d) Virtual Memory
3. The memory implemented using the semiconductor chips is _________.
a) Cache
b) Main
c) Secondary
d) Registers
4. Size of the ________ memory mainly depends on the size of the address bus.
a) Main
b) Virtual
c) Secondary
d) Cache
5. What is the high speed memory between the main memory and the CPU called?
a) Register Memory
b) Cache Memory
c) Storage Memory
d) Virtual Memory
6. Whenever the data is found in the cache memory it is called as _________.
a) HIT
b) MISS
c) FOUND
d) ERROR
7. LRU stands for ___________.
a) Low Rate Usage
b) Least Rate Usage
c) Least Recently Used
d) Low Required Usage
8. When the data at a location in cache is different from the data located in the main memory, the
cache is called _____________.
a) Unique
b) Inconsistent
c) Variable d) Fault
9. Which of the following is not a write policy to avoid Cache Coherence?

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a) Write through
b) Write within
c) Write back
d) Buffered write
10. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
a) Associative
b) Direct
c) Set Associative
d) Indirect
Fill in the Blanks
11.Which representation is most efficient to perform arithmetic operations on the numbers?
Ans: 2’S complement
12.The processor keeps track of the results of its operations using a flags called ________
Ans: Conditional code flags
13.The register used to store the flags is called as _________
Ans: Status register
14.The Flag ‘V’ is set to 1 indicates that,
Ans: The operation has resulted in an overflow
15.The most efficient method followed by computers to multiply two unsigned numbers is
_______
Ans: Bit pair recording of multipliers

UNIT - V
1. The CISC stands for ___________.
a) Computer Instruction Set Compliment
b) Complete Instruction Set Compliment
c) Computer Indexed Set Components
d) Complex Instruction set computer
2. The computer architecture aimed at reducing the time of execution of instructions is
________.
a) CISC
b) RISC
c) ISA
d) ANNA
3. The Sun micro systems processors usually follow _____ architecture.
a) CISC
b) ISA
c) ULTRA SPARC
d) RISC
4. The iconic feature of the RISC machine among the following is _______.
a) Reduced number of addressing modes
b) Increased memory size
c) Having a branch delay slot
d) All of the mentioned
5. Both the CISC and RISC architectures have been developed to reduce the ______.
a) Cost
b) Time delay

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c) Semantic gap
d) All of the mentioned
6. To increase the speed of memory access in pipelining, we make use of _______.
a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
7. When the processor executes multiple instructions at a time it is said to use _______.
a) single issue
b) Multiplicity
c) Visualization
d) Multiple issues
8. Which of the following architecture is/are not suitable for realizing SIMD?
a) Vector Processor
b) Array Processor
c) Von Neuman
d) All of the above
9. In super-scalar processors, ________ mode of execution is used.
a) In-order
b) Post order
c) Out of order
d) None of the mentioned
10. ______ have been developed specifically for pipelined systems.
a) Utility software
b) Speed up utilities
c) Optimizing compilers
d) None of the mentioned
Fill in the Blanks
11.In multiple Bus organisation, the registers are collectively placed and referred as ______
Ans: Register file
12.The main advantage of multiple bus organisation over a single bus is ____
Ans: Reduction in the number of cycles for execution
GATE: (If applicable)
1. Consider a two-level cache hierarchy with L1 and L2 caches. An application
incurs 1.4 memory accesses per instruction on average. For this application, the miss rate
of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions.
The miss rate L2 expressed correct to two decimal places is _________. (GATE 2107)
2. A processor can support a maximum memory of 4GB, where the memory is word-
addressable (a word consists of two bytes). The size of the address bus of the processor is
at least bits. (GATE2016)
3. The width of the physical address on a machine is 40 bits. The width of the tag field in a
512 KB 8-way set associative cache is _______ bits. (GATE 2016)
4. A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit
instruction word has an opcode, two register operands and an immediate operand. The
number of bits available for the immediate operand field is __________. (GATE 2016)
5. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles
per instruction of four. The same processor is upgraded to a pipelined processor with five

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stages; but due to the internal pipelined delay, the clock speed is reduced to 2 gigahertz.
Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined
processor is _____. (GATE 2016)

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