UNIVERSITY OF EDINBURGH

COLLEGE OF SCIENCE AND ENGINEERING

SCHOOL OF INFORMATICS

INFORMATICS 2C - INTRODUCTION TO COMPUTER

SYSTEMS

Monday 11 th August 2014

14:30 to 15:30

INSTRUCTIONS TO CANDIDATES

1. Answer Parts A and B. The multiple choice questions in Part A are

worth 50% in total and are each worth the same amount. Mark one
answer only for each question — multiple answers will score 0. Marks
will not be deducted for incorrect answers. Part B is worth 50% and
contains TWO questions. Answer ONE of them.

2. Use the special mark sheet for Part A. Use a script book for the ques-
tion from Part B that you answer.

CALCULATORS MAY NOT BE USED IN THIS EXAMINATION

Convener: J. Bradfield
External Examiner: C. Johnson

THIS EXAMINATION WILL BE MARKED ANONYMOUSLY

 Part A
ANSWER ALL QUESTIONS IN PART A. Use the special mark sheet.

1. According to the IEEE 754 floating-point standard, what decimal number is

represented by the 32-bit word with hex value c050 0000?
Remember that, for 32-bit numbers, the exponent bias is 127.

(a) −1.625
(b) −1.25
(c) −2.5
(d) −3.25
(e) −5.75

2. What C code does the following piece of MIPS assembly code correspond to?

slt $t0, $s1, $s2

bne $t0, $zero, skip
sub $s3, $s1, $s2
skip: add $s2, $s3, $s1

(a) if (s1 < s2) { s3 = s1 - s2; } s2 = s3 + s1;

(b) if (s1 > s2) { s3 = s1 - s2; } s2 = s3 + s1;
(c) if (s1 >= s2) { s3 = s1 - s2; } s2 = s3 + s1;
(d) if (s1 >= s2) { s2 = s1 - s3; } s1 = s3 + s2;
(e) if (s1 > s2) { s2 = s1 - s3; } s1 = s3 + s2;

3. Consider executing the following program:

int x[5] = {0,3,5,7,9};

int* y = &x[2];
*(y+2) = *(y--);

What values does the array x hold afterwards?

(a) {0,3,4,7,4}
(b) {0,3,4,7,5}
(c) {0,3,5,5,9}
(d) {0,3,5,7,9}
(e) {0,3,6,7,9}

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4. Which of the following units requires a sequential circuit for its implementation?

(a) S-R latch

(b) Ripple-carry adder
(c) Multiplexor
(d) Exclusive-or gate
(e) ALU

5. In the multi-cycle MIPS processor studied in class, what further functions is the
main ALU used for, beyond carrying out the arithmetic for instructions like add
and sub?

(a) Incrementing the program counter

(b) Computing branch addresses
(c) Computing memory addresses for load and store instructions
(d) (b) and (c)
(e) (a), (b) and (c)

6. Which hazards are present in the following piece of code, on the familiar 5-stage
pipelined MIPS processor discussed in the course?

add $s1, $s2, $s3

sub $s4, $s1, $s2
and $s5, $s2, $s3

(a) Structural hazard only

(b) Control hazard only
(c) Data hazard only
(d) Data hazard and structural hazard
(e) Data hazard and control hazard

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7. Which of the following does not typically result in the invocation of the MIPS
CPU’s exception-handling mechanism?
(a) An I/O system interrupting the CPU.
(b) A virtual memory page fault.
(c) Execution of a syscall MIPS instruction.
(d) A null pointer dereference by a C program.
(e) A Java program executing a throw statement.
8. Why do modern computers have a memory hierarchy rather than a single main
memory?
(a) The hierarchy achieves a better worst-case access time
(b) The hierarchy achieves a better average-case access time
(c) Single main memory is more expensive due to the high cost of dynamic RAM
chips
(d) Both (a) and (b)
(e) None of (a), (b) or (c)
9. Consider a direct-mapped cache with 4096 blocks/lines in which each block has
four 32-bit words. How many bits are needed for the tag and index fields, assum-
ing a 32-bit address?
(a) 16 bits tag, 12 bits index.
(b) 12 bits tag, 16 bits index
(c) 18 bits tag, 12 bits index.
(d) 12 bits tag, 18 bits index.
(e) 18 bits tag, 5 bits index.
10. What is memory-mapped Input/Output?
(a) When the processor reads/writes data to the memory, and peripherals copy
the data from memory into their internal storage when receiving data, or
write to memory when transmitting.
(b) When the processor instructs the DMA controller to transfer data from a
memory location to a peripheral or from a peripheral to a memory location.
(c) When the processor uses memory to buffer the input/output data it is read-
ing from or writing to peripherals.
(d) When specific memory addresses are used for communicating with I/O pe-
ripherals.
(e) When blocks of memory are used as the source/destination of input/output
data streams.

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 Part B
ANSWER ONE QUESTION FROM PART B.

1. (a) Convert the following C code into equivalent MIPS assembly code.
int a[50];
int i;
int m;
int n;
...
i = 1;
while (i != 50) {
m = a[i];
n = a[i-1];
if (m > n) { a[i] = n; a[i-1] = m; }
i++;
}
When your code starts, assume that the base address of array a is held in
register $s0, integer i is held in register $s1, integer m is held in register
$s2 and integer n is held in register $s3. Assume integers are 32-bit and
memory is byte addressable. You are free to use any other registers as you
wish. Please comment your code well to ease understanding. [18 marks]
(b) Draw a circuit diagram for a 4-input multiplexor built from NAND gates
and inverters. The data inputs of the multiplexor are D0-D3, the select
inputs are S1, S0 and the output is Y. A value 00 on S1,S0 selects data
input D0 on output Y, 01 selects D1, 10 selects D2 and 11 selects D3. [10 marks]
(c) i. How does a pipelined processor differ from a multi-cycle processor such
as discussed in class? Why can pipelining improve processor perfor-
mance? [6 marks]
ii. Discuss why pipelining is most effective when instructions have similar
cycle-by-cycle patterns of resource usage and when each instruction uses
distinct resources at each stage of execution. [4 marks]
(d) Explain what the Translation Lookaside Buffer is and how it operates. [12 marks]

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2. (a) Write C code for a function
void removespaces(char* s)
that modifies the string s such that all spaces are removed, but otherwise
all the characters of the original string are present and in order. Assume
that the string s is null terminated and ensure the resulting string is also
null terminated. Please add comments to your code explaining the main
components. [16 marks]
(b) Consider the familiar multi-cycle implementation of MIPS used in the course.
The datapath is shown in the figure below.

We need to add the instruction push r, n(s) which writes the contents of
register r to the address contained in s and then modifies s to contain s + n
where n is a 16-bit 2’s complement immediate constant included in the
instruction. Most commonly n might be 4 or -4, so the instruction can be
used for realising push operation on a stack.
Describe the changes needed in the datapath (including changes inside the
sub-blocks shown in the figure) and give a detailed description of what task
is performed in each cycle of execution for this instruction. [14 marks]
QUESTION CONTINUES ON NEXT PAGE

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 QUESTION CONTINUED FROM PREVIOUS PAGE

(c) What is the dual mode protection mechanism found in MIPS and other
modern processors? Explain why it is used and when the processor mode
changes. [10 marks]
(d) Compare the three main input/output methods discussed in the course:
polling-based, interrupt-based, and direct memory access. What are their
advantages and disadvantages? [10 marks]

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