LABORATORY RECORD

(VLSI DESIGN LAB - 20EC503)

V Semester, B.Tech-ECE

Department of
Electronics and Communications Engineering

GMR Institute of Technology

(An Autonomous Institute Affiliated to JNTUK,
Kakinada)
(Accredited by NBA, NAAC with “A” grade & ISO 9001-2008 certified Institution)
(Approved by AICTE, New Delhi)
GMR Nagar, Rajam – 532127
Vizianagaram - Dist., Andhra Pradesh
A.Y: 2022-23
 LABORATORY RECORD
(VLSI DESIGN LAB-20EC503)
V Semester, B.Tech-ECE

Name of the Student: _______________________________

Roll No:

Department of Electronics and Communication Engineering

GMR INSTITUTE OF TECHNOLOGY

(An Autonomous Institute Affiliated to JNTUK, Kakinada)
(Accredited by NBA, NAAC with grade ‘A’ & ISO 9001:2008 Certified Institution)
Approved by AICTE, New Delhi GMR NAGAR, RAJAM-532 127
 GMR INSTITUTE OF
TECHNOLOGY
An Autonomous Institute Affiliated to JNTUK,
Kakinada GMR NAGAR, RAJAM-532127
VIZIANAGARAM DIST., ANDHRA PRADESH, INDIA

CERTIFICATE OF COMPLETION OF LABORATORY

EXPERIMENTS

JNTU No.:

CERTIFICATE

This is to certify that Mr./Ms.

of year B.Tech / M.Tech Semester in branch

has completed his / her practical work in

during the academic year .

No. of Experiments Conducted:

No. of Experiments Performed:

Faculty In-charge Head of the Department

 INDEX SHEET
Page
S.No. Date Name of the Experiment Marks Signature
No.
Simulation of nMOS inverter with
1.
enhancement load
2. Functional verification of CMOS inverter

3. Layout design of CMOS inverter

4. Perform the DRC and LVS for the CMOS

inverter Layout
5. Perform the RC extraction for CMOS
inverter
6. Compute the delay of CMOS inverter after
the RC extraction
7. Design and simulation of Half adder
using transmission gate logic
8. Simulate a one transistor Common
Source amplifier with resistive load
9. Design and simulation of Half adder
using pass transistor
10. Design and ASIC Implementation of
4:1 MUX
11. Design and FPGA Implementation of
2:4 Decoder

12. Design and FPGA Implementation of a D-

Latch

Average Marks
 Environment Setting & Invocation of the Cadence Tool

1. Do the right click on desktop then click on Open Terminal

2. Change to working directory: “cd <path>”

3. Enter “csh” on command line and enter

4. Set the environment: “source /home/install/cshrc” (enter)

5. A welcome window pops up

6. In the new window, click “virtuoso” (enter)

7. Then the Cadence Virtuoso environment window pops up. Proceed with the virtuoso flow to
complete each experiment.
 Date:
Experiment-1
Aim: To simulate the nMOS inverter with enhancement load.

Apparatus: Cadence Tool.

Theory:

NMOS inverter circuit with an enhancement load with the substrate connected to ground.
Although, the source-to-body voltage (VSB) of upper nMOS transistor is zero, that of lower nMOS
transistor is equal to Vout. As a result, the threshold voltage of lower nMOS transistor is no longer
equal to the threshold voltage of upper nMOS transistor. For straight forward hand analysis, it is
common to neglect the transistor body effect and assume that each transistor has the same threshold
voltage.

N-type Enhancement load is always in the saturation region due to the gate terminal is
directly connected to Vdd. So the pullup transistor is always in the ON state. When the Logic 0 is
given to the N-type Enhancement load inverter the pulldown nMOS is in cutoff region then it act's
as open circuit. As the Enhancement load is already in saturation region. The Vdd is directly
connected to the output and gives Logic 1 at the output terminal. When the Logic 1 is given to the
N-type Enhancement load inverter then, pulldown nMOS will be ON state. As the two transistors
are in ON state the Vdd is directly connected to the ground terminal so the output is Logic 0. As
there is some internal resistance present due to the transistors there is some static power dissipation.

Procedure:
1. After opening the VIRTUOSO window click on File----New----Library and fill as shown, then click OK and
select gpdk180 Library then click on File----New----Cell View and fill the library and cell name.

2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180 and
select nMOS from the cell. After that press “P” for creating pins and press “W” for wire.
And connect the circuit as shown. Click on Check and Save.
3. Now click on Create---- Cell View ----from Cell View and click OK then select top,
bottom, right, left pins as shown and press OK.

4. Now a pop up window appears as shown,

Then by using drawing tools create a symbol for nMOS inverter with enhancement load as
shown, then click on Check and Save.

5. Now click on File----New and change the cell name then click OK. Then press “I” and give
the library and cell name as before given, and press OK.
6. Now press “I” and select library as analoglib and cell as vdc, vpulse and gnd as shown,

Now connect by pressing “W” connect the wires as shown, then label the wires by clicking
“L” and enter the wire names then press OK and click on the wire to label it with a name.
Then click on Check and Save.

7. Now click on Launch----ADEL. Then a pop up window appears click on Setup----

Simulator/Directory then press OK.
 Go to Setup----Model Library Setup and do changes as shown, and press OK.

8. Now click on Analyses----Choose and do the changes as shown in trans,

9. Now click on Outputs----Setup then a window opens as, click on From design and select
input and output and then press OK. Then click on Simulation----Netlist & Run.
Result:

Conclusion:
 Date:
Experiment-2
Aim: To verify the functionality of CMOS inverter.

Apparatus: Cadence Tool.

Theory:
CMOS inverter is designed with one pMOS and one nMOS. Both has the common input
across gate. And pMOS and nMOS are connected in series, the pMOS is connected to Vdd and
nMOS is connected to ground. Output is taken at the common point between the pMOS and nMOS.
When the low input voltage is given to the CMOS inverter, then the pMOS transistor is switched
ON whereas the nMOS transistor will switch OFF by allowing the flow of electrons throughout the
gate terminal & generating high logic output voltage. Similarly, when the high input voltage is given
to the CMOS inverter then, the pMOS transistor is switched OFF whereas the nMOS transistor will
be switched ON avoiding as many electrons from attaining the output voltage & generating low
logic output voltage.

Procedure:
1. After opening the VIRTUOSO window click on File----New----Library and fill as shown, then click OK and
select gpdk180 Library then click on File----New----Cell View and fill the library and cell name as before,

2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180 and
select nMOS and pMOS from the cell. After that press “P” for creating pins and press
“W” for wire. And connect the circuit as shown. Click on Check and Save.
3. Now click on Create----Cell View----from Cell View and click OK then select top,
bottom, right, left pins as shown and press OK.

4. Now a pop up window appears as shown,

Then by using drawing tools create a symbol for CMOS inverter as shown, then click on Check
and Save.

5. Now click on File----New as shown, and click OK. Then press “I” and give the library and
cell name as before given, and press OK.

6. Now press “I” and select library as analoglib and cell as vdc, vpulse, cap and gnd as shown,
 Now connect by pressing “W” connect the wires as shown, then label the wires by clicking
“L” and enter the wire names then press OK and click on the wire to label it with a name.
Then click on Check and Save.

7. Now click on Launch----ADEL. Then a pops up window appears click on Setup----

Simulator/Directory then press OK.
 Go to Setup----Model Library Setup and do changes as shown, and press OK.

8. Now click on Analyses----Choose and do the changes as shown both in trans and dc,

In dc after clicking on component parameters click on Select Component----Select Vpulse

and click on dc then click OK.
9. Now click on Outputs----Setup then a window opens as, click on From design and
select input and output and then press OK. Then click on Simulation----Netlist &
Run.
Result:

Conclusion:
 Date:
Experiment-3
Aim: To draw the layout design of CMOS inverter.

Apparatus: Cadence Tool.

Theory:
CMOS inverter is designed with one pMOS and one nMOS. Both has the common
input across gate. And pMOS and nMOS are connected in series, the pMOS is connected to
Vdd and nMOS is connected to ground. Output is taken at the common point between the
pMOS and nMOS. When the low input voltage is given to the CMOS inverter, then the pMOS
transistor is switched ON whereas the nMOS transistor will switch OFF by allowing the flow
of electrons throughout the gate terminal & generating high logic output voltage. Similarly,
when the high input voltage is given to the CMOS inverter then, the pMOS transistor is
switched OFF whereas the nMOS transistor will be switched ON avoiding as many electrons
from attaining the output voltage & generating low logic output voltage.

Procedure:
1. After opening the VIRTUOSO window click on File----New----Library and fill as shown, then click
OK and select gpdk180 Library then click on File----New----Cell View and fill the library and cell name
as before.

2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180
and select nMOS and pMOS from the cell. After that press “P” for creating pins and
 press “W” for wire. And connect the circuit as shown. Click on Check and Save.
3. Now click on ADEL----Layout XL then a startup option window opens then click
OK. Then a New File opens as shown then click OK. Then a new window pops up as

shown,
4. Now click on Connectivity----Generate----All from source then a window pops up click Shift+F. Then
the window will appear as,

5. Now click on “P” and connect the poly and metal as shown below,

• Then click on “O” and select M1 poly and insert Vin inside the M1 poly.
• Then connect the Vout metal box to the output metal connection.
• Then insert Vdd and Vss metal boxes inside the Vdd and Vss extended metal lines.
• Then click on “O” and select M1 NWELL and place it on the extended metal line of pMOS.
• Again click on “O” and select M1 PSUB and place it on the extended metal line of nMOS.
• Then click on nwell from left side and press “R” then draw the rectangle box around the pMOS,
as show below,
Results:
 Date:
Experiment-4
Aim: To perform the DRC and LVS for the CMOS inverter Layout.

Apparatus: Cadence Tool.

Theory:
A design rule is a geometric constraint imposed on circuit board, semiconductor
device, and integrated circuit (IC) designers to ensure their designs function properly, reliably,
and can be produced with acceptable yield. Electronic design automation is used extensively
to ensure that designers do not violate design rules with a process called Design Rule Checking
(DRC). DRC is a major step during physical verification which also involves LVS (layout
versus schematic) checks, XOR checks, ERC (electrical rule check). The importance of design
rules and DRC is greater for ICs, which have micro- or nano-scale geometries. For advanced
processes, some fabs also insist upon the use of more restricted rules to improve yield.

LVS stands for Layout vs Schematic. Simulations of schematic circuit are unlikely to
represent the real time behavior in real time PCB. As the results are lack of signal integrity
problems, but also a poor layout will cause crosstalk, unwanted resonances and other
problems.

Pre-layout And Post-layout Simulations: The pre-layout simulations take place before
completing the PCB layout, while post-layout simulations use the completed PCB layout as
their basis. With signal-integrity simulations we can determine the best design parameters for
each circuit block.

The Cadence LVS tool provides several sources of information which can be used to
find and debug the problems that caused LVS to fail or not pass. This document briefly
describes some of these information sources and provides some techniques for solving
common LVS problems.
Procedure:

1. After opening the VIRTUOSO window click on File----New----Library and fill as

shown, then click OK and select gpdk180 Library then click on File----New----Cell
View and fill the library and cell name as before.
2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180
and select nMOS and pMOS from the cell. After that press “P” for creating pins and
press “W” for wire. And connect the circuit as shown. Click on Check and Save.

3. Now click on ADEL----Layout XL then a startup option window opens then click
OK. Then a New File opens as shown then click OK. Then a new window pops up as
shown.
4. Now click on Connectivity----Generate----All from source then a window pops up click Shift+F. Then
the window will appear as,

5. Now click on “P” and connect the poly and metal as shown below,
• Then click on “O” and select M1 poly and insert Vin inside the M1 poly.
• Then connect the Vout metal box to the output metal connection.
• Then insert Vdd and Vss metal boxes inside the Vdd and Vss extended metal
lines.
• Then click on “O” and select M1 NWELL and place it on the extended metal
line of pMOS.
• Again click on “O” and select M1 PSUB and place it on the extended metal
line of nMOS.
• Then click on nwell from left side and press “R” then draw the rectangle box
around the pMOS,as show below, then click on Check and Save.
• Now click on Assura and select the Technology as shown below, then click OK.

• Again click on Assura----Run DRC then a pop up window opens as shown, then
do the changes as shown and click OK. Then a window pops up by showing
the Run Name then click OK. After that DRC check completion window pops
up then click on Yes. After that a window pops up showing No DRC errors
found.

• Again click on Assura----Run LVS then a pop up window opens as shown, then
do the changes as shown and click OK. Then a window pops up by showing
 the Run Name then click OK. After that a window pops up as shown below,

Results:
 Date:
Experiment-5
Aim: To perform the RC extraction for CMOS inverter.
Apparatus: Cadence Tool.
Theory:
CMOS inverter is designed with one pMOS and one nMOS. Which are having common
input at gate. And pMOS and nMOS are connected in series, the pMOS is connected to Vdd and
nMOS is connected to ground. Output is taken at the common point between the pMOS and nMOS.
For faster timing closure, a parasitic extraction method is developed for the pre-route VLSI
design. This method generates virtual route and estimates congestion using the placement
information of standard cells, and then extract the interconnect parasitics with the pattern-library
method.
Procedure:
1. After opening the VIRTUOSO window click on File----New----Library and fill as shown, then click OK and
select gpdk180 Library then click on File----New----Cell View and fill the library and cell name as before,

2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180 and
select nMOS and pMOS from the cell. After that press “P” for creating pins and press
“W” for wire. And connect the circuit as shown. Click on Check and Save.
3. Now click on Create---- Cell View ----from Cell View and click OK then select top,
bottom, right, left pins as shown and press OK.

4. Now a pops up window appears as shown,

Then by using drawing tools create a symbol for CMOS inverter as shown, then click on Check
and Save.

5. Now click on File----New as shown, and click OK. Then press “I” and give the library and
cell name as before given, and press OK.

6. Now press “I” and select library as analoglib and cell as vdc, vpulse, cap and gnd as shown,
 Now connect by pressing “W” connect the wires as shown, then label the wires by clicking
“L” and enter the wire names then press OK and click on the wire to label it with a name.
Then click on Check and Save.

7. Now click on Launch----ADEL. Then a pops up window appears click on Setup----

Simulator/Directory then press OK.
 Go to Setup----Model Library Setup and do changes as shown, and press OK.

8. Now click on Analyses----Choose and do the changes as shown both in trans and dc,

In dc after clicking on component parameters click on Select Component----Select Vpulse

and click on dc then click OK.
9. Now click on Outputs----Setup then a window opens as, click on From design and select
input and output and then press OK. Then click on Simulation----Netlist & Run.
10. Then open the Schematic view and then click on ADEL----Layout XL then a startup
option window opens then click OK. Then a New File opens as shown then click OK. Then
a new window pops up as shown.
11. Now click on Connectivity----Generate----All from source then a window pops up click
Shift+F. Then the window will appear as,

12. Now click on “P” and connect the poly and metal as shown below,

• Then click on “O” and select M1 poly and insert Vin inside the M1 poly.
• Then connect the Vout metal box to the output metal connection.
• Then insert Vdd and Vss metal boxes inside the Vdd and Vss extended metal lines.
• Then click on “O” and select M1 NWELL and place it on the extended metal line of
pMOS.
• Again click on “O” and select M1 PSUB and place it on the extended metal line of
nMOS.
• Then click on nwell from left side and press “R” then draw the rectangle box around
the pMOS, as show below, then click on Check and Save.
13. Now click on Assura and select the Technology as shown below, then click OK.

14. Again click on Assura----Run DRC then a pop up window opens as shown, then do the
changes as shown and click OK. Then a window pops up by showing the Run Name then
click OK. After that DRC check completion window pops up then click on Yes. After that
a window pops up showing No DRC errors found.
15. Again click on Assura----Run LVS then a pop up window opens as shown, then do the changes
as shown and click OK. Then a window pops up by showing the Run Name then click OK.

16. Now again run the simulation to proceed for next setps,

17. Then go to the layout and click on Assura----Run Quantus QRC and do changes as shown below,
after that click OK.

Then a small window will open with Library, Cell Name then click Close.
 18. Now open the VIRTUOSO window and go to click on Tools----Library Manager then select the
library and cell then double click on av_extracted as shown below,

After double click on av_extracted then a window pops up then click Shift+F. Then we get the parasitic
extraction.

19. Then click on the next cell name so that at the right side you can find Schematic and Symbol. Then
select Schematic and click on File----New----Cell View, then a window opens then change the Type
to config and click OK. Then a window opens and click on Use Template then another window
opens. Then do the changes as the Name to spectre and click OK.
20. After that New Configuration window opens then change the view to schematic and click OK.

21. Now left click and right click on the generated IO file, then select av_extracted after that click on
open. Now a window pops up as shown below,
Then double click on the Inverter a window pops up then change the cell to av_extracted and then click
OK.

22. Now again go to the Launch----ADEL. Then a pops up window appears click on Setup----
Simulator/Directory then press OK.

Go to Setup----Model Library Setup and do changes as shown, and press OK.

23. Now click on Analyses----Choose and do the changes as shown both in trans and dc,

In dc after clicking on component parameters click on Select Component----Select Vpulse

and click on dc then click OK.
24. Now click on Outputs----Setup then a window opens as, click on From design and select
input and output and then press OK. Then click on Simulation----Netlist & Run.
Results:
 Date:
Experiment-6
Aim: To compute the delay of CMOS inverter after the RC extraction load.

Apparatus: Cadence Tool.

Theory:
CMOS inverter is designed with one pMOS and one nMOS. Which are having common
input at gate. And pMOS and nMOS are connected in series, the pMOS is connected to Vdd and
nMOS is connected to ground. Output is taken at the common point between the pMOS and
nMOS.
For faster timing closure, a parasitic extraction method is developed for the pre-route VLSI
design. This method generates virtual route and estimates congestion using the placement
information of standard cells, and then extract the interconnect parasitics with the pattern-library
method.
Procedure:

1. After opening the VIRTUOSO window click on File----New----Library and fill as

shown, then click OK and select gpdk180 Library then click on File----New----Cell
View and fill the library and cell name as before.

2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180
and select nMOS and pMOS from the cell. After that press “P” for creating pins and
press “W” for wire. And connect the circuit as shown. Click on Check and Save.
3. Now click on Create---- Cell View ----from Cell View and click OK then select top,
bottom, right, left pins as shown and press OK.

4. Now a pop up window appears as shown,

Then by using drawing tools create a symbol for CMOS inverter as shown, then click on Check
and Save.

5. Now click on File----New as shown, and click OK. Then press “I” and give the library
and cell name as before given, and press OK.

6. Now press “I” and select library as analoglib and cell as vdc, vpulse, cap and gnd as
shown,
Now connect by pressing “W” connect the wires as shown, then label the wires by clicking
“L” and enter the wire names then press OK and click on the wire to label it with a name.
Then click on Check and Save.

7. Now click on Launch----ADEL. Then a pops up window appears click on Setup----

Simulator/Directory then press OK.
Go to Setup----Model Library Setup and do changes as shown, and press OK.

8. Now click on Analyses----Choose and do the changes as shown both in trans and dc,

In dc after clicking on component parameters click on Select Component----Select Vpulse

and click on dc then click OK.
9. Now click on Outputs----Setup then a window opens as, click on From design and
select input and output and then press OK. Then click on Simulation----Netlist & Run.
10. Then click on Tools----Calculator then another window pops up then remove the tick
mark at the chip and select wave as shown below,
11. Then select delay and select the signal 1&2 as input and output in trans as shown below,
then click OK.
Then the buffer will be updated as shown above, then click on Append then a window opens as,

12. Then open the Schematic view and then click on ADEL----Layout XL then a startup
option window opens then click OK. Then a New File opens as shown then click OK.
Then a new window pops up as shown,
13. Now click on Connectivity----Generate----All from source then a window pops up
click Shift+F. Then the window will appear as,

14. Now click on “P” and connect the poly and metal as shown below,

• Then click on “O” and select M1 poly and insert Vin inside the M1 poly.
• Then connect the Vout metal box to the output metal connection.
• Then insert Vdd and Vss metal boxes inside the Vdd and Vss extended metal lines.
• Then click on “O” and select M1 NWELL and place it on the extended metal line of
pMOS.
• Again click on “O” and select M1 PSUB and place it on the extended metal line of
nMOS.
• Then click on nwell from left side and press “R” then draw the rectangle box around
the pMOS,as show below, then click on Check and Save.
15. Now click on Assura and select the Technology as shown below, then click OK.

16. Again click on Assura----Run DRC then a pop up window opens as shown, then do the
changes as shown and click OK. Then a window pops up by showing the Run Name
then click OK. After that DRC check completion window pops up then click on Yes.
After that a window pops up showing No DRC errors found.

17. Again click on Assura----Run LVS then a pop up window opens as shown, then do the
changes as shown and click OK. Then a window pops up by showing the Run Name
 then click OK.

18. Now again run the simulation to proceed for next setps.

19. Then go to the layout and click on Assura----Run Quantus QRC and do changes as shown
below, after that click OK.

Then a small window will open with Library, Cell Name then click Close.
 20. Now open the VIRTUOSO window and go to click on Tools----Library Manager then select
the library and cell then double click on av_extracted as shown below,

After double click on av_extracted then a window pops up then click Shift+F. Then we get the parasitic
extraction.

21. Then click on the next cell name so that at the right side you can find Schematic and Symbol.
Then select Schematic and click on File----New----Cell View, then a window opens then change
the Type to config and click OK. Then a window opens and click on Use Template then another
window change the Name to spectre and click OK.

22. After that New Configuration window opens then change the view to schematic and click
OK.
 23. Now left click and right click on the generated IO file, then select av_extracted after that click
on open. Now a window pops up as shown below,

Then double click on the Inverter a window pops up then change the cell to av_extracted and then click
OK.

24. Now again go to the Launch----ADEL. Then a pop up window appears click on Setup----
Simulator/Directory then press OK.
Go to Setup----Model Library Setup and do changes as shown, and press OK.

25. Now click on Analyses----Choose and do the changes as shown both in trans and dc,

In dc after clicking on component parameters click on Select Component----Select Vpulse

and click on dc then click OK.
26. Now click on Outputs----Setup then a window opens as, click on From design and
select input and output and then press OK . Then click on Simulation----Netlist & Run.
27. Then click on Tools----Calculator then another window pops up then remove the tick
mark at the chip and select wave as shown below,
28. Then select delay and select the signal 1&2 as input and output in trans as shown below,
then click OK.
Then the buffer will be updated as shown above, then click on Append then a window opens as,

Results:
 Date:
Experiment-7
Aim: To design and simulation of Half adder using transmission gate logic.

Apparatus: Cadence Tool.

Theory:
A transmission gate, or analog switch, is defined as an electronic element that will
selectively block or pass a signal level from the input to the output. This solid-state switch is
comprised of a pMOS transistor and nMOS transistor.
Half adder is a combinational arithmetic circuit that adds two numbers and produces a
sum bit and carry bit both as output. The addition of bits is done using a combination circuit
called a Half adder. The input variables are augend and addend bits and output variables are
sum & carry bits.
The conventional CMOS logic base half adder is design using 6 transistors for AND
logic gate and 14 transistors for XOR logic gate. Thus 20 transistors are required to design
conventional half adder logic. The transmission gate are AND logic gate requires 2 transistors
and XOR gate requires 4 transistors. With the help of the transmission gates we can design the
half adder with only 6 transistors.

Procedure:

1. After opening the VIRTUOSO window click on File----New----Library and fill as shown,
then click OK and select gpdk180 Library then click on File----New----Cell View and fill
the library and cell name as before,

2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180 and
select nMOS and pMOS from the cell for desigining transmission gate. After that press
“P” for creating pins and press “W” for wire. And connect the circuit as shown. Click on
Check and Save.
 3. Now click on Launch----ADEL and click on Set up----Simulator/Directory and click OK.

Go to Setup----Model Library Setup and do changes as shown, and press OK.

Go to Set up----Stimuli and fill all the values as shown below,

4. Now click on Analyses----Choose and select trans as shown below, then click OK,

5. Now click on Output----Set up and select from design then select the input and output pins.
 6. Now click on Simulation----Netlist & Run for the output waveforms,

Results:
 Date:
Experiment-8
Aim: To simulate a one transistor Common Source amplifier with resistive load.

Apparatus: Cadence Tool.

Theory:

CS stage with resistive load converts the changes in overdrive voltage (Vov) to a small signal
drain current (Id) which then passes through load resistor (Rd) to produce an output voltage (Vout).
In this section the per-formance measures and design constraints for a specific common source
amplifier are expressed in terms of overdrive voltage (Vov), drain current (Id), load resistor (Rd)
and supply voltage (VDD) considered. If the input voltage increases from zero, M1 is off and
Vout=Vdd. As Vin approaches Vth, M1 begins to turn on, drawing current from Rd and lowering
Vout. If Vdd is not excessively low, M1 turns on in saturation. With furthur increase in Vin, Vout
drops more and the transistor continues to operate in saturation until Vin exceeds Vout by Vth.
Procedure:

1. After opening the VIRTUOSO window click on File----New----Library and fill as shown,
then click OK and select gpdk180 Library then click on File----New----Cell View and fill
the library and cell name as before.

2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180 and
select nMOS and polyres from the cell for desigining transmission gate. After that press “P”
 for creating pins and press “W” for wire. And connect the circuit as shown. Click on Check
and Save.

3. Now click on Create---- Cell View ----from Cell View and click OK then select top,
bottom, right, left pins as shown and press OK.
4. Now a pop up window appears as shown. And give it a name as cs amplifier. Then click on
Check and save.

5. Now click on File----New as shown, and click OK. Then press “I” and give the library
and cell name as before given, and press Hide.

6. Now press “I” and select library as analoglib and cell as

 vdc and gnd as shown.

7. Now connect by pressing “W” connect the wires as shown, then label the wires by clicking
“L” and enter the wire names then press OK and click on the wire to label it with a name.
Then click on Check and Save.

8. Now click on Launch----ADEL. Then a pop up window appears click on Setup----

Simulator/Director then press OK.

Go to Setup----Model Library Setup and do changes as shown, and press OK.

9. Now click on Analyses----Choose and do the changes as shown in Trans. And click on OK.
Then click on Outputs----Setup then a window opens as, click on From design and select
input and output and then press OK.

10. Now go to the Setup---Stimuli and give the related values, the pattern parameter data and
click Apply then OK.
Result:

Conclusion:
 Date:
Experiment-9
Aim: To design and simulation of Half adder using pass transistor.

Apparatus: Cadence Tool.

Theory:
Pass transistor logic (PTL) describes several logic families used in the design of integrated
circuits (ICs). It reduces the count of transistors used to make different logic gates, by eliminating
redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit,
instead of as switches connected directly to supply voltages. This reduces the number of active devices, but
has the disadvantage that the difference of the voltage between high and low logic levels decreases at each
stage. Each transistor in series is less saturated at its output than at its input. If several devices are chained
in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to
the full value. By contrast, conventional CMOS logic switches transistors so the output connects to one of
the power supply rails (resembling an open collector scheme), so logic voltage levels in a sequential chain
do not decrease. Simulation of circuits may be required to ensure adequate performance.

Half adder is a combinational arithmetic circuit that adds two numbers and produces a
sum bit (s) and carry bit (c) both as output. The addition of bits is done using a combination
circuit called a Half adder. The input variables are augend and addend bits and output variables
are sum & carry bits.
The conventional CMOS logic base half adder is design using 6 transistors for AND
logic gate and 14 transistors for XOR logic gate. Thus 20 transistors are require to design
conventional half adder logic. The pass transister’s AND logic gate requires 1 transistors and
XOR gate requires 2 transistors. With the help of the pass transistors we can design the half
adder with only 3 transistors.

Procedure:

1. After opening the VIRTUOSO window click on File----New----Library and fill as shown,
then click OK and select gpdk180 Library then click on File----New----Cell View and fill
the library and cell name as before,
 2. Then a window pops up then press “I” on keyboard. Then select the library as gpdk180 and
select nMOS and pMOS from the cell for desigining transmission gate. After that press
“P” for creating pins and press “W” for wire. And connect the circuit as shown. Click on
Check and Save.

3. Now click on Launch----ADEL and click on Set up----Simulator/Directory and click

OK.

Go to Setup----Model Library Setup and do changes as shown, and press OK.

Go to Set up----Stimuli and fill all the values as shown below, and keep the values for other
parameters same and change only the pattern parameter data.
Make sure that the pattern will be complementary for Abar and Bbar with respect to the inputs A
and B.

4. Now click on Analyses----Choose and select trans as shown below, then click OK,
 5. Now click on Output----Set up and select from design then select the input and output pins,

6. Now click on Simulation----Netlist & Run for the output waveforms,

Results: