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Ac Abstract Validation02

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207 views11 pages

Ac Abstract Validation02

Uploaded by

anilkumar kurra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CDC Errors:

1.SDC_59: Error occur due improper use of the TCL command’s.

>In the default .xml need to update the SCF switch. Usually the SDC generated from the SCF flow
and that switch has to be updated from .xml file and the generated SDC has to be converted in to
SGDC format. That switch to be enabled from the .prj file.

Ac abstract validation02 (26):


Reports block abstraction mismatch with top level design

Data Path Domain Mismatch: Top-level clocks

sswrp_gpu.u_sswrp_gpu_aux.u_sswrp_gpu_aon.u_Ipcm_gpu_instu_icm_wrapper.u_Icm.u_icm_core
.u_occ_2.occ_cgc_fast_clock.SIZEONLY_latch_u0.Q",block-level clocks 'NA block port
'gpu_rem_Ipcm_cik_warm_rst out_n', block instance 'sswrp_gpu.u_ip_gpu_top_wrapper.u ip_gpu
top.i_rgx_rogue4_0' (block:'rgx_rogue4)

iolations Waiver Tree

Explanation:
Clocks Mismatch

This mismatch occurs in the following cases:

 If a top-level clock reaches to a clock port of a block, but that clock port is not constrained by
the clock constraint.

 If a block-level clock port is not driven from a top-level clock port.

This can occur when the clock constraint is defined on a block port, but a top-level clock does not
reach that block port.

Data Path Domain Mismatch


This mismatch occurs if an abstract-block port is driven from a sequential instance, and there is a
mismatch between the clock pin driving this sequential instance and the clock specified in the -
clock argument of the abstract_port or the input constraint.

Ac_glitch03

Reports clock domain crossings subject to glitches


Use this rule to detect glitches at clock domain crossings.
Unate/Binate Analysis

You can configure the Ac_glitch03 rule to report violations related with same source reconvergence
when the reconverging paths have different polarities or at least one path has an unknown polarity.
Ac_unsync01

Reports unsynchronized clock domain crossing for scalar signals

Potential Issues

This violation appears if an unsynchronized data transfer occurs between different domain scalar
signals.
Consequences of Not Fixing

If you do not fix this violation, unsynchronized crossings may cause metastability issues in a design.
This may cause functional issues resulting in chip failure.

Ac_unsync02

Reports for unsynchronized clock domain crossings for vector signals

When to Use

Use this rule to find unsynchronized clock domain crossings for vector signals in a design.

Prerequisites

Specify the following details before running this rule:

Specify the Advanced_CDC and adv_checker license features.

Specify clock signals in any of the following ways:

By using the clock constraint

By using the automatically-generated clock information after setting


the use_inferred_clocks parameter to yes
Ac_conv01

Reports signals from the same domain that are synchronized in the same destination domain and
converge after any number of sequential elements
Ac_conv02

Reports same-domain signals that are synchronized in the same destination domain and converge
before sequential elements.

When to Use

Use this rule to check combinational convergences of the same domain signals synchronized in the
same destination domain.

Prerequisites

Following are the prerequisites for running this rule:

Specify clock signals in any of the following ways:

By using the clock constraint.

By setting the use_inferred_clocks parameter to yes to enable auto-generation of clock signals.

By using a combination of both the above methods.

Use the Advanced_CDC and adv_checker licenses for running this rule.

Description

The details of the Ac_conv02 rule are covered under the following topics:

Reasons for the Ac_conv02 Rule Violation

Checking the Gray Encoding of Converging Signals

Features of the Ac_conv02 Rule

Handling MUXes by the Ac_conv02 Rule

Reasons for the Ac_conv02 Rule Violation


The Ac_conv02 rule reports same source signals that converge after satisfying the following
properties:

Signals from the same source domain are synchronized in the same destination domain.

The signals are synchronized using Conventional Multi-Flop Synchronization Scheme, Synchronizing
Cell Synchronization Scheme, or Qualifier Synchronization Scheme Using qualifier -crossing.

Synchronized signals converge before encountering a sequential element (a flip-flop, latch, or


sequential library cell).

The same source signals are further analyzed to determine whether a specific signal in the fan-in
cone is driving these signals or the same signal is getting synchronized multiple times. You can
control the depth of this fan-in cone through the conv_src_seq_depth parameter.

The following figure shows an example of convergence of signals coming from same source clock
domains.
Ac_conv03

Checks different domain signals synchronized in the same destination domain and are converging

When to Use

Use this rule to check convergences of different domain signals that are synchronized in the same
domain.

Prerequisites

Specify clock signals in any of the following ways:

By using the clock constraint

By using the automatically generated clock signals after setting the use_inferred_clocks parameter
to yes

By using a combination of both the above methods

Description

The details of the Ac_conv03 rule are covered under the following topics:

Reasons for the Ac_conv03 Rule Violation

Features of the Ac_conv03 Rule

Handling MUXes by the Ac_conv03 Rule

Reasons for the Ac_conv03 Rule Violation

The Ac_conv03 rule reports different domain signals that converge after satisfying the following
conditions:

Signals are synchronized by using any of the following schemes:

Conventional Multi-Flop Synchronization Scheme


Synchronizing Cell Synchronization Scheme

Qualifier Synchronization Scheme

Signals from different source domains are synchronized in the same destination domain.

Synchronized signals converge before a sequential element on some net of the design.

Use the conv03_report_seq_conv parameter to enable reporting of convergences after sequential


elements.

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