Logic and Computer Design Fundamentals

Chapter 6 –Selected Design

Topics
Part 3 – Asynchronous Interactions

Charles Kime & Thomas Kaminski

© 2008 Pearson Education, Inc.
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Overview
 Part 1 – The Design Space
 Part 2 – Propagation Delay and Timing
 Part 3 – Asynchronous Interactions
• Types of Interactions
• Combinational Hazards
• Synchronization
• Metastability
• Synchronous Circuit Pitfalls
 Part 4 - Programmable Implementation
Technologies
Chapter 6 – Part 3 2
 Types of Interactions
 Differ by
• Source circuit type
• Destination circuit type
 Sequential circuit types
• Synchronous – time of state change determined by a clock
• Asynchronous – time of state change controlled by time of
input changes and combinational circuit delay
 Four possible pairings
• Asynchronous to Asynchronous
• Synchronous to Asynchronous
• Asynchronous to Synchronous
• Synchronous to Synchronous
Chapter 6 – Part 3 3
 Types of Interactions
 Asynchronous to Asynchronous – not of concern
since we are not covering general asynchronous
circuit design
 Synchronous to Asynchronous – synchronous
circuit outputs must be free of hazards
 Asynchronous to Synchronous – inputs must be
synchronized to synchronous circuit clock
 Synchronous to Synchronous
• Clocks synchronized with each other (including identical)
– normal clock timing constraints must be obeyed.
• Clocks not synchronized –inputs must be synchronized to
receiving synchronous circuit’s clock

Chapter 6 – Part 3 4
Types of Interactions

Synchronous Asynchronous
circuit circuit

(a ) Synchro n ous to async hrono us

Asynchronous Asynchrono us signals Sy nchronous

circuit circuit

( b) A synch ronous to syn chron ous

Synchron ous Asynchro nous signal s Synchron ou s

circuit circuit

Clock X Clock Y
(c) Synchro n ous circuit s with unre lated clo cks Chapter 6 – Part 3 5
Synchronous to Asynchronous
 Since the asynchronous circuit state changes in
response to input changes, there must be no “glitches”
in the outputs of the synchronous circuit.
 Such glitches can arise from:
• combinational output logic or
• input signals propagating through the synchronous circuit
 In order to avoid “glitches”
• the outputs of the synchronous circuit must be Moore outputs,
and
• The output logic driving the asynchronous circuit must be free
of combinational logic hazards
 Satisfying these two requirements is too complex for
consideration here and is covered in the reading
supplement Combinational Hazards.

Chapter 6 – Part 3 6
Remaining Interactions
 Includes asynchronous circuits to synchronous
circuits and synchronous circuits to
synchronous circuits with unsynchronized
clocks
 The problem: Input signal changes arrive at
flip-flop inputs during the setup time – hold
time interval.
 The solution:
• Synchronize input signals with the receiving circuit
clock
• Otherwise, guarantee that specific input signals will
not arrive at flip-flop inputs during the setup time –
hold time interval.
• We will focus on the first approach only.
Chapter 6 – Part 3 7
The Problem
 Changes in inputs to a synchronous
circuit arrive at inputs to two or more
circuit flip-flops during the setup-hold
time interval. (For simplicity, D flip-flops
are assumed.)
 When this occurs, the flip-flops may
respond differently, e.g., one flip-flop
may change its state and another may not
change its state, resulting in an incorrect
state.

Chapter 6 – Part 3 8
 Problem Example
 Both illustrations use the same
circuit

Chapter 6 – Part 3 9
 Problem Example
 Both illustrations use the same State State
circuit Variable
=1
 The circuit has three states and
uses a 1-hot state assignment: S0 y0
 The circuit interacts with S1 y1
its environment using two S2 y2
signals, Z and RDY. When the circuit enters
state S0, it signals to the environment with Z =
1. In response, the environment signals back
that it is ready to move to state S1 with
asynchronous input RDY = 1.
Chapter 6 – Part 3
Illustration 1 of the Problem
Clock

R DY

y0

y1

y2

(a) O ne correct circuit response to R DY: valid state (0, 1, 0) results.

Clock

R DY
y0 resets
y0
y1 fails to set
y1

y2
(b) Incorrect circuit response to R DY: invalid state (0, 0, 0) results and remains.

Chapter 6 – Part 3
 Illustration 2 of the Problem
Clock

R DY

y0

y1

y2

(a) O ne correct circuit response to R DY: valid state (0, 1, 0) results.

Clock

R DY

y0
y0 fails to reset
y1
y1 sets
y2

(c) Incorrect circuit response to R DY: invalid state sequence (1, 1, 0 ), (0, 1, 1), (1, 0, 1) results and repeats.

Chapter 6 – Part 3
Solution using Synchronizers
 Goal of solution: Preventing the
inconsistent response of two or more flip-
flops to the change in RDY by preventing
RDY from reaching the input of more the
one circuit flip-flop.
 Implementation: Place a D flip-flop in the
path from RDY to the circuit.

Chapter 6 – Part 3
Example Circuit with Synchronizer

R eset
S
D D D
y0 y1 y2
C C C
R R
Clock

R DY D
R DY_S
C
R
Synchronizer

Chapter 6 – Part 3
Circuit Behavior with Synchronizer
 Assumption 1: If RDY changes during setup-hold interval,
synchronizer either responds with corresponding change or not.
Clock

RDY
R D Y_S

y0

y1

y2
(a) Circuit response to R D Y with sensing at the Clock edge where R D Y changes

Clock

RDY
R D Y_S

y0

y1

y2
(b) Circuit response to R D Y with sensing at the next Clock edge where R D Y changes Chapter 6 – Part 3
Circuit Behavior with Synchronizer
 Assumption 2: If RDY change missed during setup-hold interval,
change will be captured at next clock edge.
Clock

RDY
R D Y_S

y0

y1

y2
(a) Circuit response to R D Y with sensing at the Clock edge where R D Y changes

Clock

RDY
R D Y_S

y0

y1

y2
(b) Circuit response to R D Y with sensing at the next Clock edge where R D Y changes Chapter 6 – Part 3
Circuit Behavior with Synchronizer
 Condition 1: In order to allow the previous pair of situations to
capture the changed value of RDY, the time interval at which
RDY retains its new value is constrained as follows:
tRDY > ts + tP + th
in which ts is the setup time, tP is the clock period and th is the hold
time.
 The time at which RDY is captured may differ by a clock cycle.
Since the timing of the asynchronous circuit signal RDY is
unknown with respect to the clock, the circuit must be designed to
work correctly within this capture variation, including capture
variation of multiple asynchronous inputs.

Chapter 6 – Part 3
Metastability
 Unfortunately, Assumption 1 given earlier is not
correct. The synchronizer does not respond to an input
change during the setup-hold interval by either
changing or not.
 If the change in RDY at the D input to the synchronizer
flip-flop occurs in a very small window within the
setup-hold time interval, then metastable behavior can
occur.
 The window width is of the order of 10 picoseconds
(pico = 10-12).

Chapter 6 – Part 3
Metastability Concept
 The concept of metastability can be illustrated by a mechanical
analogy
M

0 1

 In positions 0 and 1, the ball is stopped in a stable state. In position

M, the ball is stopped in a unstable state between 0 and 1 and
remains there until perturbed by, for example, the wind.
 The metastable state in a flip-flop latch can be attained by logical
ANDing of the RDY change close to a Clock change that produces a
very weak output pulse.
 Departure from the metastable state is produced by electronic
“noise” injected into the flip-flop latch

Chapter 6 – Part 3
Metastable Behavior
 Metastability lengthens the propagation delay to well
beyond normal.

30 ns
Clock 45 ns

13 ns

Chapter 6 – Part 3
Metastable Behavior Consequences

 If the clock period is short enough, due to the increase

in delay, the change in RDY_S may reach the D inputs
to the y0 and y1 flip-flops during the setup-hold
interval at the next positive edge and produce
inconsistent behavior.
 So, metastable behavior can reintroduce a failure in
spite of the presence of the synchronizer.

Chapter 6 – Part 3
Solution to Metastable Behavior
 Simple Solution: A Cascade of Synchronizers
• The metastable behavior delay of the first synchronizer is
encountered by the next synchronizer.
• Due to the narrow window, it is unlikely that the next synchronizer
also exhibits metastable behavior
• And so forth
 Clearly each added synchronizer lowers probability of
failure rather than absolutely eliminating failure
 Disadvantage: May slow response to asynchronous input
due to multiple clock cycles required for production of
final RDY_S.
 Typically, a cascade of three synchronizers in series lowers
probability adequately, but depends on clock period,
delays, etc.

Chapter 6 – Part 3
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Chapter 6 – Part 3