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Updated Computer Architecture Mids Questions

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10 views16 pages

Updated Computer Architecture Mids Questions

Uploaded by

gadgetsmonarch057
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ANSWER:

ANSWER:

(a) IR ← M[PC]
PC cannot provide address to memory. Address must be transferred to AR first

AR← PC
IR ← M[AR]
(b) AC ← AC + TR

Add operation must be done with DR. Transfer TR to DR first.

DR ← TR
AC ← AC + DR
(c) DR ← DR + AC

Result of addition is transferred to AC (not DR). To save value of AC its content must be stored temporary in
DR (or TR).

AC ← DR, DR ← AC (See answer to Problem 5.4(d))


AC ← AC + DR
wAC ← DR, DR ← AC
ANSWER
FIGURE 5.3
FIGURE 5.4
FIGURE 5.9

4-Bit Adder Code


module Four_bitadder(sum,carry,in1,in2,cin);
input [3:0] in1,in2;
input cin;
output [3:0] sum;
output carry;
wire [2:0] c;

full_adder f1(sum[0],c[0],in1[0],in2[0],cin);
full_adder f2(sum[1],c[1],in1[1],in2[1],c[0]);
full_adder f3(sum[2],c[2],in1[2],in2[2],c[1]);
full_adder f4(sum[3],carry,in1[3],in2[3],c[2]);
endmodule
--------------------------------------------------
module Four_bitadderdataflow(sum,carry,in1,in2,cin);
input [3:0] in1,in2;
input cin;
output [4:0] sum;
output carry;
//wire [2:0] c;

assign {carry,sum}=in1 + in2 + cin;


endmodule

4-BIT ADDER TEST BENCH


module TB_four_bitadder;
reg [3:0]in1,in2;
reg cin;
wire [4:0] sum;
wire carry;

Four_bitadderdataflow foutbA(sum,carry,in1,in2,cin);
initial
begin
in1=4'b0000; in2=4'b0000; cin=1'b0;
#5
in1=4'b0001; in2=4'b0000;
#5
in1=4'b0010; in2=4'b0000;
#5
in1=4'b0011; in2=4'b0000;
#5
in1=4'b0011; in2=4'b0011;
#5
in1=4'b0111; in2=4'b0111;
//#5
//in1=1'b1; in2=1'b0;
//#5
//in1=1'b0; in2=1'b1;
//#5
//in1=1'b1; in2=1'b1;
end
endmodule

COUNTER
module Counter( out, clk, reset, enable);

output reg[3:0] out;


input clk, reset, enable;
initial
begin
assign out = 4'b0000;
end

always@(posedge clk)
begin
if (enable == 1)
begin
if(reset == 1'b0)
assign out = out + 1;
else
assign out = 4'b0000;
end
end
endmodule

COUNTER TEST BENCH


module Counter_TB;
wire [3:0] out;
reg clk, reset, enable;
Counter count(out, clk, reset, enable);

initial
begin
clk = 1'b0;
reset = 1'b1;
enable = 1'b1;

#20
reset = 1'b1;
#30
reset = 1'b0;
#50
enable = 1'b0;
#60
enable = 1'b1;

end
always #5 clk = ~clk;
endmodule

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