East West University

Department of Electrical and Electronic Engineering

Adder and Subtractor construction

Submitted by
Palash Das
2023-1-80-016

Abstract
We will be able to create the combinational logic circuit in four distinct ways using this
experiment. Any combinational logic circuit can be simulated using Verilog or VHDL logic
simulation software. Four methods are available for simulating combinational logic circuits.
Modeling with themes, Behavioral simulation using a procedural model in Verilog, continuous
assign statement model-based behavioral Verilog simulation, and structural Verilog simulation at
the primitive gate level.

Date of Submission : 30th August, 2024

Date of Performance : 21th August, 2024
Course Instructor : Abdur Rahman

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Introduction
The simulation of combinational logic design is the focus of this lab. For this lab, Verilog or VHDL
software will be used. A hardware description language (HDL) called Verilog is used to describe
digital systems such as microprocessors, memory, flip-flops, and network switches. This implies
that we can describe any digital hardware at any level using an HDL. HDL-described designs are
technology-agnostic, incredibly simple to create and debug, and typically more helpful than
schematics—especially for big circuits.

Lab work

Figure 1: The Verilog code at primitive gate level

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 Figure 2: Verilog code using procedural model

Figure 3: Verilog code using continuous assign statement model

Comment: We are able to use the Verilog simulation for these kinds of commands in this lab.
A’B+AB’ was the Boolean expression. One OR gate and two AND gates are present. Three
different kinds of code are used to provide our Boolean expression with information. We utilize
code for Testbench as well. We indicated resistance and wire in the test bench. Next, we announced
the input and output. Next, we provide the order to start. Finally, we execute the commands “end”
and “endmodule” to finish our code. We wrote the code by declaring the gate name and number at
the basic gate level. Additionally, we defined input and output. “endmodule” was used to terminate
the code. To write the Verilog code, we went through this procedure.

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Report Questions

Answer the question no. 1

Here the Boolean expression is S = AʹB+AC+ABʹ.

Truth table:

A B C A’ B’ A’B AC AB’ S

0 0 0 1 1 0 0 0 0

0 0 1 1 1 0 0 0 0

0 1 0 1 0 1 0 0 1

0 1 1 1 0 1 0 0 1

1 0 0 0 1 0 0 1 1

1 0 1 0 1 0 1 1 1

1 1 0 0 0 0 0 0 0

1 1 1 0 0 0 0 0 1

Circuit Diagram:

Figure 4 : Circuit Diagram of the expression

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 Answer the question no. 2

(b) Structural Verilog simulation at primitive gate level:

Figure 5: Code for structural Verilog simulation at primitive gate level

Figure 6: The output of structural Verilog simulation at primitive gate level

(C) Behavioral Verilog simulation using Procedural model:

Figure 7: Code of Behavioral Verilog simulation using Procedural model

Figure 8: The output of Behavioral Verilog simulation using Procedural model.

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(d) Behavioral Verilog simulation using continuous assign statement model

Figure 9 : Code of Behavioral Verilog simulation using continuous assign state

10: The output of Behavioral Verilog simulation using continuous assign statement model

Answer the question 3

Having gleaned the truth table and shown the execution of all previously mentioned methods, it is
time to present the findings. In comparing the results attained by each method to that in the truth
table, it is striking that all are consistent. In the Verilog simulation that we conducted, the code
was derived from the Boolean function A’B + AC + AB’. This expression comprises three AND
gates and one OR gate. As regards the coding of these Boolean expressions in the EDA Playground
software, various gate level modeling can be employed including primitive gate level, procedural
model and continuous assign statement model. In the testbench, all the input codes are entered last.
We introduce resistances first, and wires, then the inputs and the outputs. Then we issue commands
in this particular order starting with the initial begin block, the commands are enclosed with end
and finally the module with the endmodule commands. At the primitive gate level, textual data is
entered in the styling by means of specifying the gate numbers and the names, the inputs and the
outputs are declared. This are also terminated with the ‘endmodule’ command. In the procedural
model, underlying concepts are implemented in the commands using ‘if’ function. The code is
executed and as a result a waveform indicating the Boolean function that was encoded in the code
is given out.

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Discussion of Results

In this particular lab, we are familiarizing ourselves with the application of the Verilog code in
designing and simulating multiple kinds of combinational logic circuits. Using these types of codes
we are able to simulate any combinational logic circuits. All thefour ways we can simulate these
logic circuits like schematic simulation, Structural Verilog simulation at primitive gate level,
Behavioral Verilog simulation using procedural model and Behavioral Verilog simulation using
Continuous Assign Statement model.

Conclusions

It has been determined that the EDA playground software enables efficient training of students
through simulating logic circuits. We have emulated logic circuits in three different techniques.
When S = A’B + AC + AB’ is used as the condition, we found that the output generated and the
output from the truth table were exactly the same. This was because utilizing the codes presented
made us face some hurdles. When corrective measures were employed, we attempted to complete
the experiment. In the end the result that we executed was fair. The Verilog simulation lab
enhanced our understanding of Concepts related to designing and testing digital circuits using The
HDL,Verilog language. This encouraged us to design and Simulate various other digital systems
including booveral combinational and sequential circuits, hence expanding our understanding of
digital system overall.

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