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Dbget cmds1

DBget command file

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bhanuprakash boddupalli
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62 views7 pages

Dbget cmds1

DBget command file

Uploaded by

bhanuprakash boddupalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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‘9128124, 222 PM Explore your design with these useful single-tine doGotscxpts in Innovus Explore your design with these useful single-line dbGet scripts in Innovus Problem What are some of the basic dbGet scripts to explore the design in Innovus? Solution You can use the following single-line dbGet scripts to explore various aspects of your design: + List all unplaced instances in the design dbGet [dbGet -p top.insts.p placed} .name all placed instances in the design dbGet [dbGet -p top. insts.pStatus placed] .name all fixed instances the design atus fixed) name dbGet [dbGet -p top. insts.p + List the metal layers on which the /O pins of the block reside dbGet top. term ns.al1Shapes.layer.name + List the non default rules (NDR) in the design dbGet head. vules.name + List the NDRs applied on a specified net dbGet [dbGet -p top.ners.name netName] .cule.name net names with specific max or min voltage dbGet [dbGet top.nets.maxVoltage value ~p) .nane dbGet [dbGet top.nets.minVoltage value -p).name + Get the placement status of an instance In: yName inst + To avoid splitting of a specified multibit flop, during multibit Optimization icMultipit tInstByName ] + To avoid merging of a specified multibi flop, during multibit Opti [dbGetInstByNane <£1o ame>] Mergemulti + Get the coordinates of a rectangular routing blockage dbGet top. fplan.r31kys shapes. rect + Get the coordinates of a rectilinear routing blockage op. fplan. r31kgs. shapes. *+ List all cell types used in the design p-insts.cell. Note: The "=" parameter filters out the duplicate objects. Get the size of block placement halos jet ~p2 top. insts.cell.subClass block*] .pHaloTep insts.cell.subClass block*] .pHaloBot ipsileupport.cadence.comlapex/ArtcleAtachmentPortaid=a 1 0d0000000nULIEAUBpageName=ActicleContent wr ‘9128124, 222 PM Explore your design with these usoulsingle-ine doGotscxpts in Innovus dbGet [dbGet -p2 top. insts.cell.subClass block*] .pHaloLeft dbGet [dbGet -p2 top. insts.cell.subClass block*) .pHaloRight + Get the size and top/bottom layers of block routing halos insts.cell.subClass insts.cell.subClass bl insts.cell.subClasa block* + Ensure all your tiehiltielo connections have tie cells (and are not connected to a rail instead) isTieHi 1 sTieLo 1 ‘The previous commands should return "0x0" if all connections have tie cells. If"1s" are returned, use the following commands to find the terms that still need a tie cell [dbGet -p top. insts.instTerms.isTie#i 1] .name [dbGet -p top.insts.in + Get all instTerm names that are tied to tieLo cells insts.cell.subClass -p [abGet -p2 to; instTezms net .allTerms.isInpu’ + Get the status of the design dbGet top. statusToPlaced dice: status. dbGet top. statusCiocksynthesized dbGet top. statusRoutea dbGet top. statusRCExtracted dbGet top. statusPowezAnalyzed List the layers used in a net dbGet [dbGet -p top.nets.name netName] .wire: ayer-name + Selecting Shield Nets of anet select_obj [dbget {ai Sehield name ].aW -nane Snet] .shieldNe ame §net ~p2. NOTE: Snet is the net for which you want to select the shield. $shicld_nane is the shield net name. + Find all instances of a certain cell type dbGet [abs ¢ -p2 top.insts.cell.name cel1Name] .name + Determine the si of a cell in the library, but not necessarily in the current design tCel1ByName cellName].size -p top.nets.isClock 1] .name Note: Before running the previous command, build a timing graph using the timebesign command, + Set all instances with a particular pattern in the name to fixed status [dbGet -p top.insts.name *clk*].pStatus fixed * Get top and bottom routing layers for a route_type dbGet [dbGet -p head. dbGet [ai uteTypes..n jet ~p head. routeTypes + Get database units ipsileupport.cadence.comlapex/ArtcleAtachmentPortaid=a 1 0d0000000nULIEAUBpageName=ActicleContent an ‘9128124, 222 PM Explore your design with these useful single-tine doGotscxpts in Innovus dbGet head. ébUnits + Get the manufacturing grid dbGet head.migGrid + Get physical only cells such as filler cell, end cap cell, and so on dbGet [dbGet -p top.insts.isPhysOnly 1) name + Report Dont Touch instances of the database: dbGet [abGet -p top. insts.dontTouch true] name + Report Dont Use cells in the Library: dbGet [dbGet -p Read. 1ibCells.dontuse 1] name + Report JTag elements: dbGet [abGet -p top.insts.isJtagElem 1] name + Report spare instances: Get [doGet ts.isSpareGate 1) .name + Filter all PG pins with direction bidi of a specific instance ¢ -p [dbGet -p top. inst: me instName] .pgCell Terms. inOutDir + Get PG pins connections of a specific instance proc getinstPGConnect ic set inst [dbget -p top.insts.name $c puts connection of instance Sc:" foreach PG? [dbget Sinst.pgCellverms.name] { puls "\tPin : SPG? --> Net: [dbget [dbeGTermet TermByName Sins ) + Get class and subClass of a cell dbGet [dbGetCel1ByName celiName] .b: dbGet. [dbGetCellByNane celiName] .s + Selecting all Macros/Blocks of a particular module (or Hierarchical instance) selectInst [dbGet [dbGet top.hInst.all?reeInsts.cell.baseClass block ~ p2l.name + Get all the sequential cells of a particular module selectModule — pes.shapes. rect) 0 op.hinst.hinstTerms.term.name - shapes. layer.num p].pins.al + Query max_cap for alist of cells set cellPtrList [dbGet -p head.allcells.name BUF*] oreach cellPtr $cellPerhist (puts "[dbGet $cellPtr.name] [db¥TermMaxCap [dbGet -p ScellPtr.terms.name termName) 1]"} + Find all instances with a specify property name "myProp" (string property type) and value "xyzz} dbGet -p top.insts.props {.name <= "my && value d value xyzzy: [dbGet ind non-clock ports in a design [dbGet -p [dbGet -p2 tor + To get information on all tech sites in the design dbGet head.sites.name dbGet hea dbTsTechsitevppon tom [dbGet head.sites.name -p] Identify and report ‘physical only’ types of cells (well tap, tie hilo, filler, endcapidecap) You can query the subclass for a cell to check whether itis welltap, tiehigh, tielow or end cap: dhGet [dbGet -p head.LibCells.subClass ) .name For example, to get names of well tap cells (specified as ‘CLASS CORE WELLTAP ‘in LEF), you can use the following command: dbGet [dbGet -p head.libCells.subClass coreWellTap] .name 1d as ‘CLASS CORE TIEHIGH' or ‘CLASS CORE, Similarly, to get names of tie high / tie low cells (spec TIELOW in LEF), use the following command: t -p head. libCells.subClass coreTielligh] .name dbGet [dbGet -p head.libCells.subClass coreTieLow! To report endcap cells (specified as ‘CLASS ENDCAP’ in LEF), use the following command dbGet [dbGet -p head. 1ibCells.subclass corefndCap*] .name Similarly, to query filler cells with ‘CLASS CORE SPACER ’in the LEF syntax, you can use the following ‘command (similar to other physical-only cells): dbGet [dbGet -p head. libCells.subClass coreSpacer] .name + Print all module names in the design treeHInsts.cell.name] { foreach module_nane This will not include the top module name. To get the top module name, run the following command: dbGet top-name ipsileupport.cadence.comlapex/ArtcleAtachmentPortaid=a 1 0d0000000nULIEAUBpageName=ActicleContent an ‘9128124, 222 PM Explore your design with these usoulsingle-ine doGotsexpts in Innovas + Get all leaf cells used in the design oreach leaf_name [dbGet insts.cell.name] { Puts “Sleaf, } + Apply set_dont_touch on selected instance Select the instances on which to apply set_dont_touch. For example, select all level-shifter instances with the "LS" prefix: dbGet top.insts.name LS* Then, run the following command: foreach term [dbGet selected set_dont_touch [dbGet $term.net.name] true ) + Skip routes hierarchical hard macro nets proc skiproutesOnimsNers {hmInstPattern deselectall selectInst *$hmInstPattern* dbset selected.hinst -nnets.net.skipRouting 1 deselectall ) + Removing nets over the Macros along with pitches and vias Incase some nets are routed over the Hard Macros, you can remove such nets along with pitches and vias using following command: foreach ¢ [dbGet [dbGet ts.cell.baseClass block] .name] -p top.insts. [dbGet $}.box ] -objType regul dbselectol dgue: $j.box ] within Block [dbget $}.name]" IGNAL puts "Deleting object at [d vselected -type Signal ) + Get the number of vias that are not power in a routed design sisPwrorGnd 0) .vi Liength [dbGet [dbGet -p top.ne + Break the DFM flow if metal fills are not added to design using run_pvs_metal_fill. Include following set of command to break the script if metal fll is not added to design puts aquot;Checking if run_pvs_metal_fill successfully inserted metal fi shapes 5_RESERVED] .sWires op.nets.name | jb has metal £111 - continuing...squot; 1 “puts équotdb has no metal set has_fill 0 £111 - stopping dfm run... 6 if {Shas fill <1) { break } else rest of of your scri + Report instance pin shape mask You can use TCL procedure below to report the mask(color) of the instance pin n layer) { [dbGet (dbGet or (inste proc pinc (! [regexp Slaye: name $instPin ~ ipsileupport.cadence.comlapex/ArtcleAtachmentPortaid=a 1 0d0000000nULIEAUBpageName=ActicleContent sr ‘9128124, 222 PM Explore your design with these useful single-tine doGotscxpts in Innovus p].cellYerm.pins.allshapes.layer.name]]} { Puts "SinstPin doesn't have pin shape on Slayer” } else { dbGet [dbGet [dbGet top.insts.instTerms.name $instPin - p].cellYerm.pins.allshapes.layer.name Slayer ~p2).shapes.mask , ) pinColor Ainst/e VIAI + Report latency of all memories in the design Following script prints the latency of all memories with cell name *RAM* and clock pin name *CLK. You can change *RAM" with cell name of the desired memories, or as per your design. sel _mem_pin [dbget [dbget lop. insts.cell.name *RAM* -p2].instTerms.aame *CLK] foreach i Smem_pin { puts "Si iget_property [get_pins $i] actual_latency _tate_rise_max]" ) + Report all flop instances with reset pin connected to the supply # Identify all flops with reset tied directly te the vss rail # report total count, and each instname and cellname to an # output file named ‘flop with tied rst.rpt' proc findRstPinsTiedToRail( VSS_name RSTport } { don't echo dGet, etc. to screen/log: setPreference CndLogMode 1 # output file name set ofile "flop with tied rst.rpe" set ecofp [ open Sofile w ] set cnt [llength [dbGet [dbGet [dbGet top.nets.name $VSS_name - p].instTerms.cellTerm.name §RSTport -p2 ].inst.name ]] set Insts [dbGet [dbGet [dbGet top.nets.name $VSS_name ~ p].instTerms.cellTerm.name $RSTport -p2 ].inst ] set ent2 [Llength Sinsts) puts Secofp "Total: Sent $cnt2" #foreach inst_ptr [dbGet [dbGet [dbGet top.nets.name §VSS_name - p].instTerms.cell?erm.name $RSTport -p2 ].inst ] foreach inst_ptr Sinsts ( set inst_name [dbGet Sinst_ptr.name] set cell ptr [dbInstCell $inst_ptr] set cell_name [dbGet $cell_ptr-nane] set rst_port [dbGet $inst_ptr.instTerms.cellTerm.name $RSTport -p2) set net” [abGet Srst_port.aet.name] puts Secofp name $cell_name , close Sec! ) + To get the status of a design: encounter> dbGet top.?? status* // reports the list of status at particular stage statusClockSynthesized: 0 statusGRouted: 0 statusIoPlaced: 1 statusPlaced: 1 statusPowerAnalyze statusRCExtracted: 0 1 statusRoute statusScanopte Example to check a particular valu nipsilsuppor.cadance.comlapen’ArtcleAttachmentPorta!?id=a Od0000000nULIEAUBpageName=ActiclaContent or ‘9128124, 222 PM Explore your design with these useful single-tine doGotscxpts in Innovus encounter> dbGet top.statusPlaced 1 // it shows design is placed Note: The Lop. statueClocksynthes ized flag is only for FE-CTS [se.cTsMode -engine ck] not for CCopt. + Create SDP(structured data path) groups of clock gates and flops: The following script will find the clock gates and the flops connected to the clk pin in the design and group them together using SdpGroup Script: set clock ¢ *elk -p2] foreach i Sclock_gates ## find clock net of the clock gate clock net [dbget $ Terms.name *clk 7 sdp_gzoup_name [string map (/ _} (join (dbget $i.name] " flops [dbget [dbget $clock_netsnet.instTerms.isInput 1 8 [abget ame *cge* -p2].instTe ipGroup -nane S$sdp_group_name ~alignByPinName clk ~inst $flops ) Note: Please use cell name and clock pins name(cge and clk used for example) as per the library specifications. Return to the top of the page ipsileupport.cadence.comlapex/ArtcleAtachmentPortaid=a 1 0d0000000nULIEAUBpageName=ActicleContent a"

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