6.

Innovus commands
Verify commands:

● clearDrc :clears all DRC markers in your Design.

●
● VerifyConnectivity :detects conditions such as opens,unconnected wires,pins,loops.
●
● createMarker:creates marker for violation in the database and imports DRC markers
generated by other software applications.
ex: createMarker –bbox {1 2 1 2} –tool calibre -type Metal1 createMarker -bbox { 468 63 483 65)
-layer Metal3

● LoadDRC :load the specified DRC violation marker file (loadDrc filename.drc)
●
● saveDrc :saves DRC violation marker in specified file(saveDrc filename.drc)
●
● Verify_drc :checks for drc violations and create vilation marker ex: verify_drc

verify_drc -layer_range{2 3}

● Verify_PG_short :checks power ground shorts between two geometries verify_PG_short

-area {0 0 1600 1600} -report shorts.rpt
●

:checks whether pre/post cap cells inserted

• verifyEndcap
correctly based on settings

:it checks width,spacing and internal geometry of

• verifyGeometry
objects and wiring between them

verifyMetalDensi
• :it verifies the metal density
ty

• verifyMetalDensity -layer M3
 verifyProcessAnt
• :verifyProcessAntenna -report test.antenna.rpt
enna

• verifyTieCell :Checks tie cell connections.

:Generates violation markers for missing well-tap

cells and for well-tap cells that do not meet the
• verifyWellTap
rule specified for thedistance between well-tap
cells.

Wire
Edit Commands

:editMove direction distance

• editMove
editMove x 0.4(moves vertical metal towards
right)

• editAddVia :editAddVia 550 675

above command adds via with origin at co-

•
ordinates 550,675

:editSelect -net VDD1 editSelectVia -net VDD1

• editChangeNet
editChangeNet -to VDD2

:editChangeVia -net VDD1 -area {x1 y1 x2 y2} -from

• editChangeVia
VIA_XX -to VIA_YY

• editDeslect :deselects wires

• editDeslectVia :deselects VIA

 :adds duplicate layer
• editDuplicate
editDuplicate -layer_horizantal M3 -layer_vertical
M4

:selects wires
• editslect
editSelect -layer {M1 M2}

●
● editStretch :editStretch {x|y} distance {high|low}
●
● editStretch y 8.5 (stretch vertical net upward from top)
Import and Export Commands

● restoreDesign :restoreDesign test.enc.dat.Top

●
● checkDesign :checks for missing or inconsistent library and design data at any stage of
design
●

• checkDesign -danglingNet

• checkDesign -floorplan

• checkDesign -netlist

• checkDesign -physicalLibrary

• checkDesign -timingLibrary
• loadDefFile|defin :loadDefFile my.def|defIn top.def

●
● loadLefFile :loadLefFile sampl.lef
●
● Defout :defOut -floorplan
●
● defOut -floorplan -unplaced topchip-sp.def
●
● saveDesign :saveDesign test.enc
●
● saveNetlist :saveNetlist mydesign_cts.v
●
● saveNetlist -phys output.v(it saves physical netlist)
●
● loadIoFile :loadIoFile mypinfile.io
●
● saveIoFile :saveIoFile mypinfile.io
●
● Streamout :streamOut filename.gds

Floorplan commands

• refineMacro :refineMacro -area x1 y1 x2 y2 -selected

:add_ndr -name default_2x_space -spacing

• add_ndr
{M1:M2 02}

• Add_via :add_via my_via1 -pt{100.1 200.5} -net vss

• addRoutingHalo :addRoutinghalo -block DTMF_INST/RAM

• addHaloToBlock :addHaloToBlock 10 20 10 20 xy_inst

• checckFplan :checkFplan -reportutil

:floorplan -b die_box io_box core_box -core

• Floorplan
margin by {io|die} left right bot top

• alignObject :alignObject -side left

• selectInst

• selectInstByCellName

• selectNet

• changeFloorplan :changeFloorplan -coreToBottom 200

:copies the selected placement or routing

blockages,use pasteObject
• copyObject
PasteObject -loc{x y}

:addEndcap -prefixpwrcap -precap abc

• addEndcap
-postcap xyz

• addWellTap :addWellTap -cell xyz welltap -cellinterval 50

 Powerplan
commands

:addRing-nets{VDD GND} -type

core_rings -center1

• addRing -layer{top metal6 bottom metal 6

right metal5 bottom metal5}

-width 10 -spacing 5

:addStripe -direction vertical

• addStripe
-nets{VDD GND} -width 10 -spacing 2

-layer Metal6 -start_offset 50 -settosetdistance 50

Miscellaneous

:addFiller -cell Fill16 Fill4 Fill2 -prefix fillers this

• addFiller command inserts fillercells instances for cells fill
16 fill4 fill 2.

• ccoptDesign

• clockDesign

• RouteDesign

• placeDesign
• deletehalofromBlock :deleteHalofromBlock cube32

: Adds either a single buffer or two inverters on

a net.
• ecoAddRepeater
ecoAddRepeater -net wire_I13 -relativeDistToSink 0.1 -cell
BUFX4

• addInst : Adds an instance and places it in the design.

• addInst -cell BUF1 -inst i1/i2 -loc 100 200

: Adds an antenna diode to a post-routed

design. Innovus places the diode as close as
possible to the specified pin.
• attachDiode
attachDiode -diodeCell D1 -pin i2 term2 -loc 500
600

: Upsizes or downsizes the specified instance based on

• ecoChangeCell the available footprint ecoChangeCell -inst Top_I18 –
upsize

: Incrementally places the unplaced standard

• ecoPlace cells. In a pre-mask flow, this command moves the
unplaced standard cells into the core area.

: Detects and fills notches, gaps, and holes, and

• fillNotch
corrects acute angle (45 degree) violation

• fix_multi_drivers : Fixes multi-drive issues by disconnecting driving

 ports that do not have a real driver.

: setMetalFill -layer METAL1 -windowSize 200

• addMetalFill
200 -windowStep 100 100

addMetalFill -layer METAL1 -area 100 200 300 400 -nets {VDD GND}