INPUT- OUTPUT ORGANIZATION

INPUT- OUTPUT INTERFACE

Interface is a special h/w components b/w CPU and peripherals to
synchronize and supervise the data transfer.
I/O interface provides a method of transferring information between internal
storage and external storage i/o devices.
Need for interface:
•Peripherals are electromechanical and electromagnetic devices. CPU
and memory are electronic devices.
•Data transfer rate of peripherals is slower than the transfer rate of
CPU.
•Data codes and formats differs.
•The operating modes differs.
 INPUT- OUTPUT INTERFACE
Functions of I/O Interface:
•Data conversion.
•Conversion between analog and digital, and vice-versa.
•Conversion between serial and parallel data formats.
•Synchronization.
•Matching of operating speed of CPU and other peripherals.
•Device selection.
•Selection of I/O device by CPU in a queue manner.
•It also decodes the address and controls received from the I/O bus,
interprets them for the peripheral, and provides signals for the
peripheral controller.
 INPUT- OUTPUT INTERFACE
I/O Bus and Interface Modules

I/O Bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard,
Magnetic Magnetic
Display Printer
Disk Tape
Terminal
 INPUT- OUTPUT INTERFACE
I/O Bus
I/O Bus and Interface Modules Data
Processor
Address
Control
I/O bus consists of:
Interface Interface Interface Interface
•Data lines.
•Address lines. Keyboard,
Magnetic Magnetic
Display Printer
Disk Tape
•Control lines. Terminal

Each peripheral device has associated with an interface unit.

Each peripheral has its own controller that operates the particular
electromechanical device.
Processor places a device address on the address lines, and at the same
time function code in the control lines.
When the interface detects its own address, it activates the path
between the bus lines and the device that it controls.
 INPUT- OUTPUT INTERFACE
I/O Bus and Interface Modules
The function code is referred as I/O Command.
Types of I/O Command:
•Control Command.
- Is issued to activate the peripheral and to inform it what to do
•Status Command.
- Used to test various status conditions in the interface and the peripheral.
•Output Data Command.
- Causes the interface to respond by transferring data from the bus to one
of its registers.
•Input Data Command.
- It makes the interface to receive an item of data from the peripheral and
places it in its buffer register.
 INPUT- OUTPUT INTERFACE
I/O Vs Memory Bus

Similar to I/O bus

Memory bus consists of:
•Data lines.
•Address lines.
•Read/Write Control lines.
Computer buses communicate with memory and I/O in three ways:
•2 separate buses (1 I/O bus, 1 memory bus).
•1 common bus (with separate control lines for I/O and for memory).
•1 common bus (with common control lines).
 INPUT- OUTPUT INTERFACE
Isolated Vs Memory-Mapped I/O

In case of 1 common bus with separate control lines,

•I/O read and I/O write control lines are enabled during I/O transfer.
•Memory read and memory write control lines are enabled during
memory transfer.
The above configuration is referred as “isolated I/O method” for assigning
addresses in a common bus.
Isolated I/O method isolates memory and I/O addresses.
 INPUT- OUTPUT INTERFACE
Isolated Vs Memory-Mapped I/O (Continued…)

In case of 1 common bus with common control lines, the configuration is
said to be “memory-mapped I/O”.
The Interface registers are treated as a part of the memory system.
Same instruction set is used to access both the interface registers and the
memory.
 ASYNCHRONOUS DATA TRANSFER

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 ASYNCHRONOUS DATA TRANSFER
Introduction

Internal operations in a digital system are synchronized by means of a clock

pulse.
Data transfer inside the internal register occur simultaneously during the
occurrence of the clock pulse.
If the registers in the interface share a common clock with the CPU
registers, the transfer between the two units is said to synchronous.
In contrast, if the two units uses its own private clock for internal registers,
they are said to asynchronous.
Asynchronous data transfer requires some control signals to be transmitted
to indicate the time at which data is being transmitted, and is achieved by
means of “strobe pulse” or “handshaking”.
 ASYNCHRONOUS DATA TRANSFER
Strobe Pulse

Strobe pulse supplied by one of the units indicates the other unit when the
transfer has to occur.
Strobe may be activated by either source or the destination unit.

Source Destination Source Destination

1. Place data on bus. 1. Enables strobe pulse.
2. Enable strobe pulse.

2. Place data on bus.

Fig. Source initiated 3. Transfers the content
data transfer Fig. Destination initiated
of the data bus into data transfer 3.Transfers the content
one of its registers. from the data bus.
4. Disables strobe pulse
4. Disables strobe pulse. 5. Remove data from
5. Remove data from the data bus.
the data bus.
 ASYNCHRONOUS DATA TRANSFER
Strobe Control

1011010 1011010
Source Data Bus Destination Source Data Bus Destination
Unit Unit Unit Unit
Strobe Strobe

Fig: Block diagram Fig: Block diagram

Valid Data Data Valid Data

Data

Strobe Strobe

Fig: Timing diagram Fig: Timing diagram

Fig: Source initiated strobe for data transfer Fig: Destination initiated strobe for data transfer
 ASYNCHRONOUS DATA TRANSFER
Handshaking

In strobe method, the source unit that initiates the transfer has no way of
knowing whether the destination unit has received the data from the data bus.
Similarly, the destination unit that initiates the transfer has no way of
knowing whether the source unit has placed the data on the bus.
Two-wired handshaking solve the above problem, and the principle is,
•One control line is used by the source unit to inform the destination unit
whether there are valid data in the bus.
•The other control line is used by the destination unit to inform the source
whether it can accept data.
 ASYNCHRONOUS DATA TRANSFER
Handshaking

1011010
Data Bus Fig: Source initiated transfer using
Source Destination handshaking
Data Valid
Unit Unit
Data Accepted
Sequence of events
Block diagram
Source Destination
Place data on bus.
Enable data valid
Data bus Valid Data

Accept data on bus.

Data valid Enable data accepted.

Data accepted Disable data valid.

Invalidate data on bus.
Timing diagram

Disable data accepted.

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 ASYNCHRONOUS DATA TRANSFER
Handshaking 1011010
Data Bus
Fig: Destination initiated transfer
using handshaking
Source Destination
Data Valid
Unit Unit
Ready for data
Block diagram
Source Destination Unit
Unit
Ready to accept data.
Enable ready for data.
Ready for data
Place data on bus.
Enable data valid Data valid

Accept data from bus. Data accepted Valid Data

Disable ready for data.
Timing diagram

Disable data valid.

Invalidate data on bus.
(initial state)
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 PRIORITY INTERRUPT

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 PRIORITY INTERRUPT
Introduction

Data transfer between the CPU and I/O device is initiated by the CPU.
The readiness of the I/O device can be determined from an interrupt signal.
All the I/O devices are able to originate the interrupt request.
Several I/O devices may request the interrupt simultaneously, and the task
of the system is to identify the source of the interrupt request and to decide
which device to service first.
A priority interrupt is a system that establishes a priority over the various
sources to determine which condition is to be serviced first when two or more
request arrive simultaneously.
 PRIORITY INTERRUPT
Introduction

Devices with high transfer rate such as magnetic disks are given high
priority.
Devices with low transfer rate such as keyboards are given low priority.
High priority devices are serviced first.
A polling procedure is used to identify the highest priority source by
software means.
The highest priority source is tested first, and if its interrupt signal is on,
control branches to a service routine for this resource.
Otherwise, the next lower priority source is tested, and so on.
Disadvantage of the above software method is, the time required to poll
them can exceed the time available to service the I/O device.
 PRIORITY INTERRUPT
Introduction

A hardware priority interrupt unit accepts interrupt requests from many

sources, determines which one of the incoming requests has the highest
priority, and issues an interrupt request to the computer.
Establishing the priority of simultaneous interrupts can be done by software
or hardware means.
The disadvantage of software method is that if there are many interrupts,
the time required to poll them can exceed the time available to service the I/O
device.
 PRIORITY INTERRUPT
Daisy-Chaining Priority
Processor Data Bus

VAD 1 VAD 2 VAD 3

To next
Device 1 Device 2 Device 3 device
1 1 0 0 0
PI PO PI PO PI PO

Interrupt Request
INT

INTACK
Interrupt Acknowledge

CPU

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 PRIORITY INTERRUPT
Daisy-Chaining Priority

Daisy-Chaining method consists of serial connection of all devices that

request an interrupt.
High priority device is placed in the first position, followed by lower-priority
devices and continues up to the lowest priority device.

Interrupt request line is Processor Data Bus

common to all devices.
VAD 1 VAD 2 VAD 3
Devices which request the To
Device 1 Device 2 Device 3 next
1 1 0 0 0
interrupt enables the “Interrupt PI PO PI PO PI PO device

request” line.
Interrupt Request INT

INTACK
Interrupt Acknowledge

CPU
 PRIORITY INTERRUPT
Daisy-Chaining Priority (Continued…)

The CPU responds to an interrupt request by enabling the “Interrupt

acknowledge” line.
The acknowledge signal is received by device 1 at its PI input.
The acknowledge signal passes on to the next device through the PO output
only if the device 1 is not requesting an interrupt.
Processor Data Bus
If device 1 has a pending
VAD 1 VAD 2 VAD 3

interrupt, it blocks the Device 1 Device 2 Device 3 next

To
1 1 0 0 0
acknowledge signal from the PI PO PI PO PI PO device

next device by placing a 0 in the Interrupt Request INT

PO output. INTACK
Interrupt Acknowledge

CPU
 PRIORITY INTERRUPT
Daisy-Chaining Priority (Continued…)

It then proceeds to insert its own interrupt vector address (VAD) into the
data bus for the CPU to use during the interrupt cycle.
Processor Data Bus

VAD 1 VAD 2 VAD 3

To next
Device 1 Device 2 Device 3 device
1 1 0 0 0
PI PO PI PO PI PO

Interrupt Request
INT

INTACK
Interrupt Acknowledge

CPU
 PRIORITY INTERRUPT
Parallel Priority Interrupt

Parallel priority interrupt method uses a register whose bits are set
separately by the interrupt signal from each device.
Priority is established according to the position of bits in the register.
A “Mask register” controls the status of each interrupt request.
The mask register can be programmed to disable lower-priority interrupt
while a higher-priority device is being serviced. It can also provide a facility
that allows a high-priority device to interrupt the CPU while a lower-priority
device is being serviced.
An interrupt is recognized only if its corresponding mask bit is set to 1 by the
program.
The priority encoder generates 2 bits of vector address, which is transferred
to the CPU.
 DIRECT MEMORY ACCESS (DMA)

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ogy
 DIRECT MEMORY ACCESS (DMA)
Introduction

Data transfer between the CPU and I/O device is initiated by the CPU.
The readiness of the I/O device can be determined from an interrupt signal.
All the I/O devices are able to originate the interrupt request.
Several I/O devices may request the interrupt simultaneously, and the task
of the system is to identify the source of the interrupt request and to decide
which device to service first.
A priority interrupt is a system that establishes a priority over the various
sources to determine which condition is to be serviced first when two or more
request arrive simultaneously.
 DIRECT MEMORY ACCESS (DMA)
Introduction

DBUS Address bus

Bus Request BR
ABUS Data bus
CPU
RD Read
Bus grant
BG WR Write