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CSE460_LabAssignment2_Summer24

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23 views3 pages

CSE460_LabAssignment2_Summer24

Uploaded by

SHAHED ABDULLAH
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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BRAC University

Department of Computer Science and Engineering

Semester: Summer 2024


Course Code: CSE460 Lab Assignment 2
Course Title: VLSI Design
Faculty: [YAR], [THL] Full Marks: 40

Submission Link: Deadline: 24 September, 2024


https://forms.gle/EXsTTHAMj9YH6g69A

1. 1. A finite state machine that has to generate z = 1 when the previous four values of input
w were 1001 or 1111; otherwise, z = 0. Overlapping input patters are allowed. The
machine also has a negative reset. An example of the desired behavior is

w : 0101 1110 0110 0111 11

z : 0000 0010 0100 0100 11


(a) Design the state diagram. Mark your reset states and transitions clearly. Is this 3
machine Mealy type or Moore type?
(b) Derive the assigned table and write the Verilog code to implement the following 4
FSM.
(c) Validate your answer with the appropriate input and output waveforms on a 3
timing diagram. Include all possible combinations of the input (w).

2. You have to design a vending machine in Quartus for two products (n=2) each cost 15 Tk.
User’s money, returned money by the machine, and product bought condition are
represented as cash_in (2-bit input), return (output), and buy (1-bit output), respectively.
The vending machine can only accept three inputs: Tk 0 (cash_in = 00), Tk 20 (cash_in =
01), and Tk 50 (cash_in = 10). Once an acceptable input is more than or equal to 2*15 Tk,
the machine generates an output (buy=1), returns to the initial state, and returns the change
(if required).
a) Draw the state diagram, assigned table, and state-assigned table 3

b) Write the Verilog code to implement the described device functionality. 3

c) Run the simulation, and verify your answer with the proper timing diagram. 4

3. Design a finite state machine that detects whether the input binary string is alternating
(i.e., 010101... or 101010...). The machine should output 1 if the input bits alternate, and
0 otherwise. The machine also has a positive Asynchronous Reset.
Example:

Input: 0101 0111 0110


Output: 0111 1100 1101

(a) Design the state diagram. Mark your reset states and transitions clearly. Is this 3
machine Mealy type or Moore type?

(b) Derive the assigned table and write the Verilog code to implement the 4
following FSM.

(c) Validate your answer with the appropriate input and output waveforms on a 3
timing diagram. Include all possible combinations of the input (w).
4. Design a Mealy machine that simulates detecting fraudulent transactions in a stream of credit
card transactions based on input categories:

• A: Low-value transaction.
• B: Medium-value transaction.
• C: High-value transaction.

The machine outputs 1 (fraud detected) if two consecutive high-value transactions (C) are
followed by a low-value transaction (A). Otherwise, it outputs 0.

Example:

• Input: B C C A B
• Output: 00010

(a) Design the state diagram. Mark your transitions clearly. 3

(b) Derive the assigned table and write the Verilog code to implement the following 4
FSM.

(c) Validate your answer with the appropriate input and output waveforms on a 3
timing diagram. Include all possible combinations of the input (w).

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