Appendix2 Instruction Encoding - Chapter
Appendix2 Instruction Encoding - Chapter
Instructions
The table in this appendix provides the different assembly language formats
of the instructions for the Intel 8086 processor discussed in this book. It also
provides machine language encoding information about the opcode and the
operands of these instructions.
In this table,
S imm8 is an 8-bit (or 1 byte) immediate data
S imm16 is a 16-bit (1 word) immediate data
S reg8 is an 8-bit (1 byte) register (that means register AL, AH,
BL, BH, CL, CH, DL or DH)
S reg16 is a 16-bit register which is not a segment register, the
flag register or register IP (that means register AX, BX, CX,
DX, SP, BP, SI, or DI)
S Sreg is a segment register (that means register CS, SS, ES, or
DS)
S mem8 is a byte memory location
S mem16 is a word memory location, and
S regcd is the 3-bit code of a register operand.
CBW 98 no
CWD 99 no
INT 3 CC no
JBE/JNA ShortOffset 76 no -
JCXZ ShortOffset E3 no -
JE/JZ ShortOffset 74 no -
JG/JNLE ShortOffset 7F no -
JGE/JNL ShortOffset 7D no -
JL/JNGE ShortOffset 7C no -
JLE/JNG ShortOffset 7E no -
JMP ShortOffset EB no -
JMP Offset E9 no -
JNBE/JA ShortOffset 77 no -
JNE/JNZ ShortOffset 75 no -
JNO ShortOffset 71 no -
JNP/JPO ShortOffset 7B no -
JNS ShortOffset 79 no -
JO ShortOffset 70 no -
JP/JPE ShortOffset 7A no -
JS ShortOffset 78 no -
LOOP ShortOffset E2 no -
LOOPNZ/LOOPNE ShortOffset E1 no -
LOOPZ/LOOPE ShortOffset E0 no -
RET C3 no
RET imm16 C2 no
RETF imm16 CA no
RETF CB no