UNIT 1

PART A
Implement the Boolean function F(A,B,C,) =Σm( 0,1,2,7)
Discuss NAND, NOR and X-NOR gates
Given 2 binary numbers, X = 1010100 and Y = 1000011. Find X –Y and Y – X using
2’s compliments.
Explain the need of Karnaugh Map.
Compare the usability of Multiplexer and Demultiplexer
State the importance of Combinational Circuits?
Compare the need of Encoder and Decoder.
Describe about shift register? Explain its types.
Define duality property
Write the applications of encoder and multiplexer
Implement the Boolean function using 8X1 MUX, F(A,B,C) = Σm (1,3,5,6)
Implement the function using G= Σm( 0,3) using 2:4 decoder.

PART B
K Map problems
Design a full adder and full subtractor and derive expression for sum, carry,
difference and borrow. Realize using gates
Identify the combinational circuit that is used to compare the relative magnitude of
two binary numbers. Construct the identified circuit for comparing 4-bit binary
numbers.
Identify the combinational circuit that is used to compare the relative magnitude of
two binary numbers. Construct the identified circuit for comparing 2 bit binary
numbers.
Model 16:1 MUX and justify with truth table.
Design a 1x16 de-multiplexer using combinational logic gates
Design a encoder and decoder using 3 selection lines

UNIT 2
PART A
Show how a JK flip flop is better than SR flip flop.
Draw the circuit diagram of SR FF and its working
Detail the edge triggering in FF?
Give the excitation table for JK and T FF
Difference between flipflop and latch
With reference to a JK FF, what is racing?
What is a shift register? List its types.
Distinguish the synchronous and asynchronous sequential circuits.
Why is State Reduction important?
Distinguish Moore and Mealy circuit.

PART B
Compare the operation of JK FF, SR FF, T-FF and D-FF with a neat diagram.
Implement T FF using D FF and JK FF using D Flip flop. Explain in detail.
A sequential circuit with two D Flip-Flops, A and B; two inputs, x and y; and one
output, z, is specified by the following next-state and output equations:
A(t+1) = x’y + xA
B(t+1) = x’B + xA
z=B
a) Draw the logic diagram of the circuit.
b) List the state table for the sequential circuit.
c) Draw the corresponding state diagram.
A sequential circuit with two D FF A & B, two inputs x and y and one output z is
specified with following next state and output equations A(t+1) = xy’+xB:
B(t+1)=xA+xB’: z=A
Draw the logic diagram, state table and state diagram
Elaborate on the shift register using SR flip flop
Design a sequence detector that detects a sequence of three or more consecutive ‘1’
s in a string of bits coming through an input line and produces an output whenever
the sequence is detected
Design a MOD-N Synchronous counter using T flip-flops. Write execution table and
state table.
Design a logic circuit diagram for 3-bit synchronous up-down counter
Design a 3 bit synchronous down counter using D flip flop
Design a sequence detector that detects a sequence of 011 an input line and
produces an output whenever the sequence is detected
Design a MOD -10 synchronous counter using D flip flop

UNIT 3
PART A
Draw the Von Neumann Architecture.
Compare memory location and memory address
Describe the operations of computer hardware?
List the eight great ideas invented by computer architecture?
Compare supercomputers and mainframe computers
Explain about the ALU and its working
Mention the registers used for communications between processor and main
memory.
Define instruction formats and their types.
List the types of operations which a computer’s instructions should be able to
perform.
Infer how register direct addressing is different from register indirect addressing.
What is Instruction Set Architecture?
Write about the process of machine instructions encoding.

PART B
Illustrate the Von Neumann Architecture in detail and how it differs from the Harvard
Architecture
Illustrate about the functional units of the digital computer.
Elaborate about the operation of the computer hardware.
Elaborate on the operands in the context of computer instructions, and what types of
operands are typically used?
Elaborate on your understanding about ISA.
Write any program and show the interaction between assembly and high-level
language
Elaborate the concept of instructions in computer architecture, their role in program
execution, and how instruction sequencing affects the flow of control within a
processor.
What are addressing modes? Explain the various addressing modes with examples
Model an example, describing the encoding of machine instructions.

UNIT 4
PART A

Define clock and clock cycles in the context of computer architecture and explain
their role in processor operations.
Give the difference between hardwired and microprogrammed control units.
List the methods to use to improve the system performance
Mention the different types of hazards that occur in pipeline.
Name the different stages used in pipelining process.
Differentiate between cache hit and Cache miss.
Write the CPU performance equation.
Define datapath.
What do you mean by data hazard?
Define and differentiate RISC and CISC architectures
Explain the different types of instruction formats used in computer architecture and
how each type influences the design and performance of a processor.
Discuss the concept of the power wall in the context of computer architecture, its
implications on processor performance

PART B
Prepare a comparative analysis between hardwired and microprogrammed control.
How to design a data path in a computer system, covering its components, data flow,
and interaction with the control unit and memory to execute instructions
Design a control unit for a hypothetical processor, detailing its components and
explaining how it coordinates the execution of instructions
With neat example explain about an instruction execution.
Explain the types of hazards with necessary diagrams.
Examine the available methods to handle data hazards in pipelined processors,
emphasizing techniques.
Design a microprogram control unit for a simple arithmetic processor and explain
how it executes an ADD instruction.
Apply the concept of pipelining to design a simple instruction sequence execution for
a RISC processor, and calculate the effective throughput.
Explain about the complications involved in pipelining multiple instructions.
Write about the pipelining organization followed by the data dependencies.

UNIT 5
PART A
Illustrate the need of cache memory.
Why are interrupt masks provided in any interrupt requests.
Draw the memory hierarchy in a typical computer system.
Differentiate between serial and parallel interface.
What is USB & SATA?
Define CPU execution time and list the types.
How DMA can improve I/O speed.
Enumerate the need to implement memory as hierarchy
Distinguish between memory mapped I/O and I/O mapped I/O. Memory mapped I/O
What is the necessary of virtual memory? State the advantages of virtual memory?
How cache memory is used to reduce the execution time
If computer A runs a program in 10 seconds and computer B runs the same program
in 15 seconds how much faster is A than B?

PART B
Give detail description about memory hierarchy and management.
Discuss about mapping and replacement techniques in detail.
Give detail description about Parallel and serial interface
How do interconnection standards enable seamless communication and integration
across diverse systems, and what are the key types and their significance in modern
technology?
Illustrate the functioning of the 8237 DMA controller, its role in direct memory access,
and how it improves data transfer efficiency between peripheral devices and memory
Describe the DMA controller in a computer system with a neat block diagram.
Explain it's operations.
Describe interrupt-based I/O and its role in improving the efficiency of input/output
operations in computer systems