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Question Bank UNIT 2 EDC (1)

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67 views8 pages

Question Bank UNIT 2 EDC (1)

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2300520310050
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INSTITUTE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

SUB NAME: EDC. YEAR : EC IIND YR

QUESTION BANK FACULTY : ER NARENDRA PAL

1.An amplifier operating from a single 15-V supply provides a 12-V peak-to-peak sine-wave signal to a 1- kΩ load and draws negligible input current from the signal source.
The dc current drawn from the 15-V supply is 8 mA. What is the power dissipated in the amplifier, and what is the amplifier efficiency? (1.11)

2. The output voltage of a voltage amplifier has been found to decrease by 20% when a load resistance of 1 kΩ is connected. What is the value of the amplifier output
resistance? (1.13)

3.An amplifier with an open-circuit voltage gain of +40 dB, an input resistance of 10 kΩ, and an output resistance of 1 kΩ is used to drive a 1- kΩ load. What is the value of
Avo? Find the value of the power gain in decibels (1.14)

4.Figure 1 depicts an amplifier composed of a cascade of three stages. The amplifier is fed by a signal source with a source resistance of 100 kΩ and delivers its output into a
load resistance of 100 Ω. The first stage has a relatively high input resistance and a modest gain factor of 10. The second stage has a higher gain factor but lower input
resistance. Finally, the last, or output, stage has unity gain but a low output resistance. We wish to evaluate the overall voltage gain, that is, vL/vs, the current gain, and the
power gain. (Ex 1.3)
5.What would the overall voltage gain of the cascade amplifier in Fig. 1 be without stage 3 (i.e., with the load resistance connected to the output of the second stage)?(1.15)

6. For the cascade amplifier of Fig. 1, let vs be 1 mV. Find vi1, vi2, vi3, and vL. (1.16)
7. (a) Model the three-stage amplifier of Fig. 1 (without the source and load), using the voltage amplifier model . What are the values of Ri, Avo, and Ro? (1.17)

(b) If RL varies in the range 10 Ω to 1000 Ω, find the corresponding range of the overall voltage gain, vo/vs.

Circuit model for the voltage amplifier.


8.With the emitter used as a common terminal between input and output, Fig. 1.19(b) shows a transistor amplifier known as a common-emitter or grounded-emitter circuit.
Derive an expression for the voltage gain vo/vs, and evaluate its magnitude for the case Rs = 5 kΩ, rπ = 2.5 kΩ, gm = 40 mA/V, ro = 100 kΩ, and RL = 5 kΩ. What would the
gain value be if the effect of ro were neglected?

9.Determine the following for the fixed-bias configuration of Fig (Ex 4.1)
a. IBQ and ICQ. b. VCEQ.
c. VB and VC. d. VBC.

10.Given the load line of Fig. 4.16 and the defined Q-point, determine the required values of VCC, RC, and RB for a fixed-bias configuration. (Ex 4.3)

11. For the emitter-bias network of Fig. determine: (Ex 4.4)

a. Ib .
b. IC.

c. VCE.

d. VC.

e. VE.

f. VB.

g. VBC.

12. Determine the dc bias voltage VCE and the current IC for the voltage- divider configuration of (Ex 4.8)

13. Given the network of Fig. 4.43 and the BJT characteristics of Fig. 4.44. (Ex 4.14)
a. Draw the load line for the network on the characteristics.

b. Determine the dc beta in the center region of the characteristics. Define the chosen point as the Q-point.
c. Using the dc beta calculated in part b, find the dc value of IB.

d. Find ICQ and ICEQ.

14. Determine the following for the network of Fig

a. IDQ and VGSQ. b. VD.


c. VS.
d. VDS.

e. VDG.

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