Super Sequencer with Margining Control

and Temperature Monitoring

Data Sheet ADM1062
FEATURES FUNCTIONAL BLOCK DIAGRAM
Complete supervisory and sequencing solution for up to DP DN REFIN REFOUT REFGND SDA SCL A1 A0

10 supplies ADM1062
10 supply fault detectors enable supervision of supplies to TEMP INTERNAL
VREF SMBus
SENSOR DIODE INTERFACE
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures

MUX
5 selectable input attenuators allow supervision of supplies to 12-BIT
EEPROM
SAR ADC
14.4 V on VH
CLOSED-LOOP
6 V on VP1 to VP4 (VPx) MARGINING SYSTEM

5 dual-function inputs, VX1 to VX5 (VXx) VX1

DUAL-
CONFIGURABLE PDO1
VX2 FUNCTION OUTPUT PDO2
High impedance input to supply fault detector with INPUTS DRIVERS PDO3
VX3
thresholds between 0.573 V and 1.375 V (LOGIC INPUTS (HV CAPABLE OF PDO4
VX4 OR PDO5
DRIVING GATES
General-purpose logic input SFDs) OF N-FET)
VX5 PDO6
SEQUENCING
10 programmable driver outputs, PDO1 to PDO10 (PDOx) ENGINE
VP1 CONFIGURABLE PDO7
Open-collector with external pull-up PROGRAMMABLE OUTPUT
VP2
RESET DRIVERS PDO8
Push/pull output, driven to VDDCAP or VPx VP3 GENERATORS
(LV CAPABLE PDO9
Open collector with weak pull-up to VDDCAP or VPx VP4 (SFDs) OF DRIVING
VH LOGIC SIGNALS) PDO10
Internally charge-pumped high drive for use with external
AGND PDOGND
N-FET (PDO1 to PDO6 only)
VOUT VOUT VOUT VOUT VOUT VOUT VDD
VDDCAP
Sequencing engine (SE) implements state machine control of DAC DAC DAC DAC DAC DAC ARBITRATOR

PDO outputs

04433-001
State changes conditional on input events DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 VCCP GND

Enables complex control of boards Figure 1.

Power-up and power-down sequence control
Fault event handling APPLICATIONS
Interrupt generation on warnings Central office systems
Watchdog function can be integrated in SE Servers/routers
Program software control of sequencing through SMBus Multivoltage system line cards
Complete voltage margining solution for 6 voltage rails DSP/FPGA supply sequencing
6 voltage output, 8-bit DACs (0.300 V to 1.551 V) allow voltage In-circuit testing of margined supplies
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages GENERAL DESCRIPTION
Internal and external temperature sensors The ADM1062 Super Sequencer® is a configurable supervisory/
Reference input (REFIN) has 2 input options
sequencing device that offers a single-chip solution for supply
Driven directly from 2.048 V (±0.25%) REFOUT pin
monitoring and sequencing in multiple-supply systems. In addition
More accurate external reference for improved
to these functions, the ADM1062 integrates a 12-bit ADC and six
ADC performance
8-bit voltage output DACs. These circuits can be used to implement
Device powered by the highest of VPx, VH for improved
a closed-loop margining system that enables supply adjustment
redundancy
by altering either the feedback node or the reference of a dc-to-dc
User EEPROM: 256 bytes
converter using the DAC outputs.
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V For more information about the ADM1062 register map, refer
Available in 40-lead, 6 mm × 6 mm LFCSP and to the AN-698 Application Note.
48-lead, 7 mm × 7 mm TQFP packages

Rev. D Document Feedback

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ADM1062 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Sequencing Engine Application Example ............................... 20
Functional Block Diagram .............................................................. 1 Fault and Status Reporting ........................................................ 21
Applications ....................................................................................... 1 Voltage Readback............................................................................ 22
General Description ......................................................................... 1 Supply Supervision with the ADC ........................................... 22
Revision History ............................................................................... 3 Supply Margining ........................................................................... 23
Detailed Block Diagram .................................................................. 4 Overview ..................................................................................... 23
Specifications..................................................................................... 5 Open-Loop Supply Margining ................................................. 23
Absolute Maximum Ratings............................................................ 8 Closed-Loop Supply Margining ............................................... 23
Thermal Resistance ...................................................................... 8 Writing to the DACs .................................................................. 24
ESD Caution .................................................................................. 8 Choosing the Size of the Attenuation Resistor ....................... 24
Pin Configurations and Function Descriptions ........................... 9 DAC Limiting and Other Safety Features ............................... 24
Typical Performance Characteristics ........................................... 11 Temperature Measurement System .............................................. 25
Powering the ADM1062 ................................................................ 14 Remote Temperature Measurement ........................................ 25
Slew Rate Consideration............................................................ 14 Applications Diagram .................................................................... 27
Inputs................................................................................................ 15 Communicating with the ADM1062 ........................................... 28
Supply Supervision ..................................................................... 15 Configuration Download at Power-Up ................................... 28
Programming the Supply Fault Detectors ............................... 15 Updating the Configuration ..................................................... 28
Input Comparator Hysteresis .................................................... 15 Updating the Sequencing Engine ............................................. 29
Input Glitch Filtering ................................................................. 16 Internal Registers........................................................................ 29
Supply Supervision with VXx Inputs ....................................... 16 EEPROM ..................................................................................... 29
VXx Pins as Digital Inputs ........................................................ 17 Serial Bus Interface..................................................................... 29
Outputs ............................................................................................ 18 SMBus Protocols for RAM and EEPROM .............................. 32
Supply Sequencing Through Configurable Output Drivers ....... 18 Write Operations ........................................................................ 32
Default Output Configuration .................................................. 18 Read Operations ......................................................................... 34
Sequencing Engine ......................................................................... 19 Outline Dimensions ....................................................................... 35
Overview...................................................................................... 19 Ordering Guide .......................................................................... 35
Warnings ...................................................................................... 19
SMBus Jump (Unconditional Jump) ........................................ 19

Rev. D | Page 2 of 35
Data Sheet ADM1062
REVISION HISTORY
1/15—Rev. C to Rev. D Changes to Table 11 ........................................................................ 24
Changed Round-Robin Circuit to Changes to Configuration Download at Power-Up Section ..... 26
ADC Round-Robin ....................................................... Throughout Changes to Table 12 ........................................................................ 27
Changes to Figure 4 and Table 4 ..................................................... 9 Changes to Figure 49 and Error Correction Section .................. 32
Added Slew Rate Consideration Section......................................14 Changes to Ordering Guide ........................................................... 34
Added VP1 Glitch Filtering Section .............................................16
Added SCL Held Low Timeout Section and False Start 12/06—Rev. 0 to Rev. A
Detection Section ............................................................................30 Updated Format ................................................................. Universal
Updated Outline Dimensions ........................................................35 Changes to Features .......................................................................... 1
Changes to Ordering Guide ...........................................................35 Changes to Figure 2 .......................................................................... 3
Changes to Table 1 ............................................................................ 4
6/11—Rev. B to Rev. C Changes to Table 2 ............................................................................ 7
Changes to Serial Bus Timing Parameter in Table 1 .................... 5 Changes to Absolute Maximum Ratings Section ......................... 9
Change to Figure 3 ............................................................................ 9 Changes to Programming the Supply Fault Detectors Section ... 14
Added Exposed Pad Notation to Outline Dimensions ..............34 Changes to Table 6 .......................................................................... 14
Changes to Ordering Guide ...........................................................35 Changes to Outputs Section .......................................................... 16
Changes to Fault Reporting Section ............................................. 20
5/08—Rev. A to Rev. B Changes to Table 9 .......................................................................... 21
Changes to Table 1 ............................................................................ 4 Changes to Identifying the ADM1062
Changes to Powering the ADM1062 Section ..............................13 on the SMBus Section ..................................................................... 28
Changes to Table 5 ..........................................................................14 Changes to Figure 39 and Figure 30 ............................................. 30
Changes to Sequence Detector Section ........................................18
Changes to Temperature Measurement System Section ............23 4/05—Revision 0: Initial Version

Rev. D | Page 3 of 35
ADM1062 Data Sheet
Supply margining can be performed with a minimum of external Temperature measurement is possible with the ADM1062. The
components. The margining loop can be used for in-circuit device contains one internal temperature sensor and a differen-
testing of a board during production (for example, to verify tial input for a remote thermal diode. Both are measured by the
board functionality at −5% of nominal supplies), or it can be 12-bit ADC.
used dynamically to accurately control the output voltage of The logical core of the device is a sequencing engine. This state-
a dc-to-dc converter. machine-based construction provides up to 63 different states.
The device also provides up to 10 programmable inputs for This design enables very flexible sequencing of the outputs,
monitoring undervoltage faults, overvoltage faults, or out-of- based on the condition of the inputs.
window faults on up to 10 supplies. In addition, 10 programmable The ADM1062 is controlled via configuration data that can be
outputs can be used as logic enables. Six of these programmable programmed into an EEPROM. The entire configuration can
outputs can also provide up to a 12 V output for driving the gate be programmed using an intuitive GUI-based software package
of an N-FET that can be placed in the path of a supply. provided by Analog Devices, Inc.

DETAILED BLOCK DIAGRAM

REFIN REFOUT

DP DN REFGND SDA SCL A1 A0

TEMP INTERNAL
SENSOR DIODE ADM1062 VREF SMBus
INTERFACE

OSC
12-BIT DEVICE
SAR ADC CONTROLLER
EEPROM

GPI SIGNAL CONFIGURABLE

CONDITIONING OUTPUT DRIVER PDO1
(HV)
VX1
SFD PDO2
VX2 PDO3
VX3 PDO4
VX4 PDO5

GPI SIGNAL
CONDITIONING CONFIGURABLE
OUTPUT DRIVER PDO6
SEQUENCING (HV)
VX5 ENGINE
SFD

SELECTABLE CONFIGURABLE
VP1 SFD OUTPUT DRIVER PDO7
ATTENUATOR
(LV)
VP2
VP3 PDO8
VP4 PDO9

SELECTABLE CONFIGURABLE
VH SFD OUTPUT DRIVER PDO10
ATTENUATOR
(LV)

AGND PDOGND
REG 5.25V VOUT VOUT
VDDCAP VDD CHARGE PUMP DAC DAC
ARBITRATOR
04433-002

GND VCCP DAC1 DAC2 DAC3 DAC4 DAC5 DAC6

Figure 2.

Rev. D | Page 4 of 35
Data Sheet ADM1062

SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPx 3.0 V Minimum supply required on one of the VH, VPx pins
VPx 6.0 V Maximum VDDCAP = 5.1 V, typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
CVDDCAP 10 μF Minimum recommended decoupling capacitance
POWER SUPPLY
Supply Current, IVH, IVPx 4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
Additional Currents
All PDO FET Drivers On 1 mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off
Current Available from VDDCAP 2 mA Maximum additional load that can be drawn from all
PDO pull-ups to VDDCAP
DAC Supply Currents 2.2 mA Six DACs on with 100 μA maximum load on each
ADC Supply Current 1 mA Running round-robin loop
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges
High Range 6 14.4 V
Midrange 2.5 6 V
VPx Pins
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges
Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error
VXx Pins
Input Impedance 1 MΩ
Detection Range
Ultralow Range 0.573 1.375 V No input attenuation error
Absolute Accuracy ±1 % VREF error + DAC nonlinearity + comparator offset error +
input attenuation error
Threshold Resolution 8 Bits
Digital Glitch Filter 0 μs Minimum programmable filter length
100 μs Maximum programmable filter length
ANALOG-TO-DIGITAL CONVERTER
Signal Range 0 VREFIN V The ADC can convert signals presented to the VH, VPx,
and VXx pins; VPx and VH input signals are attenuated
depending on the selected range; a signal at the pin
corresponding to the selected range is from 0.573 V to
1.375 V at the ADC input
Input Reference Voltage on REFIN Pin, VREFIN 2.048 V
Resolution 12 Bits
INL ±2.5 LSB Endpoint corrected, VREFIN = 2.048 V
Gain Error ±0.05 % VREFIN = 2.048 V

Rev. D | Page 5 of 35
ADM1062 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
Conversion Time 0.44 ms One conversion on one channel
84 ms All 12 channels selected, 16× averaging enabled
Offset Error ±2 LSB VREFIN = 2.048 V
Input Noise 0.25 LSB rms Direct input (no attenuator)
TEMPERATURE SENSOR2
Local Sensor Accuracy ±3 °C VDDCAP = 4.75 V
Local Sensor Supply Voltage Coefficient −1.7 °C/V
Remote Sensor Accuracy ±3 °C VDDCAP = 4.75 V
Remote Sensor Supply Voltage Coefficient −3 °C
Remote Sensor Current Source 200 μA High level
12 μA Low level
Temperature for Code 0x800 0 °C VDDCAP = 4.75 V
Temperature for Code 0xC00 128 °C VDDCAP = 4.75 V
Temperature Resolution per Code 0.125 °C
BUFFERED VOLTAGE OUTPUT DACs
Resolution 8 Bits
Code 0x80 Output Voltage Six DACs are individually selectable for centering on
one of four output voltage ranges
Range 1 0.592 0.6 0.603 V
Range 2 0.796 0.8 0.803 V
Range 3 0.996 1 1.003 V
Range 4 1.246 1.25 1.253 V
Output Voltage Range 601.25 mV Same range, independent of center point
LSB Step Size 2.36 mV
INL ±0.75 LSB Endpoint corrected
DNL ±0.4 LSB
Gain Error 1 %
Maximum Load Current (Source) 100 μA
Maximum Load Current (Sink) 100 μA
Maximum Load Capacitance 50 pF
Settling Time to 50 pF Load 2 μs
Load Regulation 2.5 mV Per mA
PSRR 60 dB DC
40 dB 100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current, IDACxMAX = −100 μA
+0.25 mV Sinking current, IDACxMAX = +100 μA
Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability
PSRR 60 dB DC
PROGRAMMABLE DRIVER OUTPUTS (PDOs)
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance 500 kΩ
VOH 11 12.5 14 V IOH = 0 μA
10.5 12 13.5 V IOH = 1 μA
IOUTAVG 20 μA 2 V < VOH < 7 V
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
VPU − 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA
VOL 0 0.50 V IOL = 20 mA

Rev. D | Page 6 of 35
Data Sheet ADM1062
Parameter Min Typ Max Unit Test Conditions/Comments
IOL3 20 mA Maximum sink current per PDOx pin
ISINK3 60 mA Maximum total sink for all PDOx pins
RPULL-UP 16 20 29 kΩ Internal pull-up
ISOURCE (VPx)3 2 mA Current load on any VPx pull-ups, that is, total source
current available through any number of PDOx pull-up
switches configured onto any one VPx pin
Three-State Output Leakage Current 10 μA VPDO = 14.4 V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 μA VIN = 5.5 V
Input Low Current, IIL 1 μA VIN = 0 V
Input Capacitance 5 pF
Programmable Pull-Down Current, IPULL-DOWN 20 μA VDDCAP = 4.75 V TA = 25°C if known logic state is required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, VOL3 0.4 V IOUT = −3.0 mA
SERIAL BUS TIMING4
Clock Frequency, fSCLK 400 kHz
Bus Free Time, tBUF 1.3 μs
Start Setup Time, tSU;STA 0.6 μs
Stop Setup Time, tSU;STO 0.6 μs
Start Hold Time, tHD;STA 0.6 μs
SCL Low Time, tLOW 1.3 μs
SCL High Time, tHIGH 0.6 μs
SCL, SDA Rise Time, tR 300 ns
SCL, SDA Fall Time, tF 300 ns
Data Setup Time, tSU;DAT 100 ns
Data Hold Time, tHD;DAT 5 ns
Input Low Current, IIL 1 μA VIN = 0 V
SEQUENCING ENGINE TIMING
State Change Time 10 μs
1
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2
All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.
3
Specification is not production tested but is supported by characterization data at initial product release.
4
Timing specifications are guaranteed by design and supported by characterization data.

Rev. D | Page 7 of 35
ADM1062 Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 2.
Parameter Rating θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Voltage on VH Pin 16 V
Voltage on VPx Pins 7V Table 3. Thermal Resistance
Voltage on VXx Pins −0.3 V to +6.5 V Package Type θJA Unit
Voltage on A0, A1 Pins −0.3 V to +7 V 40-Lead LFCSP 25 °C/W
Voltage on REFIN, REFOUT Pins 5V 48-Lead TQFP 50 °C/W
Voltage on VDDCAP, VCCP Pins 6.5 V
Voltage on PDOx Pins 16 V
Voltage on SDA, SCL Pins 7V ESD CAUTION
Voltage on GND, AGND, PDOGND, −0.3 V to +0.3 V
REFGND Pins
Voltage on DN, DP Pins −0.3 V to +5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, 215°C
Soldering Vapor Phase, 60 sec
ESD Rating, All Pins 2000 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This
is a stress rating only; functional operation of the product
at these or any other conditions above those indicated in
the operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.

Rev. D | Page 8 of 35
Data Sheet ADM1062

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PDOGND
VDDCAP

PDOGND
VDDCAP
VCCP
GND

SDA
SCL

VCCP
DN
DP

A1
A0

GND

SDA
SCL
NC

DN

NC
DP

A1
A0
40 39 38 37 36 35 34 33 32 31
48 47 46 45 44 43 42 41 40 39 38 37
VX1 1 30 PDO1
PIN 1 NC 1 36 NC
VX2 2 INDICATOR 29 PDO2 PIN 1
VX1 2 INDICATOR 35 PDO1
VX3 3 28 PDO3
VX2 3 34 PDO2
VX4 4 27 PDO4
VX3 4 33 PDO3
VX5 5 ADM1062 26 PDO5
TOP VIEW VX4 5 32 PDO4
VP1 6 (Not to Scale) 25 PDO6 ADM1062
VX5 6 31 PDO5
VP2 7 24 PDO7 TOP VIEW
VP1 7 30 PDO6
VP3 8 23 PDO8 (Not to Scale)
VP2 8 29 PDO7
VP4 9 22 PDO9 VP3 9 28 PDO8
VH 10 21 PDO10 VP4 10 27 PDO9
VH 11 26 PDO10
11 12 13 14 15 16 17 18 19 20
NC 12 25 NC
REFIN
REFGND

REFOUT
AGND

DAC1
DAC2
DAC3
DAC4
DAC5
DAC6

13 14 15 16 17 18 19 20 21 22 23 24

REFIN
REFGND

REFOUT
NC
AGND

NC
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
NOTES
1. THE LFCSP HAS AN EXPOSED PAD ON THE BOTTOM.
THIS PAD IS A NO CONNECT (NC). IF POSSIBLE, THIS
04433-003

04433-004
PAD SHOULD BE SOLDERED TO THE BOARD FOR NOTES
IMPROVED MECHANICAL STABILITY. 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 3. 40-Lead LFCSP Pin Configuration Figure 4. 48-Lead TQFP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.
40-Lead 48-Lead
LFCSP TQFP Mnemonic Description
1, 12, 13, NC No Connect. Do not connect to this pin.
24, 25, 36,
37, 48
1 to 5 2 to 6 VX1 to VX5 (VXx) High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
6 to 9 7 to 10 VP1 to VP4 (VPx) Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the
input attenuation on a potential divider connected to these pins, the output of which connects to
a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from1.25 V to 3.00 V, and
from 0.573 V
to 1.375 V.
10 11 VH High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the
input attenuation on a potential divider connected to this pin, the output of which connects
to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0
V.
11 14 AGND1 Ground Return for Input Attenuators.
12 15 REFGND1 Ground Return for On-Chip Reference Circuits.
13 16 REFIN Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.
The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.
14 17 REFOUT Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be
connected between this pin and REFGND. A 10 μF capacitor is recommended for this
purpose.
15 to 20 18 to 23 DAC1 to DAC6 Voltage Output DACs. These pins default to high impedance at power-up.
21 to 30 26 to 35 PDO10 to PDO1 Programmable Output Drivers.
31 38 PDOGND1 Ground Return for Output Drivers.
32 39 VCCP Central Charge Pump Voltage of 5.25 V. A reservoir capacitor must be connected between
this pin and GND. A 10 μF capacitor is recommended for this purpose.
33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 SCL SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
36 43 SDA SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.

Rev. D | Page 9 of 35
ADM1062 Data Sheet
Pin No.
40-Lead 48-Lead
LFCSP TQFP Mnemonic Description
37 44 DN External Temperature Sensor Cathode Connection.
38 45 DP External Temperature Sensor Anode Connection.
39 46 VDDCAP Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of
4.75 V. Note that the capacitor must be connected between this pin and GND. A 10 μF
capacitor is recommended for this purpose.
40 47 GND1 Supply Ground.
N/A2 EPAD Exposed Pad. The LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If
possible, this pad should be soldered to the board for improved mechanical stability.
1
In a typical application, all ground pins are connected together.
2
N/A is not applicable

Rev. D | Page 10 of 35
Data Sheet ADM1062

TYPICAL PERFORMANCE CHARACTERISTICS

6 180

160
5
140

4 120
VVDDCAP (V)

100

IVP1 (µA)
3
80

2 60

40
1
20

04433-053
04433-050
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
VVP1 (V) VVP1 (V)

Figure 5. VVDDCAP vs. VVP1 Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)

6 5.0

4.5
5
4.0

3.5
4
3.0
VVDDCAP (V)

IVH (mA)

3 2.5

2.0
2
1.5

1.0
1
04433-051

04433-054
0.5

0 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
VVH (V) VVH (V)

Figure 6. VVDDCAP vs. VVH Figure 9. IVH vs. VVH (VH as Supply)

5.0 350

4.5
300
4.0

3.5 250

3.0
200
IVP1 (mA)

IVH (µA)

2.5
150
2.0

1.5 100

1.0
50
04433-055
04433-052

0.5

0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
VVP1 (V) VVH (V)

Figure 7. IVP1 vs. VVP1 (VP1 as Supply) Figure 10. IVH vs. VVH (VH Not as Supply)

Rev. D | Page 11 of 35
ADM1062 Data Sheet
14 1.0

0.8
12
0.6
CHARGE-PUMPED V PDO1 (V)

10 0.4

0.2
8

DNL (LSB)
0
6
–0.2

4 –0.4

–0.6
2

04433-056

04433-066
–0.8

0 –1.0
0 2.5 5.0 7.5 10.0 12.5 15.0 0 1000 2000 3000 4000
ILOAD (µA) CODE

Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD Figure 14. DNL for ADC

5.0 1.0

4.5 0.8

4.0 0.6

3.5 0.4

3.0 0.2
VPDO1 (V)

INL (LSB)

VP1 = 5V
2.5 0
VP1 = 3V
2.0 –0.2

1.5 –0.4

1.0 –0.6
04433-057

04433-063
0.5 –0.8

0 –1.0
0 1 2 3 4 5 6 0 1000 2000 3000 4000
ILOAD (mA) CODE

Figure 12. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD Figure 15. INL for ADC

4.5 12000

4.0 9894
10000
3.5
VP1 = 5V
3.0 8000
HITS PER CODE
VPDO1 (V)

2.5
VP1 = 3V 6000
2.0

1.5 4000

1.0
2000
0.5
04433-058

04433-064

25 81
0 0
0 10 20 30 40 50 60 2047 2048 2049
ILOAD (µA) CODE

Figure 13. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD Figure 16. ADC Noise, Midcode Input, 10,000 Reads

Rev. D | Page 12 of 35
Data Sheet ADM1062
1.005

1.004

1.003

1.002

DAC OUTPUT
1.001
VP1 = 3.0V
1.000
VP1 = 4.75V
DAC 20kΩ
0.999
BUFFER
OUTPUT PROBE
47pF POINT 0.998

0.997

04433-065
0.996
1

04433-059
0.995
–40 –20 0 20 40 60 80 100

CH1 200mV M1.00µs CH1 756mV TEMPERATURE (C)

Figure 17. Transient Response of DAC Code Change into Typical Load Figure 19. DAC Output vs. Temperature

2.058

2.053

REFOUT (V) VP1 = 3.0V

2.048

DAC 100kΩ VP1 = 4.75V

BUFFER 1V
OUTPUT

PROBE 2.043
POINT

04433-061
1
04433-060

2.038
–40 –20 0 20 40 60 80 100
CH1 200mV M1.00µs CH1 944mV TEMPERATURE (C)

Figure 18. Transient Response of DAC to Turn-On from High-Z State Figure 20. REFOUT vs. Temperature

Rev. D | Page 13 of 35
ADM1062 Data Sheet

POWERING THE ADM1062

The ADM1062 is powered from the highest voltage input on either When two or more supplies are within 100 mV of each other,
the positive-only supply inputs (VPx) or the high voltage supply the supply that first takes control of VDD keeps control. For example,
input (VH). This technique offers improved redundancy because if VP1 is connected to a 3.3 V supply, VDD powers up to approxi-
the device is not dependent on any particular voltage rail to keep mately 3.1 V through VP1. If VP2 is then connected to another
it operational. The same pins are used for supply fault detection 3.3 V supply, VP1 still powers the device, unless VP2 goes 100 mV
(see the Supply Supervision section). A VDD arbitrator on the higher than VP1.
device chooses which supply to use. The arbitrator can be VDDCAP
VP1 IN OUT
considered an OR’ing of five low dropout regulators (LDOs) 4.75V
together. A supply comparator chooses the highest input to LDO
EN
provide the on-chip supply. There is minimal switching loss with
VP2 IN OUT
this architecture (~0.2 V), resulting in the ability to power the 4.75V
LDO
ADM1062 from a supply as low as 3.0 V. Note that the supply EN
on the VXx pins cannot be used to power the device. VP3 IN OUT
4.75V
An external capacitor to GND is required to decouple the on-chip LDO
EN
supply from noise. This capacitor should be connected to the
VP4 IN OUT
VDDCAP pin, as shown in Figure 21. The capacitor has another 4.75V
LDO
use during brownouts (momentary loss of power). Under these EN
conditions, when the input supply (VPx or VH) dips transiently INTERNAL
VH IN OUT DEVICE
below VDD, the synchronous rectifier switch immediately turns 4.75V SUPPLY
LDO
off so that it does not pull VDD down. The VDD capacitor can EN
then act as a reservoir to keep the device active until the next
highest supply takes over the powering of the device. A 10 μF SUPPLY
COMPARATOR
capacitor is recommended for this reservoir/decoupling function.

04433-022
The VH input pin can accommodate supplies up to 14.4 V, which
allows the ADM1062 to be powered using a 12 V backplane supply.
In cases where this 12 V supply is hot swapped, it is recommended Figure 21. VDD Arbitrator Operation
that the ADM1062 not be connected directly to the supply. Suitable SLEW RATE CONSIDERATION
precautions, such as the use of a hot swap controller, should be
When the ambient temperature of operation is less than
taken to protect the device from transients that could cause
approximately −20°C, and in the event of a power loss where all
damage during hot swap events.
supply inputs fail for less than a few hundreds of milliseconds
(for example, due to a system supply brownout), it is recommended
that the supply voltage recover with a ramp rate of at least
1.5 V/ms or less than 0.5 V/ms.

Rev. D | Page 14 of 35
Data Sheet ADM1062

INPUTS
SUPPLY SUPERVISION The threshold value required is given by
The ADM1062 has 10 programmable inputs. Five of these are VT = (VR × N)/255 + VB
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VPx (VP1 to VP4) by default. The other five where:
inputs are labeled VXx (VX1 to VX5) and have dual functionality. VT is the desired threshold voltage (undervoltage or overvoltage).
They can be used either as SFDs, with functionality similar to VH VR is the voltage range.
and VPx, or as CMOS-/TTL-compatible logic inputs to the device. N is the decimal value of the 8-bit code.
Therefore, the ADM1062 can have up to 10 analog inputs, VB is the bottom of the range.
a minimum of five analog inputs and five digital inputs, or Reversing the equation, the code for a desired threshold is given by
a combination thereof. If an input is used as an analog input, N = 255 × (VT − VB)/VR
it cannot be used as a digital input. Therefore, a configuration
requiring 10 analog inputs has no available digital inputs. Table 6 For example, if the user wants to set a 5 V overvoltage threshold
shows the details of each input. on VP1, the code to be programmed in the PS1OVTH register
(as discussed in the AN-698 Application Note) is given by
PROGRAMMING THE SUPPLY FAULT DETECTORS
N = 255 × (5 − 2.5)/3.5
The ADM1062 can have up to 10 SFDs on its 10 input channels.
Therefore, N = 182 (1011 0110 or 0xB6).
These highly programmable reset generators enable the supervision
of up to 10 supply voltages. The supplies can be as low as 0.573 V INPUT COMPARATOR HYSTERESIS
and as high as 14.4 V. The inputs can be configured to detect The UV and OV comparators shown in Figure 22 are always
an undervoltage fault (the input voltage drops below a prepro- monitoring VPx. To avoid chatter (multiple transitions when the
grammed value), an overvoltage fault (the input voltage rises input is very close to the set threshold level), these comparators
above a preprogrammed value), or an out-of-window fault (the have digitally programmable hysteresis. The hysteresis can be
input voltage is outside a preprogrammed range). The thresholds programmed up to the values shown in Table 6.
can be programmed to an 8-bit resolution in registers provided in
RANGE
the ADM1062. This translates to a voltage resolution that is SELECT
ULTRA
dependent on the range selected. LOW
OV
+ COMPARATOR
VPx
The resolution is given by –
VREF GLITCH FAULT
FILTER OUTPUT
Step Size = Threshold Range/255
+
Therefore, if the high range is selected on VH, the step size can LOW
–
be calculated as follows: MID
UV
COMPARATOR
FAULT TYPE
SELECT

04433-023
(14.4 V − 6.0 V)/255 = 32.9 mV
Table 5 lists the upper and lower limits of each available range, Figure 22. Supply Fault Detector Block
the bottom of each range (VB), and the range itself (VR).
The hysteresis is added after a supply voltage goes out of
Table 5. Voltage Range Limits tolerance. Therefore, the user can program the amount above
Voltage Range (V) VB (V) VR (V) the undervoltage threshold to which the input must rise before
0.573 to 1.375 0.573 0.802 an undervoltage fault is deasserted. Similarly, the user can program
1.25 to 3.00 1.25 1.75 the amount below the overvoltage threshold to which an input
2.5 to 6.0 2.5 3.5 must fall before an overvoltage fault is deasserted.
6.0 to 14.4 6.0 8.4

Table 6. Input Functions, Thresholds, and Ranges

Input Function Voltage Range (V) Maximum Hysteresis Voltage Resolution (mV) Glitch Filter (μs)
VH High Voltage Analog Input 2.5 to 6.0 425 mV 13.7 0 to 100
6.0 to 14.4 1.02 V 32.9 0 to 100
VPx Positive Analog Input 0.573 to 1.375 97.5 mV 3.14 0 to 100
1.25 to 3.00 212 mV 6.8 0 to 100
2.5 to 6.0 425 mV 13.7 0 to 100
VXx High-Z Analog Input 0.573 to 1.375 97.5 mV 3.14 0 to 100
Digital Input 0 to 5.0 N/A N/A 0 to 100

Rev. D | Page 15 of 35
ADM1062 Data Sheet
The hysteresis value is given by VP1 Glitch Filtering
VHYST = VR × NTHRESH/255 If the ADC round-robin is used, it is recommended to enable
glitch filtering on VP1 because the ADC input mux is connected
where:
VHYST is the desired hysteresis voltage. to VP1 when the ADC round-robin stops. When the ADC
round-robin stops, a small internal glitch on the VP1 monitor
NTHRESH is the decimal value of the 5-bit hysteresis code.
rail occurs, and if the rail is close to the UV threshold, it may be
Note that NTHRESH has a maximum value of 31. The maximum enough to trip the VP1 UV comparator. Use any value of glitch
hysteresis for the ranges is listed in Table 6. filter greater than 0 μs to avoid false UV triggers. For more
INPUT GLITCH FILTERING information about the ADC round-robin, see the Voltage
Readback section.
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators, SUPPLY SUPERVISION WITH VXx INPUTS
which allows the user to remove any spurious transitions, such The VXx inputs have two functions. They can be used as either
as supply bounce at turn-on. The glitch filter function is in addition supply fault detectors or digital logic inputs. When selected as
to the digitally programmable hysteresis of the SFD comparators. analog (SFD) inputs, the VXx pins have functionality that is
The glitch filter timeout is programmable up to 100 μs. very similar to the VH and VPx pins. The primary difference is
For example, when the glitch filter timeout is 100 μs, any pulse that the VXx pins have only one input range: 0.573 V to 1.375 V.
appearing on the input of the glitch filter block that is less than Therefore, these inputs can directly supervise only the very low
100 μs in duration is prevented from appearing on the output of supplies. However, the input impedance of the VXx pins is high,
the glitch filter block. Any input pulse that is longer than 100 μs allowing an external resistor divide network to be connected to the
appears on the output of the glitch filter block. The output is pin. Thus, potentially any supply can be divided down into the
delayed with respect to the input by 100 μs. The filtering input range of the VXx pin and supervised, enabling the ADM1062
process is shown in Figure 23. to monitor other supplies, such as +24 V, +48 V, and −5 V.
INPUT PULSE SHORTER INPUT PULSE LONGER An additional supply supervision function is available when the
THAN GLITCH FILTER TIMEOUT THAN GLITCH FILTER TIMEOUT
VXx pins are selected as digital inputs. In this case, the analog
PROGRAMMED PROGRAMMED
TIMEOUT TIMEOUT function is available as a second detector on each of the dedi-
cated analog inputs, VPx and VH. The analog function of VX1
is mapped to VP1, VX2 is mapped to VP2, and so on; VX5 is
INPUT INPUT mapped to VH. In this case, these SFDs can be viewed as secondary
or warning SFDs.

t0 tGF t0 tGF The secondary SFDs are fixed to the same input range as the
primary SFDs. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be gener-
ated on a single supply using only one pin. For example, if VP1
is set to output a fault when a 3.3 V supply drops to 3.0 V, VX1
OUTPUT OUTPUT can be set to output a warning at 3.1 V. Warning outputs are
available for readback from the status registers. They are also
04433-024

t0 tGF t0 tGF OR’ed together and fed into the SE, allowing warnings to generate
Figure 23. Input Glitch Filter Function interrupts on the PDOs. Therefore, in this example, if the
supply drops to 3.1 V, a warning is generated and remedial
action can be taken before the supply drops out of tolerance.

Rev. D | Page 16 of 35
Data Sheet ADM1062
VXx PINS AS DIGITAL INPUTS The digital blocks feature the same glitch filter function that is
As discussed in the Supply Supervision with VXx Inputs section, available on the SFDs. This function enables the user to ignore
the VXx input pins on the ADM1062 have dual functionality. The spurious transitions on the inputs. For example, the filter can be
second function is as a digital logic input to the device. Therefore, used to debounce a manual reset switch.
the ADM1062 can be configured for up to five digital inputs. These When configured as digital inputs, each VXx pin has a weak
inputs are TTL-/CMOS-compatible. Standard logic signals can be (10 μA) pull-down current source available for placing the input
applied to the pins: RESET from reset generators, PWRGD signals, into a known condition, even if left floating. The current source,
fault flags, manual resets, and so on. These signals are available if selected, weakly pulls the input to GND.
as inputs to the SE and, therefore, can be used to control the status
VXx
of the PDOs. The inputs can be configured to detect either a change (DIGITAL INPUT) +
TO
GLITCH
in level or an edge. DETECTOR FILTER
SEQUENCING
ENGINE
When configured for level detection, the output of the digital –

block is a buffered version of the input. When configured for

04433-027
edge detection, a pulse of programmable width is output from VREF = 1.4V
the digital block once the logic transition is detected. The width
Figure 24. VXx Digital Input Function
is programmable from 0 μs to 100 μs.

Rev. D | Page 17 of 35
ADM1062 Data Sheet

OUTPUTS
SUPPLY SEQUENCING THROUGH The data driving each of the PDOs can come from one of three
CONFIGURABLE OUTPUT DRIVERS sources. The source can be enabled in the PDOxCFG configuration
register (see the AN-698 Application Note for details).
Supply sequencing is achieved with the ADM1062 using the
programmable driver outputs (PDOs) on the device as control The data sources are as follows:
signals for supplies. The output drivers can be used as logic  Output from the SE.
enables or as FET drivers.  Directly from the SMBus. A PDO can be configured so that
The sequence in which the PDOs are asserted (and, therefore, the SMBus has direct control over it. This enables software
the supplies are turned on) is controlled by the sequencing engine control of the PDOs. Therefore, a microcontroller can be used
(SE). The SE determines what action is taken with the PDOs, to initiate a software power-up/power-down sequence.
based on the condition of the ADM1062 inputs. Therefore, the  On-chip clock. A 100 kHz clock is generated on the device.
PDOs can be set up to assert when the SFDs are in tolerance, This clock can be made available on any of the PDOs. It can be
the correct input signals are received on the VXx digital pins, used, for example, to clock an external device such as an LED.
no warnings are received from any of the inputs of the device,
and at other times. The PDOs can be used for a variety of func- DEFAULT OUTPUT CONFIGURATION
tions. The primary function is to provide enable signals for LDOs All of the internal registers in an unprogrammed ADM1062
or dc-to-dc converters that generate supplies locally on a board. device from the factory are set to 0. Because of this, the PDOx pins
The PDOs can also be used to provide a PWRGD signal, when are pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.
all the SFDs are in tolerance, or a RESET output if one of the As the input supply to the ADM1062 ramps up on VPx or VH,
SFDs goes out of specification (this can be used as a status signal all the PDOx pins behave as follows:
for a DSP, FPGA, or other microcontroller).
 Input supply = 0 V to 1.2 V. The PDOs are high impedance.
The PDOs can be programmed to pull up to a number of differ-
 Input supply = 1.2 V to 2.7 V. The PDOs are pulled to GND
ent options. The outputs can be programmed as follows:
by a weak (20 kΩ) on-chip pull-down resistor.
 Open-drain (allowing the user to connect an external  Supply > 2.7 V. Factory-programmed devices continue to
pull-up resistor). pull all PDOs to GND by a weak (20 kΩ) on-chip pull-down
 Open-drain with weak pull-up to VDD. resistor. Programmed devices download current EEPROM
 Open-drain with strong pull-up to VDD. configuration data, and the programmed setup is latched. The
 Open-drain with weak pull-up to VPx. PDO then goes to the state demanded by the configuration.
 Open-drain with strong pull-up to VPx. This provides a known condition for the PDOs during
 Strong pull-down to GND. power-up.
 Internally charge-pumped high drive (12 V, PDO1 to The internal pull-down can be overdriven with an external pull-up
PDO6 only). of suitable value tied from the PDOx pin to the required pull-up
voltage. The 20 kΩ resistor must be accounted for in calculating
The last option (available only on PDO1 to PDO6) allows the
a suitable value. For example, if PDOx must be pulled up to 3.3 V,
user to directly drive a voltage high enough to fully enhance an
and 5 V is available as an external supply, the pull-up resistor value
external N-FET, which is used to isolate, for example, a card-
is given by
side voltage from a backplane supply (a PDO can sustain greater
than 10.5 V into a 1 μA load). The pull-down switches can also 3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
be used to drive status LEDs directly. Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ
VFET (PDO1 TO PDO6 ONLY)
VDD
VP4
SEL VP1
CFG4 CFG5 CFG6
20kΩ

20kΩ

20kΩ
10Ω

10Ω

10Ω

SE DATA

SMBus DATA PDO

CLK DATA
20kΩ

04433-028

Figure 25. Programmable Driver Output

Rev. D | Page 18 of 35
Data Sheet ADM1062

SEQUENCING ENGINE
OVERVIEW
MONITOR
The ADM1062 sequencing engine (SE) provides the user with FAULT STATE
TIMEOUT
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex

04433-029
control of boards, including power-up and power-down sequence SEQUENCE

control, fault event handling, and interrupt generation on warnings.

A watchdog function that verifies the continued operation of a Figure 26. State Cell
processor clock can be integrated into the SE program. The SE The ADM1062 offers up to 63 state definitions. The signals
can also be controlled via the SMBus, giving software or firmware monitored to indicate the status of the input pins are the
control of the board sequencing. outputs of the SFDs.
The SE state machine comprises 63 state cells. Each state has the WARNINGS
following attributes:
The SE also monitors warnings. These warnings can be generated
 Monitors signals indicating the status of the 10 input pins, when the ADC readings violate their limit register value or when
VP1 to VP4, VH, and VX1 to VX5. the secondary voltage monitors on VPx and VH are triggered.
 Can be entered from any other state. The warnings are OR’ed together and are available as a single
 Three exit routes move the state machine onto the next state: warning input to each of the three blocks that enable exiting
sequence detection, fault monitoring, and timeout. a state.
 Delay timers for the sequence and timeout blocks can be SMBus JUMP (UNCONDITIONAL JUMP)
programmed independently and changed with each state
The SE can be forced to advance to the next state uncondition-
change. The range of timeouts is from 0 ms to 400 ms.
ally. This enables the user to force the SE to advance. Examples
 Output condition of the 10 PDO pins is defined and fixed
of the use of this feature include moving to a margining state or
within a state.
debugging a sequence. The SMBus jump or go-to command can
 Transition from one state to the next is made in less than
be seen as another input to sequence and timeout blocks to
20 μs, which is the time needed to download a state
provide an exit from each state.
definition from EEPROM to the SE.

Table 7. Sample Sequence State Entries

State Sequence Timeout Monitor
IDLE1 If VX1 is low, go to State IDLE2.
IDLE2 If VP1 is okay, go to State EN3V3.
EN3V3 If VP2 is okay, go to State EN2V5. If VP2 is not okay after 10 ms, If VP1 is not okay, go to State IDLE1.
go to State DIS3V3.
DIS3V3 If VX1 is high, go to State IDLE1.
EN2V5 If VP3 is okay, go to State PWRGD. If VP3 is not okay after 20 ms, If VP1 or VP2 is not okay, go to State FSEL2.
go to State DIS2V5.
DIS2V5 If VX1 is high, go to State IDLE1.
FSEL1 If VP3 is not okay, go to State DIS2V5. If VP1 or VP2 is not okay, go to State FSEL2.
FSEL2 If VP2 is not okay, go to State DIS3V3. If VP1 is not okay, go to State IDLE1.
PWRGD If VX1 is high, go to State DIS2V5. If VP1, VP2, or VP3 is not okay, go to State FSEL1.

Rev. D | Page 19 of 35
ADM1062 Data Sheet
SEQUENCING ENGINE APPLICATION EXAMPLE If a timer delay is specified, the input to the sequence detector
The application in this section demonstrates operation of the must remain in the defined state for the duration of the timer
SE. Figure 28 shows how the simple building block of a single delay. If the input changes state during the delay, the timer is reset.
SE state can be used to build a power-up sequence for a three- The sequence detector can also help to identify monitoring faults.
supply system. Table 8 lists the PDO outputs for each state in the In the sample application shown in Figure 28, the FSEL1 and
same SE implementation. In this system, a good 5 V supply on the FSEL2 states first identify which of the VP1, VP2, or VP3 pins
VP1 pin and the VX1 pin held low are the triggers required to start has faulted, and then they take appropriate action.
a power-up sequence. The sequence next turns on the 3.3 V supply,
then the 2.5 V supply (assuming successful turn-on of the 3.3 V
SEQUENCE
supply). When all three supplies are have turned on correctly, the STATES
PWRGD state is entered, where the SE remains until a fault occurs
on one of the three supplies, or until it is instructed to go through
a power-down sequence by VX1 going high. IDLE1

Faults are dealt with throughout the power-up sequence on VX1 = 0

a case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
IDLE2
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 28 to demon-
VP1 = 1
strate the actions of the state machine. MONITOR FAULT TIMEOUT
STATES STATES

Sequence Detector
EN3V3
10ms
The sequence detector block is used to detect when a step in a VP1 = 0

sequence has been completed. It looks for one of the SE inputs

VP2 = 1
to change state and is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer EN2V5 DIS3V3
block that is included in this detector can insert delays into a (VP1 + VP2) = 0
20ms

VX1 = 1
power-up or power-down sequence, if required. Timer delays
VP3 = 1
can be set from 10 μs to 400 ms. Figure 27 is a block diagram of
the sequence detector. PWRGD DIS2V5
VP2 = 0
(VP1 + VP2 + VP3) = 0
SUPPLY FAULT
VP1 DETECTION VX1 = 1
SEQUENCE
DETECTOR VX1 = 1
FSEL1
(VP1 +
VP2) = 0
LOGIC INPUT CHANGE VP3 = 0
VX5 OR FAULT DETECTION
TIMER FSEL2
VP1 = 0
WARNINGS
VP2 = 0
INVERT

04433-030
FORCE FLOW
(UNCONDITIONAL JUMP)
04433-032

SELECT Figure 28. Sample Application Flow Diagram

Figure 27. Sequence Detector Block Diagram

Table 8. PDO Outputs for Each State

PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2
PDO1 = 3V3ON 0 0 1 1 0 1 1 1 1
PDO2 = 2V5ON 0 0 0 1 1 0 1 1 1
PDO3 = FAULT 0 0 0 0 1 1 0 1 1

Rev. D | Page 20 of 35
Data Sheet ADM1062
Monitoring Fault Detector Timeout Detector
The monitoring fault detector block is used to detect a failure on an The timeout detector allows the user to trap a failure to ensure
input. The logical function implementing this is a wide OR gate proper progress through a power-up or power-down sequence.
that can detect when an input deviates from its expected condition. In the sample application shown in Figure 28, the timeout next-
The clearest demonstration of the use of this block is in the state transition is from the EN3V3 and EN2V5 states. For the
PWRGD state, where the monitor block indicates that a failure EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
on one or more of the VP1, VP2, or VP3 inputs has occurred. pin upon entry to this state to turn on a 3.3 V supply. This supply
No programmable delay is available in this block because the rail is connected to the VP2 pin, and the sequence detector looks
triggering of a fault condition is likely to be caused by a supply for the VP2 pin to go above its undervoltage threshold, which is
falling out of tolerance. In this situation, the device needs to set in the supply fault detector (SFD) attached to that pin.
react as quickly as possible. The power-up sequence progresses when this change is detected.
Some latency occurs when moving out of this state because it If, however, the supply fails (perhaps due to a short circuit over-
takes a finite amount of time (~20 μs) for the state configuration loading this supply), the timeout block traps the problem. In this
to download from the EEPROM into the SE. Figure 29 is a block example, if the 3.3 V supply fails within 10 ms, the SE moves to
diagram of the monitoring fault detector. the DIS3V3 state and turns off this supply by bringing PDO1
MONITORING FAULT low. It also indicates that a fault has occurred by taking PDO3
DETECTOR
high. Timeout delays of 100 μs to 400 ms can be programmed.
1-BIT FAULT
DETECTOR FAULT AND STATUS REPORTING
SUPPLY FAULT FAULT
VP1 DETECTION The ADM1062 has a fault latch for recording faults. Two registers,
FSTAT1 and FSTAT2, are set aside for this purpose. A single bit
MASK
SENSE is assigned to each input of the device, and a fault on that input
sets the relevant bit. The contents of the fault register can be
read out over the SMBus to determine which input(s) faulted.
1-BIT FAULT
DETECTOR The fault register can be enabled or disabled in each state. To
VX5
LOGIC INPUT CHANGE FAULT latch data from one state, ensure that the fault latch is disabled
OR FAULT DETECTION
in the following state. This ensures that only real faults are
MASK
SENSE
captured and not, for example, undervoltage conditions that
may be present during a power-up or power-down sequence.
1-BIT FAULT
DETECTOR The ADM1062 also has a number of status registers. These include
FAULT more detailed information, such as whether an undervoltage or
WARNINGS
overvoltage fault is present on a particular input. The status regis-
ters also include information on ADC limit faults. Note that the
04433-033

MASK
data in the status registers is not latched in any way and, therefore,
Figure 29. Monitoring Fault Detector Block Diagram
is subject to change at any time.
See the AN-698 Application Note for full details about the
ADM1062 registers.

Rev. D | Page 21 of 35
ADM1062 Data Sheet

VOLTAGE READBACK
The ADM1062 has an on-board, 12-bit, accurate ADC for Table 9. ADC Input Voltage Ranges
voltage readback over the SMBus. The ADC has a 12-channel
SFD Input ADC Input Voltage
analog mux on the front end. The 12 channels consist of the Range (V) Attenuation Factor Range (V)
10 SFD inputs (VH, VPx, and VXx), plus two channels for 0.573 to 1.375 1 0 to 2.048
temperature readback (see the Temperature Measurement System 1.25 to 3.00 2.181 0 to 4.46
section). Any or all of these inputs can be selected to be read, 2.5 to 6.0 4.363 0 to 6.01
in turn, by the ADC. The circuit controlling this operation is 6.0 to 14.4 10.472 0 to 14.41
called the ADC round-robin. This circuit can be selected to run 1
The upper limit is the absolute maximum allowed voltage on the VPx and
through its loop of conversions once or continuously. Averaging VH pins.
is also provided for each channel. In this case, the ADC round- The typical way to supply the reference to the ADC on the
robin runs through its loop of conversions 16 times before
REFIN pin is to connect the REFOUT pin to the REFIN pin.
returning a result for each channel. At the end of this cycle, the
REFOUT provides a 2.048 V reference. As such, the supervising
results are written to the output registers.
range covers less than half the normal ADC range. It is possible,
The ADC samples single-sided inputs with respect to the AGND however, to provide the ADC with a more accurate external
pin. A 0 V input gives out Code 0, and an input equal to the reference for improved readback accuracy.
voltage on REFIN gives out full code (4095 decimal).
Supplies can also be connected to the input pins purely for ADC
The inputs to the ADC come directly from the VXx pins and readback, even though these pins may go above the expected
from the back of the input attenuators on the VPx and VH pins, supervisory range limits (but not above the absolute maximum
as shown in Figure 30 and Figure 31. ratings on these pins). For example, a 1.5 V supply connected to
DIGITIZED the VX1 pin can be correctly read out as an ADC code of approxi-
NO ATTENUATION VOLTAGE
READING mately 3/4 full scale, but it always sits above any supervisory limits
12-BIT
VXx
ADC that can be set on that pin. The maximum setting for the REFIN
pin is 2.048 V.
04433-025

2.048V VREF
SUPPLY SUPERVISION WITH THE ADC
Figure 30. ADC Reading on VXx Pins In addition to the readback capability, another level of supervi-
sion is provided by the on-chip, 12-bit ADC. The ADM1062 has
ATTENUATION NETWORK
limit registers with which the user can program a maximum or
VPx/VH (DEPENDS ON RANGE SELECTED)
minimum allowable threshold. Exceeding the threshold generates
DIGITIZED
VOLTAGE
READING
a warning that can either be read back from the status registers
12-BIT or input into the SE to determine what sequencing action the
ADC
ADM1062 should take. Only one register is provided for each
input channel. Therefore, either an undervoltage threshold or
04433-026

2.048V VREF
overvoltage threshold (but not both) can be set for a given channel.
Figure 31. ADC Reading on VPx/VH Pins The ADC round-robin can be enabled via an SMBus write, or it
can be programmed to turn on in any state in the SE program.
The voltage at the input pin can be derived from the following
For example, it can be set to start after a power-up sequence is
equation:
complete, and all supplies are known to be within expected
ADC Code tolerance limits.
V= × Attenuation Factor × VREFIN
4095 Note that a latency is built into this supervision, dictated by the
where VREFIN = 2.048 V when the internal reference is used (that is, conversion time of the ADC. With all 12 channels selected, the
the REFIN pin is connected to the REFOUT pin). total time for the round-robin operation (averaging off) is
The ADC input voltage ranges for the SFD input ranges are listed approximately 6 ms (500 μs per channel selected). Supervision
in Table 9. using the ADC, therefore, does not provide the same real-time
response as the SFDs.

Rev. D | Page 22 of 35
Data Sheet ADM1062

SUPPLY MARGINING
OVERVIEW CLOSED-LOOP SUPPLY MARGINING
It is often necessary for the system designer to adjust supplies, A more accurate and comprehensive method of margining is to
either to optimize their level or force them away from nominal implement a closed-loop system (see Figure 33). The voltage on
values to characterize the system performance under these condi- the rail to be margined can be read back to accurately margin the
tions. This is a function typically performed during an in-circuit rail to the target voltage. The ADM1062 incorporates all the
test (ICT), such as when a manufacturer wants to guarantee that circuits required to do this, with the 12-bit successive
a product under test functions correctly at nominal supplies approximation ADC used to read back the level of the supervised
minus 10%. voltages, and the six voltage output DACs, implemented as
described in the Open-Loop Supply Margining section, used to
OPEN-LOOP SUPPLY MARGINING adjust supply levels. These circuits can be used along with other
The simplest method of margining a supply is to implement an intelligence, such as a microcontroller, to implement a closed-loop
open-loop technique (see Figure 32). A popular way to do this is margining system that allows any dc-to-dc converter or LDO
to switch extra resistors into the feedback node of a power module, supply to be set to any voltage, accurate to within ±0.5% of the
such as a dc-to-dc converter or LDO. The extra resistor alters target.
the voltage at the feedback or trim node and forces the output To implement closed-loop margining
voltage to margin up or down by a certain amount.
1. Disable the six DACx outputs.
The ADM1062 can perform open-loop margining for up to six 2. Set the DAC output voltage equal to the voltage on the
supplies. The six on-board voltage DACs (DAC1 to DAC6) can feedback node.
drive into the feedback pins of the power modules to be margined. 3. Enable the DAC.
The simplest circuit to implement this function is an attenuation 4. Read the voltage at the dc-to-dc converter output that is
resistor that connects the DACx pin to the feedback node of a connected to one of the VPx, VH, or VXx pins.
dc-to-dc converter. When the DACx output voltage is set equal 5. If necessary, modify the DACx output code up or down to
to the feedback voltage, no current flows into the attenuation adjust the dc-to-dc converter output voltage. Otherwise,
resistor, and the dc-to-dc converter output voltage does not stop because the target voltage has been reached.
change. Taking DACx above the feedback voltage forces current 6. Set the DAC output voltage to a value that alters the supply
into the feedback node, and the output of the dc-to-dc converter output by the required amount (for example, ±5%).
is forced to fall to compensate for this. The dc-to-dc converter 7. Repeat Step 4 through Step 6 until the measured supply
output can be forced high by setting the DACx output voltage reaches the target voltage.
lower than the feedback node voltage. The series resistor can
be split in two, and the node between them can be decoupled Step 1 to Step 3 ensure that when the DACx output buffer is
with a capacitor to ground. This can help to decouple any noise turned on, it has little effect on the dc-to-dc converter output.
picked up from the board. Decoupling to a ground local to The DAC output buffer is designed to power up without glitching
the dc-to-dc converter is recommended. by first powering up the buffer to follow the pin voltage. It does
not drive out onto the pin at this time. Once the output buffer is
The ADM1062 can be commanded to margin a supply up or
properly enabled, the buffer input is switched over to the DAC,
down over the SMBus by updating the values on the relevant
and the output stage of the buffer is turned on. Output glitching
DAC output.
is negligible.
VIN
MICROCONTROLLER

VOUT
ADM1062
OUTPUT DEVICE
ATTENUATION CONTROLLER
DC-TO-DC RESISTOR (SMBus)
CONVERTER
DACx
FEEDBACK DAC

PCB
GND TRACE NOISE
04433-067

DECOUPLING
CAPACITOR

Figure 32. Open-Loop Margining System Using the ADM1062

Rev. D | Page 23 of 35
ADM1062 Data Sheet
MICROCONTROLLER
VIN

ADM1062

DC-TO-DC VH/VPx/VXx
CONVERTER
MUX ADC
OUTPUT ATTENUATION
RESISTOR, R3
R1 DEVICE
DACx CONTROLLER
FEEDBACK DAC (SMBus)
R2
PCB
GND TRACE NOISE

04433-034
DECOUPLING
CAPACITOR

Figure 33. Closed-Loop Margining System Using the ADM1062

WRITING TO THE DACS the current flowing through R3. Therefore, a direct relationship
exists between the extra voltage drop across R1 during margining
Four DAC ranges are offered. They can be placed with midcode and the voltage drop across R3.
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are
placed to correspond to the most common feedback voltages. This relationship is given by the following equation:
Centering the DAC outputs in this way provides the best use of R1
ΔVOUT = (VFB − VDACOUT)
the DAC resolution. For most supplies, it is possible to place the R3
DAC midcode at the point where the dc-to-dc converter output
where:
is not modified, thereby giving half of the DAC range to margin
ΔVOUT is the change in VOUT.
up and the other half to margin down.
VFB is the voltage at the feedback node of the dc-to-dc converter.
The DAC output voltage is set by the code written to the DACx VDACOUT is the voltage output of the margining DAC.
register. The voltage is linear with the unsigned binary number
This equation demonstrates that if the user wants the output
in this register. Code 0x7F is placed at the midcode voltage, as
voltage to change by ±300 mV, then R1 = R3. If the user wants the
described previously. The output voltage is given by the following
output voltage to change by ±600 mV, then R1 = 2 × R3, and so on.
equation:
It is best to use the full DAC output range to margin a supply.
DAC Output = (DACx − 0x7F)/255 × 0.6015 + VOFF
Choosing the attenuation resistor in this way provides the most
where VOFF is one of the four offset voltages. resolution from the DAC, meaning that with one DAC code
There are 256 DAC settings available. The midcode value is change, the smallest effect on the dc-to-dc converter output
located at DAC Code 0x7F, as close as possible to the middle voltage is induced. If the resistor is sized up to use a code such as
of the 256 code range. The full output swing of the DACs is 27 decimal to 227 decimal to move the dc-to-dc converter output
+302 mV (+128 codes) and −300 mV (−127 codes) around the by ±5%, it takes 100 codes to move 5% (each code moves the
selected midcode voltage. The voltage range for each midcode output by 0.05%). This is beyond the readback accuracy of the
voltage is shown in Table 10. ADC, but it should not prevent the user from building a circuit to
use the most resolution.
Table 10. Ranges for Midcode Voltages
DAC LIMITING AND OTHER SAFETY FEATURES
Midcode Minimum Voltage Maximum Voltage
Voltage (V) Output (V) Output (V) Limit registers (called DPLIMx and DNLIMx) on the device
0.6 0.300 0.902 offer the user some protection from firmware bugs that can cause
0.8 0.500 1.102 catastrophic board problems by forcing supplies beyond their
1.0 0.700 1.302 allowable output ranges. Essentially, the DAC code written into
1.25 0.950 1.552 the DACx register is clipped such that the code used to set the
DAC voltage is given by
CHOOSING THE SIZE OF THE ATTENUATION DAC Code
RESISTOR = DACx, DACx ≥ DNLIMx and DACx ≤ DPLIMx
The size of the attenuation resistor, R3, determines how much = DNLIMx, DACx < DNLIMx
= DPLIMx, DACx > DPLIMx
the DAC voltage swing affects the output voltage of the dc-to-dc
converter that is being margined (see Figure 33). In addition, the DAC output buffer is three-stated if DNLIMx >
DPLIMx. By programming the limit registers this way, the user
Because the voltage at the feedback pin remains constant, the
can make it very difficult for the DAC output buffers to be turned
current flowing from the feedback node to GND through R2 is a
on during normal system operation. The limit registers are among
constant. In addition, the feedback node itself is high impedance.
the registers downloaded from the EEPROM at startup.
This means that the current flowing through R1 is the same as
Rev. D | Page 24 of 35
Data Sheet ADM1062

TEMPERATURE MEASUREMENT SYSTEM

The ADM1062 contains an on-chip, band gap temperature Figure 36 shows the input signal conditioning used to measure the
sensor whose output is digitized by the on-chip, 12-bit ADC. output of a remote temperature sensor. This figure shows the
Theoretically, the temperature sensor and the ADC can measure external sensor as a substrate transistor provided for temperature
temperatures from −128°C to +128°C with a resolution of 0.125°C. monitoring on some microprocessors, but it could equally be
Because this exceeds the operating temperature range of the device, a discrete transistor such as a 2N3904 or 2N3906.
local temperature measurements outside this range are not possible. If a discrete transistor is used, the collector is not grounded and
Temperature measurements from −128°C to +128°C are possible should be linked to the base. If a PNP transistor is used, the base
using a remote sensor. The output code is in offset binary format, is connected to the DN input, and the emitter is connected to
with −128°C given by Code 0x400, 0°C given by Code 0x800, the DP input. If an NPN transistor is used, the emitter is connected
and +128°C given by Code 0xC00. to the DN input, and the base is connected to the DP input.
As with the other analog inputs to the ADC, a limit register is Figure 34 and Figure 35 show how to connect the ADM1062 to
provided for each of the temperature input channels. Therefore, an NPN or PNP transistor for temperature measurement. To
a temperature limit can be set such that if it is exceeded, a warning prevent ground noise from interfering with the measurement,
is generated and available as an input to the sequencing engine. the more negative terminal of the sensor is not referenced to
This enables users to control their sequence or monitor functions ground but is biased above ground by an internal diode at the
based on an overtemperature or undertemperature event. DN input.
REMOTE TEMPERATURE MEASUREMENT ADM1062
The ADM1062 can measure the temperature of a remote diode 2N3904
NPN DP
sensor or diode-connected transistor connected to Pin DN and
Pin DP (Pin 37 and Pin 38 on the LFCSP package and Pin 44

04433-070
DN
and Pin 45 on the TQFP package).
The forward voltage of a diode or diode-connected transistor Figure 34. Measuring Temperature Using an NPN Transistor
operated at a constant current exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute value
of VBE varies from device to device, and individual calibration ADM1062
is required to null it, making the technique unsuitable for mass DP

production. The technique used in the ADM1062 is to measure

2N3906 DN
the change in VBE when the device is operated at two different PNP

04433-071
currents.
The change in VBE is given by Figure 35. Measuring Temperature Using a PNP Transistor

ΔVBE = kT/q × ln(N)

where:
k is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
VDD

CPU
I N×I IBIAS

VOUT+
THERM DA DP
REMOTE THERM DC DN TO ADC
SENSING
TRANSISTOR BIAS VOUT–
DIODE LOW-PASS FILTER
fC = 65kHz
04433-069

Figure 36. Signal Conditioning for Remote Diode Temperature Sensors

Rev. D | Page 25 of 35
ADM1062 Data Sheet
To measure ΔVBE, the sensor is switched between operating Table 11. Temperature Data Format
currents of I and N × I. The resulting waveform is passed through Temperature Digital Output (Hex) Digital Output (Binary)
a 65 kHz low-pass filter to remove noise and through a chopper- −128°C 0x400 010000000000
stabilized amplifier that amplifies and rectifies the waveform −125°C 0x418 010000011000
to produce a dc voltage proportional to ΔVBE. This voltage is −100°C 0x4E0 010011100000
measured by the ADC to produce a temperature output in 12-bit −75°C 0x5A8 010110101000
offset binary. To further reduce the effects of noise, digital filtering −50°C 0x670 011001110000
is performed by averaging the results of 16 measurement cycles. −25°C 0x738 011100111000
A remote temperature measurement takes nominally 600 ms. −10°C 0x7B0 011110110000
The results of remote temperature measurements are stored in 0°C 0x800 100000000000
12-bit, offset binary format, as shown in Table 11. This format +10.25°C 0x852 100001010010
provides temperature readings with a resolution of 0.125°C. +25.5°C 0x8CC 100011001100
+50.75°C 0x996 100110010110
+75°C 0xA58 101001011000
+100°C 0XB20 101100100000
+125°C 0xBE8 101111101000
+128°C 0xC00 110000000000

Rev. D | Page 26 of 35
Data Sheet ADM1062

APPLICATIONS DIAGRAM
12V IN 12V OUT

5V IN 5V OUT

3V IN 3V OUT

IN
DC-TO-DC1
EN OUT 3.3V OUT
VH
ADM1062
5V OUT VP1 PDO1
3V OUT VP2 PDO2
3.3V OUT VP3
IN
2.5V OUT VP4
1.8V OUT VX1 PDO3 DC-TO-DC2
1.2V OUT VX2 PDO4 EN OUT 2.5V OUT
0.9V OUT VX3 PDO5
POWRON PWRGD
VX4 PDO6
SIGNAL VALID
RESET PDO7 IN
SYSTEM RESET DC-TO-DC3
VX5 PDO8
PDO9 EN OUT 1.8V OUT
PDO10
3.3V OUT
REFOUT DAC1*
DP IN
DN LDO
REFIN VCCP VDDCAP GND
EN OUT 0.9V OUT
3.3V OUT
10µF 10µF 10µF
IN
OUT 1.2V OUT
*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC6 EN TRIM
ALLOW MARGINING FOR UP TO SIX
VOLTAGE RAILS. DC-TO-DC4
TEMPERATURE
DIODE

3.3V OUT
MICRO-
PROCESSOR
2.5V OUT
04433-068

Figure 37. Applications Diagram

Rev. D | Page 27 of 35
ADM1062 Data Sheet

COMMUNICATING WITH THE ADM1062

CONFIGURATION DOWNLOAD AT POWER-UP The ADM1062 provides several options that allow the user to
The configuration of the ADM1062 (undervoltage/overvoltage update the configuration over the SMBus interface. The following
thresholds, glitch filter timeouts, PDO configurations, and so on) three options are controlled in the UPDCFG register:
is dictated by the contents of the RAM. The RAM comprises Option 1
digital latches that are local to each of the functions on the device. Update the configuration in real time. The user writes to the RAM
The latches are double-buffered and have two identical latches, across the SMBus, and the configuration is updated immediately.
Latch A and Latch B. Therefore, when an update to a function
Option 2
occurs, the contents of Latch A are updated first, and then the
contents of Latch B are updated with identical data. The advantages Update the Latch As without updating the Latch Bs. With this
of this architecture are explained in detail in the Updating the method, the configuration of the ADM1062 remains unchanged
Configuration section. and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be Option 3
restored at power-up by downloading the contents of the EEPROM Change the EEPROM register contents without changing the
(nonvolatile memory) to the local latches. This download occurs RAM contents, and then download the revised EEPROM contents
in six steps, as follows: to the RAM registers. With this method, the configuration of
1. With no power applied to the device, the PDOs are all the ADM1062 remains unchanged and continues to operate in
high impedance. the original setup until the instruction is given to update the RAM.
2. When 1.2 V appears on any of the inputs connected to the The instruction to download from the EEPROM in Option 3 is
VDD arbitrator (VH or VPx), the PDOs are all weakly also a useful way to restore the original EEPROM contents if
pulled to GND with a 20 kΩ resistor. revisions to the configuration are unsatisfactory. For example,
3. When the supply rises above the undervoltage lockout of if the user needs to alter an overvoltage threshold, the RAM
the device (UVLO is 2.5 V), the EEPROM starts to register can be updated, as described in Option 1. However,
download to the RAM. if the user is not satisfied with the change and wants to revert to
4. The EEPROM downloads its contents to all Latch As. the original programmed value, the device controller can issue
5. When the contents of the EEPROM are completely down- a command to download the EEPROM contents to the RAM
loaded to the Latch As, the device controller signals all again, as described in Option 3, restoring the ADM1062 to its
Latch As to download to all Latch Bs simultaneously, original configuration.
completing the configuration download.
The topology of the ADM1062 makes this type of operation
6. At 0.5 ms after the configuration download completes, the first
possible. The local, volatile registers (RAM) are all double-
state definition is downloaded from the EEPROM into the SE.
buffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
Note that any attempt to communicate with the device prior to the double-buffered latches open at all times. If Bit 0 is set to 0
the completion of the download causes the ADM1062 to issue when a RAM write occurs across the SMBus, only the first side
a no acknowledge (NACK). of the double-buffered latch is written to. The user must then write
a 1 to Bit 1 of the UPDCFG register. This generates a pulse to
UPDATING THE CONFIGURATION
update all the second latches at once. EEPROM writes occur in
After power-up, with all the configuration settings loaded from a similar way.
the EEPROM into the RAM registers, the user may need to alter
The final bit in this register can enable or disable EEPROM
the configuration of functions on the ADM1062, such as changing
page erasure. If this bit is set high, the contents of an EEPROM
the undervoltage or overvoltage limit of an SFD, changing the
page can all be set to 1. If this bit is set low, the contents of a
fault output of an SFD, or adjusting the rise time delay of one of
page cannot be erased, even if the command code for page
the PDOs.
erasure is programmed across the SMBus. The bit map for the
UPDCFG register is shown in the AN-698 Application Note. A
flow diagram for download at power-up and subsequent
configuration updates is shown in Figure 38.

Rev. D | Page 28 of 35
Data Sheet ADM1062
SMBus

POWER-UP DEVICE
(VCC > 2.5V) E CONTROLLER R U
E A P
P D M D
R A L
O T D
M A
L LATCH A LATCH B
FUNCTION
D (OV THRESHOLD

04433-035
EEPROM ON VP1)

Figure 38. Configuration Update Flow Diagram

UPDATING THE SEQUENCING ENGINE The major differences between the EEPROM and other
Sequencing engine (SE) functions are not updated in the same way registers are as follows:
as regular configuration latches. The SE has its own dedicated  An EEPROM location must be blank before it can be
512-byte nonvolatile, electrically erasable, programmable, read- written to. If it contains data, the data must first be erased.
only memory (EEPROM) for storing state definitions. The  Writing to the EEPROM is slower than writing to the RAM.
EEPROM provides 63 individual states, each with a 64-bit word  Writing to the EEPROM should be restricted because it has
(one state is reserved). At power-up, the first state is loaded from a limited write/cycle life of typically 10,000 write operations
the SE EEPROM into the engine itself. When the conditions of this due to the usual EEPROM wear-out mechanisms.
state are met, the next state is loaded from the EEPROM into the
engine, and so on. The loading of each new state takes approxi- The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
mately 10 μs. each. Page 0 to Page 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1062 (such
To alter a state, the required changes must be made directly to as the SFDs and PDOs). These EEPROM addresses are the same
the EEPROM. RAM for each state does not exist. The relevant as the RAM register addresses, prefixed by F8. Page 7 is reserved.
alterations must be made to the 64-bit word, which is then Page 8 to Page 15 are for customer use.
uploaded directly to the EEPROM.
Data can be downloaded from the EEPROM to the RAM in one
INTERNAL REGISTERS of the following ways:
The ADM1062 contains a large number of data registers. The  At power-up, when Page 0 to Page 6 are downloaded
principal registers are the address pointer register and the
 By setting Bit 0 of the UDOWNLD register (0xD8), which
configuration registers.
performs a user download of Page 0 to Page 6
Address Pointer Register
SERIAL BUS INTERFACE
The address pointer register contains the address that selects
one of the other internal registers. When writing to the ADM1062, The ADM1062 is controlled via the serial system management
the first byte of data is always a register address that is written to bus (SMBus) and is connected to this bus as a slave device under
the address pointer register. the control of a master device. It takes approximately 1 ms after
power-up for the ADM1062 to download from its EEPROM.
Configuration Registers Therefore, access to the ADM1062 is restricted until the download
The configuration registers provide control and configuration is complete.
for various operating parameters of the ADM1062.
Identifying the ADM1062 on the SMBus
EEPROM The ADM1062 has a 7-bit serial bus slave address (see Table 12).
The ADM1062 has two 512-byte cells of nonvolatile EEPROM The device is powered up with a default serial bus address. The
from Register Address 0xF800 to Register Address 0xFBFF. The five MSBs of the address are set to 00101; the two LSBs are
EEPROM is used for permanent storage of data that is not lost determined by the logical states of Pin A1 and Pin A0. This
when the ADM1062 is powered down. One EEPROM cell contains allows the connection of four ADM1062 devices to one SMBus.
the configuration data of the device; the other contains the state Table 12. Serial Bus Slave Address
definitions for the SE. Although referred to as read-only memory,
A1 Pin A0 Pin Hex Address 7-Bit Address1
the EEPROM can be written to, as well as read from, using the
Low Low 0x28 0010100x
serial bus in exactly the same way as the other registers.
Low High 0x2A 0010101x
High Low 0x2C 0010110x
High High 0x2E 0010111x
1
x = Read/Write bit. The address is shown only as the first 7 MSBs.

Rev. D | Page 29 of 35
ADM1062 Data Sheet
The device also has several identification registers (read-only) It may be an instruction telling the slave device to expect a block
that can be read across the SMBus. Table 13 lists these registers write, or it may be a register address that tells the slave where subse-
with their values and functions. quent data is to be written. Because data can flow in only one
direction, as defined by the R/W bit, sending a command to a
Table 13. Identification Register Values and Functions
slave device during a read operation is not possible. Before a read
Name Address Value Function operation, it may be necessary to perform a write operation to
MANID 0xF4 0x41 Manufacturer ID for Analog Devices tell the slave what sort of read operation to expect and/or the
REVID 0xF5 0x02 Silicon revision address from which data is to be read.
MARK1 0xF6 0x00 Software brand
MARK2 0xF7 0x00 Software brand Step 3
When all data bytes have been read or written, stop conditions
General SMBus Timing are established. In write mode, the master pulls the data line
Figure 39, Figure 40, and Figure 41 are timing diagrams for high during the 10th clock pulse to assert a stop condition. In
general read and write operations using the SMBus. The SMBus read mode, the master device releases the SDA line during the
specification defines specific conditions for different types of low period before the ninth clock pulse, but the slave device
read and write operations, which are discussed in the Write does not pull it low. This is known as a no acknowledge. The
Operations and Read Operations sections. master then takes the data line low during the low period before
The general SMBus protocol operates as follows: the 10th clock pulse and then high during the 10th clock pulse
to assert a stop condition.
Step 1
SCL Held Low Timeout
The master initiates data transfer by establishing a start condition,
If the bus master holds the SCL low for a time that is a multiple
defined as a high-to-low transition on the serial data (SDA) line,
of approximately 30 ms, the ADM1062 bus interface may timeout.
while the serial clock-line (SCL) remains high. This indicates that a
If this timeout happens, the in progress transaction is NACKed,
data stream follows. All slave peripherals connected to the serial
and the transaction must be repeated. This behavior is only seen
bus respond to the start condition and shift in the next eight bits,
if the I2C bus master is interrupted midtransaction by a higher
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
priority task that delays completion of the transaction.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write, False Start Detection
1 = read). The data hold time specification defines the time that data must
The peripheral whose address corresponds to the transmitted be valid on the SDA line, following an SCL falling edge. If there
address responds by pulling the data line low during the low are multiple ADM1062 devices on the same bus, one of the
period before the ninth clock pulse, known as the acknowledge ADM1062 devices may see the SCL/SDA transition due to an
bit, and by holding it low during the high period of this clock pulse. acknowledge (ACK) from a different device as a start condition
because of internal timing skew, which for most transactions,
All other devices on the bus remain idle while the selected device this is not an issue. In a case where the data appearing on the
waits for data to be read from or written to it. If the R/W bit is a 0, bus after the false start is detected happens to match the address
the master writes to the slave device. If the R/W bit is a 1, the of another ADM1062 on the bus, that device may incorrectly ACK.
master reads from the slave device.
A bus master may see this ACK as another bus master talking
Step 2 on the bus, halt the bus transaction, and not produce any more
Data is sent over the serial bus in sequences of nine clock pulses: clocks on the SCL. As a result, the ADM1062 device that
eight bits of data followed by an acknowledge bit from the slave incorrectly ACKed continues to hold down the SDA line low.
device. Data transitions on the data line must occur during the To retry the halted bus transaction, the bus master performs a
low period of the clock signal and remain stable during the high clock flush on the SCL by sending a series of up to 16 clock pulses.
period because a low-to-high transition when the clock is high The clock flush forces the ADM1062 to release the SDA line.
could be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.

Rev. D | Page 30 of 35
Data Sheet ADM1062
1 9 1 9
SCL

SDA 0 0 1 0 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER SLAVE SLAVE
FRAME 1 FRAME 2
SLAVE ADDRESS COMMAND CODE
1 9 1 9
SCL
(CONTINUED)

SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY ACK. BY STOP

04433-036
SLAVE SLAVE BY
FRAME 3 FRAME N MASTER
DATA BYTE DATA BYTE

Figure 39. General SMBus Write Timing Diagram

1 9 1 9
SCL

SDA 0 0 1 0 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER SLAVE MASTER
FRAME 1 FRAME 2
SLAVE ADDRESS DATA BYTE
1 9 1 9
SCL
(CONTINUED)

SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY STOP

04433-037
MASTER NO ACK. BY
FRAME 3 FRAME N MASTER
DATA BYTE DATA BYTE

Figure 40. General SMBus Read Timing Diagram

tR tF t HD; STA

SCL t LO W

t HD; STA t HI G H t SU; STA t SU; STO

t HD; DAT t SU; DAT
SDA
04433-038

t BUF
P S S P

Figure 41. Serial Bus Timing Diagram

Rev. D | Page 31 of 35
ADM1062 Data Sheet
SMBus PROTOCOLS FOR RAM AND EEPROM In the ADM1062, the send byte protocol is used for two purposes:
The ADM1062 contains volatile registers (RAM) and non-  To write a register address to the RAM for a subsequent single
volatile registers (EEPROM). User RAM occupies Address 0x00 byte read from the same address, or for a block read or a
to Address 0xDF; the EEPROM occupies Address 0xF800 to block write starting at that address, as shown in Figure 42.
Address 0xFBFF.
1 2 3 4 5 6
Data can be written to and read from both the RAM and the SLAVE
RAM

04433-039
S W A ADDRESS A P
EEPROM as single data bytes. Data can be written only to unpro- ADDRESS
(0x00 TO 0xDF)
grammed EEPROM locations. To write new data to a programmed
Figure 42. Setting a RAM Address for Subsequent Read
location, the location contents must first be erased. EEPROM
erasure cannot be done at the byte level. The EEPROM is arranged  To erase a page of EEPROM memory. EEPROM memory
as 32 pages of 32 bytes each, and an entire page must be erased. can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
Page erasure is enabled by setting Bit 2 in the UPDCFG register
programmed, the page(s) containing those locations must
(Address 0x90) to 1. If this bit is not set, page erasure cannot
first be erased. EEPROM memory is erased by writing a
occur, even if the command byte (0xFE) is programmed across
command byte.
the SMBus.
The master sends a command code telling the slave device
WRITE OPERATIONS to erase the page. The ADM1062 command code for a page
The SMBus specification defines several protocols for different erasure is 0xFE (1111 1110). Note that for a page erasure to
types of read and write operations. The following abbreviations take place, the page address must be given in the previous
are used in Figure 42 to Figure 50: write word transaction (see the Write Byte/Word section).
In addition, Bit 2 in the UPDCFG register (Address 0x90)
 S = Start
must be set to 1.
 P = Stop
1 2 3 4 5 6
 R = Read
COMMAND
 SLAVE

04433-040
W = Write S
ADDRESS
W A BYTE A P
(0xFE)
 A = Acknowledge
 A = No acknowledge Figure 43. EEPROM Page Erasure

As soon as the ADM1062 receives the command byte,

The ADM1062 uses the following SMBus write protocols.
page erasure begins. The master device can send a stop
Send Byte command as soon as it sends the command byte. Page
In a send byte operation, the master device sends a single erasure takes approximately 20 ms. If the ADM1062 is
command byte to a slave device, as follows: accessed before erasure is complete, it responds with a no
acknowledge (NACK).
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge (ACK)
on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.

Rev. D | Page 32 of 35
Data Sheet ADM1062
Write Byte/Word Block Write
In a write byte/word operation, the master device sends a In a block write operation, the master device writes a block of
command byte and one or two data bytes to the slave device, data to a slave device. The start address for a block write must
as follows: have been set previously. In the ADM1062, a send byte opera-
1. The master device asserts a start condition on SDA. tion sets a RAM address, and a write byte/word operation sets
2. The master sends the 7-bit slave address followed by the an EEPROM address, as follows:
write bit (low). 1. The master device asserts a start condition on SDA.
3. The addressed slave device asserts an ACK on SDA. 2. The master sends the 7-bit slave address followed by
4. The master sends a command code. the write bit (low).
5. The slave asserts an ACK on SDA. 3. The addressed slave device asserts an ACK on SDA.
6. The master sends a data byte. 4. The master sends a command code that tells the slave
7. The slave asserts an ACK on SDA. device to expect a block write. The ADM1062 command
8. The master sends a data byte or asserts a stop condition. code for a block write is 0xFC (1111 1100).
9. The slave asserts an ACK on SDA. 5. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end 6. The master sends a data byte that tells the slave device how
the transaction. many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
In the ADM1062, the write byte/word protocol is used for three
7. The slave asserts an ACK on SDA.
purposes:
8. The master sends N data bytes.
 To write a single byte of data to the RAM. In this case, the 9. The slave asserts an ACK on SDA after each data byte.
command byte is RAM Address 0x00 to RAM Address 0xDF, 10. The master asserts a stop condition on SDA to end the
and the only data byte is the actual data, as shown in Figure 44. transaction.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10
RAM
SLAVE W A
04433-041

S ADDRESS ADDRESS A DATA A P S SLAVE W A COMMAND 0xFC A BYTE A DATA A DATA A DATA A P

04433-044
(0x00 TO 0xDF) ADDRESS (BLOCK WRITE) COUNT 1 2 N

Figure 44. Single Byte Write to the RAM

Figure 47. Block Write to the EEPROM or RAM
 To set up a 2-byte EEPROM address for a subsequent read, Unlike some EEPROM devices that limit block writes to within
write, block read, block write, or page erase. In this case, the a page boundary, there is no limitation on the start address
command byte is the high byte of EEPROM Address 0xF8 when performing a block write to EEPROM, except when
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 45.  There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
1 2 3 4 5 6 7 8
EEPROM EEPROM
invalid addresses.
SLAVE ADDRESS ADDRESS

04433-042

S ADDRESS W A
HIGH BYTE A
LOW BYTE
A P An address crosses a page boundary. In this case, both
(0xF8 TO 0xFB) (0x00 TO 0xFF)
pages must be erased before programming.
Figure 45. Setting an EEPROM Address
Note that the ADM1062 features a clock extend function for
Because a page consists of 32 bytes, only the three MSBs writes to EEPROM. Programming an EEPROM byte takes
of the address low byte are important for page erasure. The approximately 250 μs, which limits the SMBus clock for repeated
lower five bits of the EEPROM address low byte specify the or block write operations. The ADM1062 pulls SCL low and
addresses within a page and are ignored during an erase extends the clock pulse when it cannot accept any more data.
operation.
 To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 46.
1 2 3 4 5 6 7 8 9 10
EEPROM EEPROM
SLAVE ADDRESS ADDRESS
04433-043

S ADDRESS W A HIGH BYTE A A DATA A P

LOW BYTE
(0xF8 TO 0xFB) (0x00 TO 0xFF)

Figure 46. Single Byte Write to the EEPROM

Rev. D | Page 33 of 35
ADM1062 Data Sheet
READ OPERATIONS 10. The master asserts an ACK on SDA.
The ADM1062 uses the following SMBus read protocols. 11. The master receives 32 data bytes.
12. The master asserts an ACK on SDA after each data byte.
Receive Byte 13. The master asserts a stop condition on SDA to end
In a receive byte operation, the master device receives a single the transaction.
byte from a slave device, as follows: 1 2 3 4 5 6 7 8 9 10 11 12

1. The master device asserts a start condition on SDA. S

SLAVE
W A
COMMAND 0xFD
A S
SLAVE
R A
BYTE
A
DATA
A
ADDRESS (BLOCK READ) ADDRESS COUNT 1
2. The master sends the 7-bit slave address followed by the
read bit (high).
13
3. The addressed slave device asserts an ACK on SDA.
DATA

04433-046
4. The master receives a data byte. 32
A P

5. The master asserts a NACK on SDA.

6. The master asserts a stop condition on SDA, and the Figure 49. Block Read from the EEPROM or RAM
transaction ends. Error Correction
In the ADM1062, the receive byte protocol is used to read a The ADM1062 provides the option of issuing a packet error
single byte of data from a RAM or EEPROM location whose correction (PEC) byte after a write to the RAM, a write to the
address has previously been set by a send byte or write EEPROM, a block write to the RAM/EEPROM, or a block read
byte/word operation, as shown in Figure 48. from the RAM/ EEPROM. This option enables the user to verify
1 2 3 4 5 6
that the data received by or sent from the ADM1062 is correct.
The PEC byte is an optional byte sent after the last data byte has
SLAVE
04433-045

S R A DATA A P
ADDRESS been written to or read from the ADM1062. The protocol is the
same as a block read for Step 1 to Step 12 and then proceeds as
Figure 48. Single Byte Read from the EEPROM or RAM Block Read
follows:
In a block read operation, the master device reads a block of
13. The ADM1062 issues a PEC byte to the master. The master
data from a slave device. The start address for a block read must
checks the PEC byte and issues another block read if the
have been set previously. In the ADM1062, this is done by a
PEC byte is incorrect.
send byte operation to set a RAM address, or a write byte/word
14. A NACK is generated after the PEC byte to signal the end
operation to set an EEPROM address. The block read operation
of the read.
itself consists of a send byte operation that sends a block read
15. The master asserts a stop condition on SDA to end the
command to the slave, immediately followed by a repeated start
transaction.
and a read operation that reads out multiple data bytes, as follows:
1. The master device asserts a start condition on SDA. Note that the PEC byte is calculated using CRC-8. The frame
2. The master sends the 7-bit slave address followed by the check sequence (FCS) conforms to CRC-8 by the polynomial
write bit (low). C(x) = x8 + x2 + x1 + 1
3. The addressed slave device asserts an ACK on SDA. See the SMBus Version 1.1 specification for details.
4. The master sends a command code that tells the slave
device to expect a block read. The ADM1062 command An example of a block read with the optional PEC byte is shown
in Figure 50.
code for a block read is 0xFD (1111 1101).
1 2 3 4 5 6 7 8 9 10 11 12
5. The slave asserts an ACK on SDA.
6. The master asserts a repeat start condition on SDA. S SLAVE
ADDRESS
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
(BLOCK READ) ADDRESS COUNT 1
7. The master sends the 7-bit slave address followed by the
read bit (high). 13 14 15
8. The slave asserts an ACK on SDA.
DATA
04433-047

A PEC A P
9. The ADM1062 sends a byte-count data byte that tells the 32

master how many data bytes to expect. The ADM1062

Figure 50. Block Read from the EEPROM or RAM with PEC
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.

Rev. D | Page 34 of 35
Data Sheet ADM1062

OUTLINE DIMENSIONS
6.10 0.30
6.00 SQ 0.25
PIN 1 5.90 0.18
INDICATOR PIN 1
31 40
INDICATOR
30 1

0.50
BSC 4.25
EXPOSED
PAD 4.10 SQ
3.95

21 10
20 11
0.45 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.35 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE

05-06-2011-A
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.

Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-9)
Dimensions shown in millimeters
1.20 9.00
0.75 MAX BSC SQ
0.60
0.45 48 37
1 36

PIN 1
7.00
TOP VIEW BSC SQ
1.05 0° MIN
0.20 (PINS DOWN)
1.00 0.09
0.95 7°
3.5° 12 25
0.15 0° 13 24
SEATING
0.05 PLANE 0.08 MAX
COPLANARITY VIEW A 0.50 0.27
BSC 0.22
LEAD PITCH
VIEW A 0.17
ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026ABC

Figure 52. 48-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-48)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM1062ACPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-9
ADM1062ACPZ-REEL7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-9
ADM1062ASUZ −40°C to +85°C 48-Lead Thin Plastic Quad Flat Package [TQFP] SU-48
ADM1062ASUZ-REEL7 −40°C to +85°C 48-Lead Thin Plastic Quad Flat Package [TQFP] SU-48
EVAL-ADM1062TQEBZ Evaluation Kit (TQFP Version)
1
Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04433-0-1/15(D)

Rev. D | Page 35 of 35