TPS62A06, TPS62A06A

SLUSET0A – APRIL 2023 – REVISED JUNE 2023

TPS62A06x, 6-A, High-Efficiency, Synchronous Buck Converter in a SOT563 Package

1 Features 3 Description
• 2.5-V to 5.5-V input voltage range The TPS62A06 family of devices are synchronous,
• 0.6-V to VIN adjustable output voltage range step-down, buck, DC/DC converters optimized for
• 15-mΩ / 10-mΩ low RDSON switches (6 A) high efficiency and compact solution size. The device
• 25-µA quiescent current integrates switches capable of delivering an output
• 1% feedback accuracy (0°C to 125°C) current up to 6 A. At medium to heavy loads, the
• 100% mode operation device operates in pulse width modulation (PWM)
• 2.2-MHz switching frequency mode with 2.2-MHz switching frequency. At light load,
• Power save mode or FPWM option available the device automatically enters power save mode
• Power-good output pin (PSM) to maintain high efficiency over the entire load
• Short-circuit protection (HICCUP) current range. The TPS62A06A variants of this device
• Internal soft start-up family operate in forced PWM across the whole load
• Output discharge current range.
• Thermal shutdown protection
The TPS62A06 provides an adjustable output voltage
• Available in a 1.6-mm × 1.6-mm SOT563 package
through an external resistor divider. An internal soft-
• Pin-to-pin compatible with the TLV62585
start circuit limits the inrush current during start-up.
2 Applications Other features like overcurrent protection, thermal
shutdown protection, and power good are built-in. The
• Multi-function printer
device is available in a SOT563 package.
• Set top box
• TV applications Device Information
• IP network camera PART
MODE PACKAGE(1) BODY SIZE (NOM)
• Wireless router, solid state drive NUMBER
• Battery-powered applications TPS62A06 PSM, PWM DRL
1.60 mm × 1.60 mm
• General purpose point-of-load supply TPS62A06A FPWM (SOT563, 6)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
TPS62A06
L1 100
VOUT
0.22
H 1.2 V/ 6.0 A
VIN
2.5 V to 5.5 V VIN
SW 95

R1 90
CIN 100 kΩ CFF COUT
22 F
GND FB
3x22 F 85
Efficiency [%]

GND VPG 80
R2
R3 100 kΩ 75
EN PG
70
GND
65
Typical Application 60
VOUT = 1.2 V
55 VOUT = 1.8 V
VOUT = 3.3 V
50
1m 10m 100m 1 6
Output Current [A] D002

Efficiency Versus Output Current at 5 VIN

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62A06, TPS62A06A
SLUSET0A – APRIL 2023 – REVISED JUNE 2023 www.ti.com

Table of Contents
1 Features............................................................................1 8.4 Device Functional Modes............................................8
2 Applications..................................................................... 1 9 Application and Implementation.................................. 10
3 Description.......................................................................1 9.1 Application Information............................................. 10
4 Revision History.............................................................. 2 9.2 Typical Application.................................................... 10
5 Device Comparison Table...............................................3 9.3 Power Supply Recommendations.............................14
6 Pin Configuration and Functions...................................3 9.4 Layout....................................................................... 14
7 Specifications.................................................................. 4 10 Device and Documentation Support..........................15
7.1 Absolute Maximum Ratings........................................ 4 10.1 Device Support....................................................... 15
7.2 ESD Ratings............................................................... 4 10.2 Documentation Support.......................................... 15
7.3 Recommended Operating Conditions.........................4 10.3 Receiving Notification of Documentation Updates..15
7.4 Thermal Information....................................................4 10.4 Support Resources................................................. 15
7.5 Electrical Characteristics.............................................5 10.5 Trademarks............................................................. 15
7.6 Typical Characteristics................................................ 6 10.6 Electrostatic Discharge Caution..............................15
8 Detailed Description........................................................7 10.7 Glossary..................................................................15
8.1 Overview..................................................................... 7 11 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram........................................... 7 Information.................................................................... 15
8.3 Feature Description.....................................................7

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (April 2023) to Revision A (June 2023) Page
• Changed document status from Advance Information to Production Data.........................................................1

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS62A06 TPS62A06A

 TPS62A06, TPS62A06A
www.ti.com SLUSET0A – APRIL 2023 – REVISED JUNE 2023

5 Device Comparison Table

DEVICE NUMBER OUTPUT CURRENT OPERATION MODE
TPS62A06 6A PSM/ PWM
TPS62A06A 6A FPWM

6 Pin Configuration and Functions

GND 1 6 PG

SW 2 5 FB

VIN 3 4 EN

Not to scale

Figure 6-1. 6-Pin DRL SOT563 Package (Top View)

Table 6-1. Pin Functions

PIN
I/O(1) DESCRIPTION
NAME NO.
Device enable logic input. Logic high enables the device, logic low disables the device and turns the
EN 4 I
device into shutdown. Do not leave the pin floating.
FB 5 I Feedback pin for the internal control loop. Connect this pin to an external feedback divider.
GND 1 G Ground pin
Power-good open-drain output pin. The pullup resistor cannot be connected to any voltage higher than
PG 6 O
5.5 V. If unused, leave the pin open or connect to GND.
Switch pin connected to the internal FET switches and inductor terminal. Connect the inductor of the
SW 2 O
output filter to this pin.
VIN 3 I Power supply voltage pin

(1) I = Input, O = Output, G = Ground

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: TPS62A06 TPS62A06A

TPS62A06, TPS62A06A
SLUSET0A – APRIL 2023 – REVISED JUNE 2023 www.ti.com

7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN, EN, PG –0.3 6 V
SW, DC –0.3 VIN + 0.3 V
Pin voltage(2)
SW, transient < 10 ns –3.0 10 V
FB –0.3 3 V
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground terminal.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
±2000
JS-001 (1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/ESDA/JEDEC
±500
JS-002 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input supply voltage range 2.5 5.5 V
VOUT Output voltage range 0.6 VIN V
L Effective inductance 0.22 µH
COUT Effective output capacitance VOUT < 1.2 V 120 µF
COUT Effective output capacitance 1.2 V <= VOUT < 1.8 V 45 µF
COUT Effective output capacitance VOUT => 1.8 V 45 µF
IOUT Output current range TPS62A06 0 6 A
IPG Power Good input current capability 0 1 mA
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

TPS62A06x TPS62A06EVM-248
THERMAL METRIC(1) DRL EVM UNIT
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 137.5 74.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 60.2 - °C/W
RθJB Junction-to-board thermal resistance 22.0 - °C/W
ψJT Junction-to-top characterization parameter 1.4 1.2 °C/W
ψJB Junction-to-board characterization parameter 21.6 33.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS62A06 TPS62A06A

 TPS62A06, TPS62A06A
www.ti.com SLUSET0A – APRIL 2023 – REVISED JUNE 2023

7.5 Electrical Characteristics

TJ = –40°C to +125°C, VIN = 2.5 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN) VIN quiescent current Non-switching, VEN = High, VFB = 610 mV 26 µA
ISD(VIN) VIN shutdown supply current TJ = –40°C to 85°C, VEN = Low 0.01 4 µA
UVLO
VUVLO(R) VIN UVLO rising threshold VIN rising 2.3 2.4 2.5 V
VUVLO(F) VIN UVLO falling threshold VIN falling 2.2 2.3 2.4 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 V
VEN(F) EN voltage falling threshold EN falling, disable switching 0.4 V
VEN(LKG) EN Input leakage current VEN = 5 V 100 nA
REFERENCE VOLTAGE
VFB FB voltage TJ = 0°C to 125°C, PWM mode 594 600 606 mV
VFB FB voltage PWM mode 591 600 609 mV
IFB(LKG) FB input leakage current VFB = 0.6 V 100 nA
SWITCHING FREQUENCY
fSW(FCCM) Switching frequency, FPWM operation VIN = 5 V, VOUT = 1.8 V 2200 kHz
STARTUP
Internal fixed soft-start time From EN = High to VFB = 0.56 V 0.5 1 ms
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance TPS62A06, VIN = 5 V 15 mΩ
RDSON(LS) Low-side MOSFET on-resistance TPS62A06, VIN = 5 V 10 mΩ
OVERCURRENT PROTECTION
IHS(OC) High-side peak current limit TPS62A06 8.2 10 A
ILS(OC) Low-side valley current limit TPS62A06 9.1 A
POWER GOOD
VPGTH Power Good threshold PG low, FB falling 93.5 %
VPGTH Power Good threshold PG high, FB rising 96 %
PG delay falling 30 µs
PG delay rising 10 µs
PG pin Leakage current when open drain
IPG(LKG) VPG = 5 V 100 nA
output is high
PG pin output low-level voltage IPG = 1 mA 400 mV
OUTPUT DISCHARGE
Output discharge current on SW pin VIN = 3 V, VOUT = 2.0 V 150 mA
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold Temperature rising 170 °C
TJ(HYS) Thermal shutdown hysteresis 20 °C

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: TPS62A06 TPS62A06A

TPS62A06, TPS62A06A
SLUSET0A – APRIL 2023 – REVISED JUNE 2023 www.ti.com

7.6 Typical Characteristics

32 2
VIN = 2.5 V
1.8 VIN = 3.6 V
30 VIN = 5.0 V
1.6
Quiescent Current [µA]

Shutdown Current [µA]

28 1.4
1.2
26
1
24 0.8

22 0.6

TJ=-40°C 0.4
20 TJ=30°C
TJ=85°C 0.2
TJ=125°C
18 0
2.5 3 3.5 4 4.5 5 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 140
Input Voltage [V] Junction Temperature [°C]

Figure 7-1. Quiescent Current vs Input Voltage Figure 7-2. Shutdown Current vs Junction
Temperature
300
270
Output Discharge Current [mA]

240
210
180
150
120
90
TJ = -40°C
60 TJ = 0°C
TJ = 30°C
30 TJ = 85°C
TJ = 125°C
0
2.5 3 3.5 4 4.5 5 5.5
Input Voltage [V]

Figure 7-3. Output Discharge Current vs Input Voltage

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS62A06 TPS62A06A

 TPS62A06, TPS62A06A
www.ti.com SLUSET0A – APRIL 2023 – REVISED JUNE 2023

8 Detailed Description
8.1 Overview
The TPS62A0x is a high-efficiency, synchronous step-down converter. The device operates with an adaptive
off time with a peak current control scheme. The device operates typically at 2.2-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets
the required off time for the low-side MOSFET. This action makes the switching frequency relatively constant
regardless of the variation of the input voltage, output voltage, and load current.
8.2 Functional Block Diagram
VIN

VI

Device Control
and Logic
HS Limit
UVLO Peak Current Detect
EN
Soft Start
HICCUP protection
Thermal Shutdown

Modulator and
Power Control

SW
Power Save Mode Gate
and PWM Driver
Operation

VFB
VFB – 100% Mode
+
VREF

LS Limit
Zero Current Detect

Active
Discharge

EN

PG
VI

TOFF timer

+ VPG
VO
– VFB

GND

8.3 Feature Description

8.3.1 Power Save Mode
The device automatically enters power save mode to improve efficiency at light load when the inductor current
becomes discontinuous. In power save mode, the converter reduces the switching frequency and minimizes
current consumption. In power save mode, the output voltage rises slightly above the nominal output voltage.
This effect is minimized by increasing the output capacitor or adding a feedforward capacitor.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: TPS62A06 TPS62A06A

TPS62A06, TPS62A06A
SLUSET0A – APRIL 2023 – REVISED JUNE 2023 www.ti.com

8.3.2 100% Duty Cycle Low Dropout Operation

The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:

VIN(MIN) = VOUT + IOUT × RDS(ON) + RL (1)

where
• RDS(ON) = High-side FET on-resistance
• RL = Inductor ohmic resistance (DCR)
8.3.3 Soft Start
After enabling the device, internal soft start-up circuitry ramps up the output voltage, which reaches the nominal
output voltage during start-up time, avoiding excessive inrush current and creating a smooth output voltage rise
slope. soft start-up circuitry also prevents excessive voltage drops of primary cells and rechargeable batteries
with high internal impedance.
The TPS62A0x is able to start into a pre-biased output capacitor. The converter starts with the applied bias
voltage and ramps the output voltage to its nominal value.
8.3.4 Switch Current Limit and Short-Circuit Protection (HICCUP)
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current can occur with a shorted or saturated inductor or an overload
or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET is
turned off and the low-side MOSFET is turned on to ramp down the inductor current with an adaptive off time.
When this switch current limit is triggered 32 times, the device reduces the current limit for further 32 cycles and
then stops switching to protect the output. The device then automatically starts a new start-up after a typical
delay time of 500 µs has passed. This action is named HICCUP short-circuit protection. The device repeats this
mode until the high load condition disappears. HICCUP protection is also enabled during the start-up.
8.3.5 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the device at voltages lower than VUVLO with a hysteresis of 130 mV.
8.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
8.4 Device Functional Modes

8.4.1 Enable and Disable

The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If
the device is enabled, the internal power stage starts switching and regulates the output voltage to the set point
voltage. The EN input must be terminated and must not be left floating.
8.4.2 Power Good
The TPS62A06x has a built-in power-good (PG) feature to indicate whether the output voltage has reached its
target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin
is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level.
PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN must
remain present for the PG pin to stay low.
If the power-good output is not used, TI recommends to tie to GND or leave open.

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS62A06 TPS62A06A

 TPS62A06, TPS62A06A
www.ti.com SLUSET0A – APRIL 2023 – REVISED JUNE 2023

Table 8-1. Power-Good indicator Functional Table

LOGIC SIGNALS
PG STATUS
VI EN PIN THERMAL SHUTDOWN VO

VO on target High Impedance

NO VO < target LOW

HIGH
VI > UVLO YES LOW

YES x LOW

UVLO < VI < 1.8 V x x LOW

VI < 1.8 V x x x Undefined

The PG indicator features a de-glitch to avoid the signal indicating glitches or transient responses from the loop
sketch the behavior.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: TPS62A06 TPS62A06A

TPS62A06, TPS62A06A
SLUSET0A – APRIL 2023 – REVISED JUNE 2023 www.ti.com

9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application
TPS62A06
L1 VOUT
0.22
H 1.2 V/ 6.0 A
VIN SW
2.5 V to 5.5 V VIN

R1
CIN 100 kΩ CFF COUT
22 F 3x22 F
GND FB

GND VPG
R2
R3 100 kΩ
EN PG

GND

Figure 9-1. TPS62A06 Typical Application Circuit

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1 as the input parameters
Table 9-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage 2.5 V to 5.5 V
Output voltage 1.2 V
Maximum output current 6.0 A

Table 9-2 lists the components used for the example.

Table 9-2. List of Components
(1)
REFERENCE DESCRIPTION MANUFACTURER
22 µF, Ceramic Capacitor, 10 V, X7R, size
C1 Murata
0805, GRM21BZ71A226KE15L
22 µF, Ceramic Capacitor, 10 V, X7R, size
C2, C3, C4 Murata
0805, GRM21BZ71A226KE15L
L1 0.22 µH, Power Inductor, XGL4015-221MEC Coilcraft
R1, R2 Chip resistor, 1%, size 0603 Std.
C5 Optional, 120 pF if needed Std.

(1) See the Third-Party Products Disclaimer.

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS62A06 TPS62A06A

 TPS62A06, TPS62A06A
www.ti.com SLUSET0A – APRIL 2023 – REVISED JUNE 2023

9.2.2 Detailed Design Procedure

9.2.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider according to Equation 2. To keep the feedback (FB) net
robust from noise, set R2 equal to or lower than 100 kΩ to have at least 6 µA of current in the voltage divider.
Lower values of FB resistors achieve better noise immunity, and lower light load efficiency, as explained in the
Design Considerations for a Resistive Feedback Divider in a DC/DC Converter technical brief.

VOUT VOUT
R1 = R2 × VFB − 1 = R2 × 0.6 V − 1 (2)

9.2.2.2 Feedforward Capacitor

TI recommends a feedforward capacitor CFF in parallel with R1 to improve the load transient performance and
reduce the output ripple voltage in PSM. The recommended value for CFF is 120 pF.
9.2.2.3 Output Filter Design
The inductor and output capacitor together provide a low-pass filter. To simplify this process, Table 9-3 outlines
possible inductor and capacitor value combinations. Checked cells represent combinations that are proven for
stability by simulation and lab test. Check further combinations for each individual application.
Table 9-3. Matrix of Output Capacitor and Inductor Combinations
COUT [µF](2)
VOUT [V] L [µH](1)
3 × 22 2 × 47 3 × 47

0.6 ≤ VOUT < 1.2 0.22 ++(3) ++

1.2 ≤ VOUT < 1.8 0.22 ++(3) + +

1.8 ≤ VOUT 0.22 ++(3) + +

(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and –30%.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and –50%.
(3) This LC combination is the standard value and recommended for most applications.

9.2.2.4 Input and Output Capacitor Selection

The architecture of the TPS62A0x allows use of tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep
resistance up to high frequencies and to achieve narrow capacitance variation with temperature, TI recommends
to use X7R or X5R dielectric.
The input capacitor is the low impedance energy source for the converter that helps provide stable operation.
TI recommends a low-ESR multilayer ceramic capacitor for best filtering. For most applications, a 10-μF input
capacitor is sufficient; a larger value reduces input voltage ripple.
The recommended typical output capacitor value for 1.2-V output typical application is 45 μF of effective
capacitance. This capacitance can vary over a wide range, as outlined in Table 9-3.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: TPS62A06 TPS62A06A

TPS62A06, TPS62A06A
SLUSET0A – APRIL 2023 – REVISED JUNE 2023 www.ti.com

9.2.3 Application Curves

VIN = 5.0 V, VOUT = 1.2 V, TA = 25°C, BOM = Table 9-2 unless otherwise noted.

100 100
95 95
90 90
85 85
Efficiency [%]

Efficiency [%]
80 80
75 75
70 70
65 65
60 60
VIN = 2.5 V VIN = 2.5 V
55 VIN = 3.3 V 55 VIN = 3.3 V
VIN = 5.0 V VIN = 5.0 V
50 50
1m 10m 100m 1 6 1m 10m 100m 1 6
Output Current [A] Output Current [A]

Figure 9-2. 0.6-V Output Efficiency (TPS62A06) Figure 9-3. 1.2-V Output Efficiency (TPS62A06)
100 100
95 95
90
90
85
85
80
Efficiency [%]

Efficiency [%]

80 75
75 70
70 65
60
65
55
60
VIN = 2.5 V 50 VIN = 2.5 V
55 VIN = 3.3 V 45 VIN = 3.3 V
VIN = 5.0 V VIN = 5.0 V
50 40
1m 10m 100m 1 6 0 1 2 3 4 5 6
Output Current [A] Output Current [A]

Figure 9-4. 1.8-V Output Efficiency (TPS62A06) Figure 9-5. 1.8-V Output Efficiency (TPS62A06A)

Load Current = 6 A Load Current = 100 mA

Figure 9-6. PWM Operation (TPS62A06) Figure 9-7. PFM Operation (TPS62A06)

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS62A06 TPS62A06A

 TPS62A06, TPS62A06A
www.ti.com SLUSET0A – APRIL 2023 – REVISED JUNE 2023

VOUT

PG

PG
IL
VOUT
IL
EN EN

Figure 9-8. Start-Up With No Load (TPS62A06) Figure 9-9. Shutdown With No Load (TPS62A06)

Load Step: 0.1 A to 6 A, 1 A/µs Load Step: 0.1 A to 6 A, 1 A/µs

Figure 9-10. Load Transient Response (TPS62A06) Figure 9-11. Load Transient Response
(TPS62A06A)
7 7
VOUT = 0.6 V VOUT = 0.6 V
VOUT = 0.9 V VOUT = 0.9 V
6 VOUT = 1.2 V 6 VOUT = 1.2 V
VOUT = 1.8 V VOUT = 1.8 V
VOUT = 3.3 V
Output Current [A]
Output Current [A]

5 5

4 4

3 3

2 2

1 1
60 65 70 75 80 85 90 95 100 105 110 115 120 60 65 70 75 80 85 90 95 100 105 110 115 120
Ambient Temperature [°C] Ambient Temperature [°C]
RθJA = 74.5°C/W TJmax = 125°C RθJA = 74.5°C/W TJmax = 125°C

Figure 9-12. Safe Operating Area Based On EVM, Figure 9-13. Safe Operating Area Based On EVM,
VIN = 5.0 V, TPS62A06DRL VIN = 3.3 V, TPS62A06DRL

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: TPS62A06 TPS62A06A

TPS62A06, TPS62A06A
SLUSET0A – APRIL 2023 – REVISED JUNE 2023 www.ti.com

9.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.5 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.
9.4 Layout
9.4.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TPS62A0x
device.
• Place the input and output capacitors and the inductor as close as possible to the IC. This action keeps
the power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• Connect the low side of the input and output capacitors properly to the GND pin to avoid a ground potential
shift.
• Take special care to avoid noise being induced. The sense traces connected to FB is a signal trace. Keep
these traces away from SW nodes.
• Use common ground. GND layers can be used for shielding.
See Figure 9-14 for the recommended PCB layout.
9.4.2 Layout Example

Figure 9-14. TPS62A06x PCB Layout Recommendation

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS62A06 TPS62A06A

 TPS62A06, TPS62A06A
www.ti.com SLUSET0A – APRIL 2023 – REVISED JUNE 2023

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Device Support

10.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Documentation Support
10.2.1 Related Documentation
Texas Instruments, Design Considerations for a Resistive Feedback Divider in a DC/DC Converter technical brief
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: TPS62A06 TPS62A06A

 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS62A06ADRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 1MH Samples

TPS62A06DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 1MG Samples

XPS62A06ADRLR ACTIVE SOT-5X3 DRL 6 4000 TBD Call TI Call TI -40 to 125 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2023

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Aug-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62A06ADRLR SOT-5X3 DRL 6 4000 180.0 8.4 2.0 1.8 0.75 4.0 8.0 Q3
TPS62A06DRLR SOT-5X3 DRL 6 4000 180.0 8.4 2.0 1.8 0.75 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Aug-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62A06ADRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0
TPS62A06DRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DRL0006A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
6

4X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 6X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
6X 0.05 C
0.08 SYMM

SYMM

0.27
6X
0.15
0.1 C A B
0.4
6X 0.05
0.2
4223266/C 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4223266/C 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4223266/C 12/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated