Fault Coverage

- Fault coverage is a measure of the effectiveness of a test in detecting faults in a design. It is

defined as the percentage of faults that can be detected by a given set of test cases.
- Type - Static Fault Coverage: Estimate of
coverage without actual testing.
o Dynamic Fault Coverage: Coverage
measured after actual test execution.
Yield
- Yield refers to the proportion of functional devices produced in a manufacturing process
compared to the total number of devices produced.
- Types - Manufacturing Yield: Ratio of defects to total devices produced.
o Test Yield: Ratio of
functional devices that
pass tests.
Rule of Ten
- The Rule of Ten states that the cost of fixing a defect increases tenfold at each subsequent
phase of the product development lifecycle.
- Cost Implications:
o Design Phase: Cost = x
o Implementation Phase: Cost = 10x/
o Post-Production: Cost = 100x
Observability
- Observability is the ability to observe the internal states of a system or component through its
outputs.
- Types - Full Observability: All internal states are observable through outputs.
o Partial Observability: Only some internal states are observable through outputs
Controllability
- Controllability refers to the ability to set the internal states of a system or component to
specific values using its inputs.
- Types - Full Controllability: All internal states can be controlled through inputs.
o Partial Controllability: Only some internal states can be controlled through inputs.
 Different scan cells.
1. D Flip-Flop (DFF) Scan Cell
2. Scan Latch
3. MUX-based Scan Cell
4. Dual-Edge Triggered Scan Cell
5. Scan-Based Test Cell
6. BIST (Built-In Self-Test) Scan Cell
Discussion on D Flip-Flop (DFF) Scan Cell
- A D Flip-Flop (DFF) scan cell is a modified sequential logic element designed for testing and
verification purposes. It allows for easy access to internal states by enabling test data to be
shifted into the flip-flop.
- Operation:
o Normal Mode: Captures data from the D input on the clock edge, producing an output (Q)
based on the D value.
o Test Mode: Allows test data to be shifted in through the scan input (SI) and shifted out
through the scan output (SO) for testing purposes.
- Benefits:
o Enhanced Testing: Simplifies the application of test patterns and increases fault coverage.
o Design for Testability (DFT): Commonly used technique that improves testing efficiency.
- Limitations:
o Area Overhead: Increases circuit area due to additional logic.
o Performance Impact: May slightly affect performance because of the extra routing and logic.
Importance of Scan Design Rules in DFT
- Scan design rules are essential for enhancing the testability of digital circuits by integrating scan
chains, which allow the easy control and observation of flip-flops. These rules make it possible to
detect faults in a circuit by providing a structured way to apply test inputs and observe outputs.
1. Increased Testability:
- Scan design allows each flip-flop to be controlled and observed during test mode, making it
easier to test internal states of the circuit.
2. Fault Detection:
- By connecting flip-flops in a serial fashion (scan chain), faults in combinational logic can be
detected more easily. Test patterns can be shifted into the circuit, and the resulting outputs can be
shifted out, revealing faults.
3. Improved Debugging:
- Debugging is simplified as specific parts of the circuit can be isolated and tested independently
by shifting in known test vectors and checking the outputs.
4. Easier Automation:
- Scan design rules make the testing process more automated, reducing manual intervention and
errors. This helps in running tests faster and on a large scale in manufacturing.
5. Example - D Flip-Flop (DFF) with Scan Chain:
- A MUX is added before each flip-flop to allow it to operate in two modes:
( I ) normal mode (for regular operation) & ( ii )scan mode (for testing). In scan mode, test data is
shifted through the flip-flops to test the circuit’s internal states efficiently.
[ normal input ] → (MUX) → (DFF) → [ Output/Scan out ]
scan input
Explain various bridging fault models
- when two or more signal lines in a circuit unintentionally connect (or "bridge") due to a defect,
such as a short circuit. These faults can significantly affect circuit behavior, making them
important in testing and verification.
1. Stuck-at Fault Model
- A stuck-at fault assumes that a signal line is permanently fixed at either a
logic '0' (stuck-at-0) or logic '1' (stuck-at-1).
- While primarily used for single-line faults, it can represent some bridging faults by
considering the fixed states of connected lines.
2. Single Bridging Fault
- A single bridging fault occurs when two lines are connected due to a defect. For instance, a
line that is supposed to be isolated is connected to another line.
- Ex: If lines A and B are bridged, and line A is driven high, line B may also unintentionally go
high, affecting the intended circuit logic.
- The goal is to determine if the fault can be detected by applying specific test vectors.
3. Multiple Bridging Faults
- Multiple bridging faults occur when more than two signal lines are connected together. This
can lead to more complex behavior and interactions.
- Ex: Lines A, B, and C are all bridged, leading to a more intricate set of potential outputs and
interactions with the circuit logic.
- Testing becomes more complex as multiple combinations of inputs must be considered to
detect the fault.
4. Coupling Faults
- Definition: Coupling faults are a type of bridging fault where the fault does not directly
create a path between two lines but allows for unintended interactions due to the electrical
coupling between them.
- Example: If line A transitions and induces a voltage change on line B without a direct
connection, this is a coupling fault.
- Testing: Requires different test strategies to capture the effects of the coupled lines.
5. Bridge Fault with Unknown State
- Definition: In this model, the faulted signal lines can be in an unknown state rather than
fixed at '0' or '1', leading to unpredictable circuit behavior.
- Testing: This model can complicate testing because it may require advanced fault simulation
to understand potential outcomes.
6. Resistive Bridging Faults
- Definition: These faults occur when a high-resistance path is formed between two lines
instead of a low-resistance path. This can lead to voltage drops rather than a full logic level
change.
- Example: If a weak bridge exists between lines, it might affect signal integrity without
creating a hard short.
- Testing: Special techniques may be needed to evaluate the performance under resistive
bridging conditions.
 Probability-Based Testability Analysis
- Probability-based testability analysis evaluates how easily faults in a circuit can be detected by
using controllability and observability measures
1. Controllability: Probability of setting the circuit's output to '1' or '0' by controlling the inputs.
2. Observability: Probability of detecting changes at the circuit's output when an internal signal
changes.
- 3-Input XOR Gate: Probability-Based Measures
the output is '1' when an odd number of inputs are '1' (Y= 0-1-1-0-1-0-0-1)
1. Controllability: odd number of inputs are '1'
o P(Output = 1)=0.5
o P(Output = 0)=0.5
2. Observability:
o The probability of a change in an input affecting the output is 0.75.
Ad Hoc Approach - Test Point Insertion (TPI) Technique
- Test Point Insertion (TPI) is a Design for Testability (DFT) technique used in digital circuits to
enhance fault detection. In the Ad Hoc approach, test points (additional signals) are manually
inserted into the circuit to improve observability and controllability of internal nodes.
Key Points
1. The main goal of TPI is to make internal signals more accessible during testing, which helps in
detecting faults more easily.
2. Types of Test Points:
- Control Points: Allow control of internal signals to set them to desired logic values ('0' or '1').
These are typically implemented using multiplexers or logic gates.
- Observation Points: Allow internal signals to be observed at the circuit's output. This makes it
easier to detect changes in the internal states that might otherwise be hidden.
3. Ad Hoc Approach:
- Test points are added manually based on the designer's experience and analysis of the circuit.
- There’s no systematic algorithm; instead, test points are placed where the designer believes
testing needs improvement, typically at hard-to-control or hard-to-observe nodes.
4. Advantages:
- Simple to implement.
- Improves fault coverage with minimal changes to the design.
5. Disadvantages:
- Not optimal, as manual placement may not cover all critical areas.
- Can introduce performance overhead (e.g., increased power, delay).
Transistor Faults in CMOS Circuits
- Transistor faults in CMOS circuits refer to defects or malfunctions in transistors that cause
deviations from normal circuit behavior. These faults can occur due to various reasons like
manufacturing defects, aging, or environmental stress.
1. Stuck-at faults: Transistors get stuck at logic '0' or '1.'
2. Open faults: Connection is broken, leading to an open circuit.
3. Short-Circuit Faults: A short circuit occurs when transistors are incorrectly connected,
causing a permanent path between VDD and GND.
4. Bridging Faults: Occurs when two transistors or signal lines that shouldn't be connected are
shorted.
Detecting Transistor Faults
1. Stuck-at testing: Apply input patterns and observe output behavior.
2. IDDQ testing: Check for abnormal power consumption, which indicates short circuits.
3. Scan chain testing: Used to observe internal states of the circuit.
2-Input CMOS NAND Gate
- A CMOS NAND gate consists of two PMOS transistors in parallel and two NMOS transistors in
series. The circuit outputs logic '1' unless both inputs are '1', in which case the output is '0'.
- Transistor Layout for a 2-Input NAND Gate:
o PMOS: Connected to VDD, turns on when the input is '0'. A B Y
o NMOS: Connected to GND, turns on when the input is '1'. --> 0 0 1
0 1 1
Detecting Transistor Faults in 2-Input CMOS NAND Gate 1 0 1
- To detect faults in this NAND gate, test patterns need to be applied to 1 1 0
each transistor configuration:
1. Stuck-At Fault Detection:
- Apply inputs '0 0': Both PMOS should turn on, and the output should be '1'. If any of the
NMOS transistors are stuck-at '1', the output might be '0' due to failure to disconnect GND.
- Apply inputs '1 1': Both NMOS should turn on, and PMOS should turn off, leading to an
output '0'. If one of the PMOS transistors is stuck-at '1', the output will not go to '0'.
2. Open Fault Detection:
- Open faults can be detected using current monitoring methods like IDDQ testing. If there's
no current flow where it should be, an open fault may be present in the circuit.
3. Short-Circuit Fault Detection:
- If the PMOS and NMOS transistors short together, the output may be stuck at an undefined
voltage. This can be detected through abnormal power consumption and improper output.

Cmos circuit -----------------

PMOS1 and PMOS2 handle the high-output logic ('1'), while NMOS1 and NMOS2 deal with low-
output logic ('0').
 Stuck-at Faults in Circuits
- Stuck-at faults occur when a signal or node in a circuit is permanently stuck at logic '0' (stuck-at-
0) or logic '1' (stuck-at-1), regardless of the input signals. This can happen due to manufacturing
defects, damage, or aging of the circuit, preventing proper operation.
- Detecting Stuck-at Faults
o Apply specific test input patterns.
o Compare the actual output to the expected output.
o A mismatch indicates a stuck-at fault.
- 2-to-1 Multiplexer (MUX)
1. Stuck-at-0 on Input A:
- Apply test pattern: S = 0, A = 1, B = 0.
- Expected output: Y = 1 (since A is selected when S = 0).
- If the output is 0, it means A is stuck-at-0, as it should have been selected and set Y to '1'.
2. Stuck-at-1 on Select Line (S):
- Apply test pattern: S = 0, A = 1, B = 0.
- Expected output: Y = 1 (A should be selected).
- If the output is 0, it indicates that S is stuck-at-1, causing the MUX to always select input B.
3. Stuck-at-1 on Output (Y):
- Apply test pattern: S = 0, A = 0, B = 0.
- Expected output: Y = 0.
- If the output remains 1, this suggests the output node Y is stuck-at-1.

Scan Design
- Scan design is a DFT technique used to improve the testability of sequential circuits. It works
by converting flip-flops into scan cells, which are connected to form a scan chain. This
allows easy control and observation of internal states during testing.
Key Steps in Scan Design:
1. Modify flip-flops: Convert regular flip-flops into scan flip-flops with additional inputs for scanning
test data in and out.
2. Form scan chains: Connect the scan flip-flops in a series, creating a scan chain. The flip-flops act as
shift registers during test mode, allowing test patterns to be loaded and results to be shifted out.
3. Shift and capture: In test mode, input test vectors are shifted into the scan chain, and circuit
behavior is observed by capturing the output at different stages.
Advantages of Scan Design:
1. Improves fault detection: Makes it easier to test complex sequential circuits.
2. Simplifies testing: Converts sequential problems into combinational ones by controlling and
observing flip-flop states.
3. Reduces complexity: Increases controllability & observability, making it easier to diagnose faults.
4. Increases Controllability and Observability:
5. Works with ATPG (Automatic Test Pattern Generation):
Example of Scan Desig 1.A set of flip-flops is modified to work in scan mode.
2.The flip-flops are connected in a chain during the test mode.